Patrick Georgi | afd4c87 | 2020-05-05 23:43:18 +0200 | [diff] [blame] | 1 | /* Memory information */ |
Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 2 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Kane Chen | 33faac6 | 2014-07-27 12:54:44 -0700 | [diff] [blame] | 3 | |
| 4 | #ifndef _MEMORY_INFO_H_ |
| 5 | #define _MEMORY_INFO_H_ |
| 6 | |
Barnali Sarkar | c16d389 | 2017-02-23 16:56:54 +0530 | [diff] [blame] | 7 | #include <stdint.h> |
| 8 | |
Raul E Rangel | 99f54a6 | 2018-04-11 10:58:14 -0600 | [diff] [blame] | 9 | #define DIMM_INFO_SERIAL_SIZE 4 |
Aaron Durbin | 4b6f262 | 2018-10-09 07:31:24 -0600 | [diff] [blame] | 10 | #define DIMM_INFO_PART_NUMBER_SIZE 33 |
Johnny Lin | d8740c3 | 2022-05-04 15:16:16 +0800 | [diff] [blame] | 11 | #define DIMM_INFO_TOTAL 32 |
Richard Spiegel | bd65480 | 2018-02-22 10:03:39 -0700 | [diff] [blame] | 12 | |
Raul E Rangel | 5041e9b | 2018-03-20 12:37:27 -0600 | [diff] [blame] | 13 | /** |
Kane Chen | 33faac6 | 2014-07-27 12:54:44 -0700 | [diff] [blame] | 14 | * If this table is filled and put in CBMEM, |
| 15 | * then these info in CBMEM will be used to generate smbios type 17 table |
Raul E Rangel | 5041e9b | 2018-03-20 12:37:27 -0600 | [diff] [blame] | 16 | * |
| 17 | * Values are specified according to the JEDEC SPD Standard. |
Kane Chen | 33faac6 | 2014-07-27 12:54:44 -0700 | [diff] [blame] | 18 | */ |
| 19 | struct dimm_info { |
Raul E Rangel | 5041e9b | 2018-03-20 12:37:27 -0600 | [diff] [blame] | 20 | /* |
| 21 | * Size of the module in MiB. |
| 22 | */ |
Kane Chen | 33faac6 | 2014-07-27 12:54:44 -0700 | [diff] [blame] | 23 | uint32_t dimm_size; |
Raul E Rangel | 5041e9b | 2018-03-20 12:37:27 -0600 | [diff] [blame] | 24 | /* |
| 25 | * SMBIOS (not SPD) device type. |
| 26 | * |
Elyes HAOUAS | 28114ae | 2018-11-14 17:51:00 +0100 | [diff] [blame] | 27 | * See the smbios.h smbios_memory_type enum. |
Raul E Rangel | 5041e9b | 2018-03-20 12:37:27 -0600 | [diff] [blame] | 28 | */ |
Kane Chen | 33faac6 | 2014-07-27 12:54:44 -0700 | [diff] [blame] | 29 | uint16_t ddr_type; |
Rob Barnes | 327f105 | 2020-09-01 10:26:57 -0600 | [diff] [blame] | 30 | /* |
| 31 | * ddr_frequency is deprecated. |
| 32 | * Use max_speed_mts and configured_speed_mts instead. |
| 33 | */ |
Kane Chen | 33faac6 | 2014-07-27 12:54:44 -0700 | [diff] [blame] | 34 | uint16_t ddr_frequency; |
| 35 | uint8_t rank_per_dimm; |
David Milosevic | 6be82a4 | 2022-10-18 19:17:19 +0200 | [diff] [blame] | 36 | /* |
Tim Chu | d292c4f | 2022-12-12 07:50:19 +0000 | [diff] [blame] | 37 | * Socket-ID |
| 38 | */ |
| 39 | uint8_t soc_num; |
| 40 | /* |
David Milosevic | 6be82a4 | 2022-10-18 19:17:19 +0200 | [diff] [blame] | 41 | * Memory-Controller-ID |
| 42 | */ |
| 43 | uint8_t ctrlr_num; |
| 44 | /* |
| 45 | * Channel-ID |
| 46 | */ |
Kane Chen | 33faac6 | 2014-07-27 12:54:44 -0700 | [diff] [blame] | 47 | uint8_t channel_num; |
David Milosevic | 6be82a4 | 2022-10-18 19:17:19 +0200 | [diff] [blame] | 48 | /* |
| 49 | * DIMM-ID |
| 50 | */ |
Kane Chen | 33faac6 | 2014-07-27 12:54:44 -0700 | [diff] [blame] | 51 | uint8_t dimm_num; |
| 52 | uint8_t bank_locator; |
Raul E Rangel | 5041e9b | 2018-03-20 12:37:27 -0600 | [diff] [blame] | 53 | /* |
Raul E Rangel | 99f54a6 | 2018-04-11 10:58:14 -0600 | [diff] [blame] | 54 | * SPD serial number. |
Raul E Rangel | 5041e9b | 2018-03-20 12:37:27 -0600 | [diff] [blame] | 55 | */ |
Richard Spiegel | bd65480 | 2018-02-22 10:03:39 -0700 | [diff] [blame] | 56 | uint8_t serial[DIMM_INFO_SERIAL_SIZE]; |
Raul E Rangel | 5041e9b | 2018-03-20 12:37:27 -0600 | [diff] [blame] | 57 | /* |
| 58 | * The last byte is '\0' for the end of string |
| 59 | * |
| 60 | * Must contain only printable ASCII. |
| 61 | */ |
Richard Spiegel | bd65480 | 2018-02-22 10:03:39 -0700 | [diff] [blame] | 62 | uint8_t module_part_number[DIMM_INFO_PART_NUMBER_SIZE]; |
Raul E Rangel | 5041e9b | 2018-03-20 12:37:27 -0600 | [diff] [blame] | 63 | /* |
| 64 | * SPD Manufacturer ID |
| 65 | */ |
Kane Chen | 33faac6 | 2014-07-27 12:54:44 -0700 | [diff] [blame] | 66 | uint16_t mod_id; |
Raul E Rangel | 5041e9b | 2018-03-20 12:37:27 -0600 | [diff] [blame] | 67 | /* |
| 68 | * SPD Module Type. |
| 69 | * |
| 70 | * See spd.h for valid values. |
| 71 | * |
| 72 | * e.g., SPD_RDIMM, SPD_SODIMM, SPD_MICRO_DIMM |
| 73 | */ |
Kane Chen | 33faac6 | 2014-07-27 12:54:44 -0700 | [diff] [blame] | 74 | uint8_t mod_type; |
Raul E Rangel | 5041e9b | 2018-03-20 12:37:27 -0600 | [diff] [blame] | 75 | /* |
| 76 | * SPD bus width. |
| 77 | * |
| 78 | * Bits 0 - 2 encode the primary bus width: |
| 79 | * 0b000 = 8 bit width |
| 80 | * 0b001 = 16 bit width |
| 81 | * 0b010 = 32 bit width |
| 82 | * 0b011 = 64 bit width |
| 83 | * |
| 84 | * Bits 3 - 4 encode the extension bits (ECC): |
| 85 | * 0b00 = 0 extension bits |
| 86 | * 0b01 = 8 bit of ECC |
| 87 | * |
| 88 | * e.g., |
| 89 | * 64 bit bus with 8 bits of ECC (72 bits total): 0b1011 |
| 90 | * 64 bit bus with 0 bits of ECC (64 bits total): 0b0011 |
| 91 | * |
| 92 | * See the smbios.h smbios_memory_bus_width enum. |
| 93 | */ |
Kane Chen | 33faac6 | 2014-07-27 12:54:44 -0700 | [diff] [blame] | 94 | uint8_t bus_width; |
Christian Walter | f972322 | 2019-05-28 10:37:24 +0200 | [diff] [blame] | 95 | /* |
| 96 | * Voltage Level |
| 97 | */ |
| 98 | uint16_t vdd_voltage; |
Rob Barnes | 327f105 | 2020-09-01 10:26:57 -0600 | [diff] [blame] | 99 | /* |
| 100 | * Max speed in MT/s |
| 101 | * If the value is 0, ddr_frequency should be used instead. |
| 102 | */ |
| 103 | uint16_t max_speed_mts; |
| 104 | /* |
| 105 | * Configured speed in MT/s |
| 106 | * If the value is 0, ddr_frequency should be used instead. |
| 107 | */ |
| 108 | uint16_t configured_speed_mts; |
Stefan Reinauer | 6a00113 | 2017-07-13 02:20:27 +0200 | [diff] [blame] | 109 | } __packed; |
Kane Chen | 33faac6 | 2014-07-27 12:54:44 -0700 | [diff] [blame] | 110 | |
| 111 | struct memory_info { |
Angel Pons | 6724ba4 | 2021-01-31 15:06:59 +0100 | [diff] [blame] | 112 | /* |
| 113 | * SMBIOS error correction type. |
| 114 | * See the smbios.h smbios_memory_array_ecc enum. |
| 115 | */ |
| 116 | uint8_t ecc_type; |
Patrick Rudolph | 5e00780 | 2020-07-27 15:37:43 +0200 | [diff] [blame] | 117 | /* Maximum capacity the DRAM controller/mainboard supports */ |
| 118 | uint32_t max_capacity_mib; |
| 119 | /* Maximum number of DIMMs the DRAM controller/mainboard supports */ |
| 120 | uint16_t number_of_devices; |
| 121 | |
| 122 | /* active DIMM configuration */ |
Kane Chen | 33faac6 | 2014-07-27 12:54:44 -0700 | [diff] [blame] | 123 | uint8_t dimm_cnt; |
Richard Spiegel | bd65480 | 2018-02-22 10:03:39 -0700 | [diff] [blame] | 124 | struct dimm_info dimm[DIMM_INFO_TOTAL]; |
Stefan Reinauer | 6a00113 | 2017-07-13 02:20:27 +0200 | [diff] [blame] | 125 | } __packed; |
Kane Chen | 33faac6 | 2014-07-27 12:54:44 -0700 | [diff] [blame] | 126 | |
Nick Vaccaro | 3b24bb6 | 2020-09-30 13:05:09 -0700 | [diff] [blame] | 127 | /* |
| 128 | * mainboard_get_dram_part_num returns a DRAM part number override string |
| 129 | * return NULL = no part number override provided by mainboard |
| 130 | * return non-NULL = pointer to a string terminating in '\0' |
| 131 | */ |
| 132 | const char *mainboard_get_dram_part_num(void); |
Kane Chen | 33faac6 | 2014-07-27 12:54:44 -0700 | [diff] [blame] | 133 | #endif |