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Patrick Georgiafd4c872020-05-05 23:43:18 +02001/* Memory information */
Patrick Georgiac959032020-05-05 22:49:26 +02002/* SPDX-License-Identifier: GPL-2.0-only */
Kane Chen33faac62014-07-27 12:54:44 -07003
4#ifndef _MEMORY_INFO_H_
5#define _MEMORY_INFO_H_
6
Barnali Sarkarc16d3892017-02-23 16:56:54 +05307#include <stdint.h>
Patrick Rudolph5e007802020-07-27 15:37:43 +02008#include <stdbool.h>
Barnali Sarkarc16d3892017-02-23 16:56:54 +05309
Raul E Rangel99f54a62018-04-11 10:58:14 -060010#define DIMM_INFO_SERIAL_SIZE 4
Aaron Durbin4b6f2622018-10-09 07:31:24 -060011#define DIMM_INFO_PART_NUMBER_SIZE 33
Richard Spiegelbd654802018-02-22 10:03:39 -070012#define DIMM_INFO_TOTAL 8 /* Maximum num of dimm is 8 */
13
Raul E Rangel5041e9b2018-03-20 12:37:27 -060014/**
Kane Chen33faac62014-07-27 12:54:44 -070015 * If this table is filled and put in CBMEM,
16 * then these info in CBMEM will be used to generate smbios type 17 table
Raul E Rangel5041e9b2018-03-20 12:37:27 -060017 *
18 * Values are specified according to the JEDEC SPD Standard.
Kane Chen33faac62014-07-27 12:54:44 -070019 */
20struct dimm_info {
Raul E Rangel5041e9b2018-03-20 12:37:27 -060021 /*
22 * Size of the module in MiB.
23 */
Kane Chen33faac62014-07-27 12:54:44 -070024 uint32_t dimm_size;
Raul E Rangel5041e9b2018-03-20 12:37:27 -060025 /*
26 * SMBIOS (not SPD) device type.
27 *
Elyes HAOUAS28114ae2018-11-14 17:51:00 +010028 * See the smbios.h smbios_memory_type enum.
Raul E Rangel5041e9b2018-03-20 12:37:27 -060029 */
Kane Chen33faac62014-07-27 12:54:44 -070030 uint16_t ddr_type;
Rob Barnes327f1052020-09-01 10:26:57 -060031 /*
32 * ddr_frequency is deprecated.
33 * Use max_speed_mts and configured_speed_mts instead.
34 */
Kane Chen33faac62014-07-27 12:54:44 -070035 uint16_t ddr_frequency;
36 uint8_t rank_per_dimm;
37 uint8_t channel_num;
38 uint8_t dimm_num;
39 uint8_t bank_locator;
Raul E Rangel5041e9b2018-03-20 12:37:27 -060040 /*
Raul E Rangel99f54a62018-04-11 10:58:14 -060041 * SPD serial number.
Raul E Rangel5041e9b2018-03-20 12:37:27 -060042 */
Richard Spiegelbd654802018-02-22 10:03:39 -070043 uint8_t serial[DIMM_INFO_SERIAL_SIZE];
Raul E Rangel5041e9b2018-03-20 12:37:27 -060044 /*
45 * The last byte is '\0' for the end of string
46 *
47 * Must contain only printable ASCII.
48 */
Richard Spiegelbd654802018-02-22 10:03:39 -070049 uint8_t module_part_number[DIMM_INFO_PART_NUMBER_SIZE];
Raul E Rangel5041e9b2018-03-20 12:37:27 -060050 /*
51 * SPD Manufacturer ID
52 */
Kane Chen33faac62014-07-27 12:54:44 -070053 uint16_t mod_id;
Raul E Rangel5041e9b2018-03-20 12:37:27 -060054 /*
55 * SPD Module Type.
56 *
57 * See spd.h for valid values.
58 *
59 * e.g., SPD_RDIMM, SPD_SODIMM, SPD_MICRO_DIMM
60 */
Kane Chen33faac62014-07-27 12:54:44 -070061 uint8_t mod_type;
Raul E Rangel5041e9b2018-03-20 12:37:27 -060062 /*
63 * SPD bus width.
64 *
65 * Bits 0 - 2 encode the primary bus width:
66 * 0b000 = 8 bit width
67 * 0b001 = 16 bit width
68 * 0b010 = 32 bit width
69 * 0b011 = 64 bit width
70 *
71 * Bits 3 - 4 encode the extension bits (ECC):
72 * 0b00 = 0 extension bits
73 * 0b01 = 8 bit of ECC
74 *
75 * e.g.,
76 * 64 bit bus with 8 bits of ECC (72 bits total): 0b1011
77 * 64 bit bus with 0 bits of ECC (64 bits total): 0b0011
78 *
79 * See the smbios.h smbios_memory_bus_width enum.
80 */
Kane Chen33faac62014-07-27 12:54:44 -070081 uint8_t bus_width;
Christian Walterf9723222019-05-28 10:37:24 +020082 /*
83 * Voltage Level
84 */
85 uint16_t vdd_voltage;
Rob Barnes327f1052020-09-01 10:26:57 -060086 /*
87 * Max speed in MT/s
88 * If the value is 0, ddr_frequency should be used instead.
89 */
90 uint16_t max_speed_mts;
91 /*
92 * Configured speed in MT/s
93 * If the value is 0, ddr_frequency should be used instead.
94 */
95 uint16_t configured_speed_mts;
Stefan Reinauer6a001132017-07-13 02:20:27 +020096} __packed;
Kane Chen33faac62014-07-27 12:54:44 -070097
98struct memory_info {
Angel Pons6724ba42021-01-31 15:06:59 +010099 /*
100 * SMBIOS error correction type.
101 * See the smbios.h smbios_memory_array_ecc enum.
102 */
103 uint8_t ecc_type;
Patrick Rudolph5e007802020-07-27 15:37:43 +0200104 /* Maximum capacity the DRAM controller/mainboard supports */
105 uint32_t max_capacity_mib;
106 /* Maximum number of DIMMs the DRAM controller/mainboard supports */
107 uint16_t number_of_devices;
108
109 /* active DIMM configuration */
Kane Chen33faac62014-07-27 12:54:44 -0700110 uint8_t dimm_cnt;
Richard Spiegelbd654802018-02-22 10:03:39 -0700111 struct dimm_info dimm[DIMM_INFO_TOTAL];
Stefan Reinauer6a001132017-07-13 02:20:27 +0200112} __packed;
Kane Chen33faac62014-07-27 12:54:44 -0700113
Nick Vaccaro3b24bb62020-09-30 13:05:09 -0700114/*
115 * mainboard_get_dram_part_num returns a DRAM part number override string
116 * return NULL = no part number override provided by mainboard
117 * return non-NULL = pointer to a string terminating in '\0'
118 */
119const char *mainboard_get_dram_part_num(void);
Kane Chen33faac62014-07-27 12:54:44 -0700120#endif