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Patrick Georgiafd4c872020-05-05 23:43:18 +02001/* Memory information */
Patrick Georgiac959032020-05-05 22:49:26 +02002/* SPDX-License-Identifier: GPL-2.0-only */
Kane Chen33faac62014-07-27 12:54:44 -07003
4#ifndef _MEMORY_INFO_H_
5#define _MEMORY_INFO_H_
6
Barnali Sarkarc16d3892017-02-23 16:56:54 +05307#include <stdint.h>
8
Raul E Rangel99f54a62018-04-11 10:58:14 -06009#define DIMM_INFO_SERIAL_SIZE 4
Aaron Durbin4b6f2622018-10-09 07:31:24 -060010#define DIMM_INFO_PART_NUMBER_SIZE 33
Richard Spiegelbd654802018-02-22 10:03:39 -070011#define DIMM_INFO_TOTAL 8 /* Maximum num of dimm is 8 */
12
Raul E Rangel5041e9b2018-03-20 12:37:27 -060013/**
Kane Chen33faac62014-07-27 12:54:44 -070014 * If this table is filled and put in CBMEM,
15 * then these info in CBMEM will be used to generate smbios type 17 table
Raul E Rangel5041e9b2018-03-20 12:37:27 -060016 *
17 * Values are specified according to the JEDEC SPD Standard.
Kane Chen33faac62014-07-27 12:54:44 -070018 */
19struct dimm_info {
Raul E Rangel5041e9b2018-03-20 12:37:27 -060020 /*
21 * Size of the module in MiB.
22 */
Kane Chen33faac62014-07-27 12:54:44 -070023 uint32_t dimm_size;
Raul E Rangel5041e9b2018-03-20 12:37:27 -060024 /*
25 * SMBIOS (not SPD) device type.
26 *
Elyes HAOUAS28114ae2018-11-14 17:51:00 +010027 * See the smbios.h smbios_memory_type enum.
Raul E Rangel5041e9b2018-03-20 12:37:27 -060028 */
Kane Chen33faac62014-07-27 12:54:44 -070029 uint16_t ddr_type;
30 uint16_t ddr_frequency;
31 uint8_t rank_per_dimm;
32 uint8_t channel_num;
33 uint8_t dimm_num;
34 uint8_t bank_locator;
Raul E Rangel5041e9b2018-03-20 12:37:27 -060035 /*
Raul E Rangel99f54a62018-04-11 10:58:14 -060036 * SPD serial number.
Raul E Rangel5041e9b2018-03-20 12:37:27 -060037 */
Richard Spiegelbd654802018-02-22 10:03:39 -070038 uint8_t serial[DIMM_INFO_SERIAL_SIZE];
Raul E Rangel5041e9b2018-03-20 12:37:27 -060039 /*
40 * The last byte is '\0' for the end of string
41 *
42 * Must contain only printable ASCII.
43 */
Richard Spiegelbd654802018-02-22 10:03:39 -070044 uint8_t module_part_number[DIMM_INFO_PART_NUMBER_SIZE];
Raul E Rangel5041e9b2018-03-20 12:37:27 -060045 /*
46 * SPD Manufacturer ID
47 */
Kane Chen33faac62014-07-27 12:54:44 -070048 uint16_t mod_id;
Raul E Rangel5041e9b2018-03-20 12:37:27 -060049 /*
50 * SPD Module Type.
51 *
52 * See spd.h for valid values.
53 *
54 * e.g., SPD_RDIMM, SPD_SODIMM, SPD_MICRO_DIMM
55 */
Kane Chen33faac62014-07-27 12:54:44 -070056 uint8_t mod_type;
Raul E Rangel5041e9b2018-03-20 12:37:27 -060057 /*
58 * SPD bus width.
59 *
60 * Bits 0 - 2 encode the primary bus width:
61 * 0b000 = 8 bit width
62 * 0b001 = 16 bit width
63 * 0b010 = 32 bit width
64 * 0b011 = 64 bit width
65 *
66 * Bits 3 - 4 encode the extension bits (ECC):
67 * 0b00 = 0 extension bits
68 * 0b01 = 8 bit of ECC
69 *
70 * e.g.,
71 * 64 bit bus with 8 bits of ECC (72 bits total): 0b1011
72 * 64 bit bus with 0 bits of ECC (64 bits total): 0b0011
73 *
74 * See the smbios.h smbios_memory_bus_width enum.
75 */
Kane Chen33faac62014-07-27 12:54:44 -070076 uint8_t bus_width;
Christian Walterf9723222019-05-28 10:37:24 +020077 /*
78 * Voltage Level
79 */
80 uint16_t vdd_voltage;
Stefan Reinauer6a001132017-07-13 02:20:27 +020081} __packed;
Kane Chen33faac62014-07-27 12:54:44 -070082
83struct memory_info {
84 uint8_t dimm_cnt;
Richard Spiegelbd654802018-02-22 10:03:39 -070085 struct dimm_info dimm[DIMM_INFO_TOTAL];
Stefan Reinauer6a001132017-07-13 02:20:27 +020086} __packed;
Kane Chen33faac62014-07-27 12:54:44 -070087
88#endif