Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Ronald G. Minnich | 4f78b18 | 2013-04-17 16:57:30 -0700 | [diff] [blame] | 4 | * Copyright 2012 Google Inc. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
Patrick Georgi | b890a12 | 2015-03-26 15:17:45 +0100 | [diff] [blame] | 17 | * Foundation, Inc. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 18 | */ |
| 19 | |
| 20 | #include <arch/io.h> |
| 21 | #include <console/console.h> |
Kyösti Mälkki | ab56b3b | 2013-11-28 16:44:51 +0200 | [diff] [blame] | 22 | #include <bootmode.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 23 | #include <delay.h> |
| 24 | #include <device/device.h> |
| 25 | #include <device/pci.h> |
| 26 | #include <device/pci_ids.h> |
Ronald G. Minnich | 5bcca7e | 2013-06-25 15:56:46 -0700 | [diff] [blame] | 27 | #include <drivers/intel/gma/i915_reg.h> |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 28 | #include <drivers/intel/gma/i915.h> |
Duncan Laurie | 356833d | 2013-07-09 15:40:27 -0700 | [diff] [blame] | 29 | #include <cpu/intel/haswell/haswell.h> |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 30 | #include <stdlib.h> |
Ronald G. Minnich | 9518b56 | 2013-09-19 16:45:22 -0700 | [diff] [blame] | 31 | #include <string.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 32 | |
| 33 | #include "chip.h" |
| 34 | #include "haswell.h" |
| 35 | |
Furquan Shaikh | cb61ea7 | 2013-08-15 15:23:58 -0700 | [diff] [blame] | 36 | #if CONFIG_CHROMEOS |
| 37 | #include <vendorcode/google/chromeos/chromeos.h> |
| 38 | #endif |
| 39 | |
Duncan Laurie | 356833d | 2013-07-09 15:40:27 -0700 | [diff] [blame] | 40 | struct gt_reg { |
| 41 | u32 reg; |
| 42 | u32 andmask; |
| 43 | u32 ormask; |
| 44 | }; |
| 45 | |
| 46 | static const struct gt_reg haswell_gt_setup[] = { |
| 47 | /* Enable Counters */ |
| 48 | { 0x0a248, 0x00000000, 0x00000016 }, |
| 49 | { 0x0a000, 0x00000000, 0x00070020 }, |
| 50 | { 0x0a180, 0xff3fffff, 0x15000000 }, |
| 51 | /* Enable DOP Clock Gating */ |
| 52 | { 0x09424, 0x00000000, 0x000003fd }, |
| 53 | /* Enable Unit Level Clock Gating */ |
| 54 | { 0x09400, 0x00000000, 0x00000080 }, |
| 55 | { 0x09404, 0x00000000, 0x40401000 }, |
| 56 | { 0x09408, 0x00000000, 0x00000000 }, |
| 57 | { 0x0940c, 0x00000000, 0x02000001 }, |
| 58 | { 0x0a008, 0x00000000, 0x08000000 }, |
| 59 | /* Wake Rate Limits */ |
| 60 | { 0x0a090, 0xffffffff, 0x00000000 }, |
| 61 | { 0x0a098, 0xffffffff, 0x03e80000 }, |
| 62 | { 0x0a09c, 0xffffffff, 0x00280000 }, |
| 63 | { 0x0a0a8, 0xffffffff, 0x0001e848 }, |
| 64 | { 0x0a0ac, 0xffffffff, 0x00000019 }, |
| 65 | /* Render/Video/Blitter Idle Max Count */ |
| 66 | { 0x02054, 0x00000000, 0x0000000a }, |
| 67 | { 0x12054, 0x00000000, 0x0000000a }, |
| 68 | { 0x22054, 0x00000000, 0x0000000a }, |
| 69 | /* RC Sleep / RCx Thresholds */ |
| 70 | { 0x0a0b0, 0xffffffff, 0x00000000 }, |
| 71 | { 0x0a0b4, 0xffffffff, 0x000003e8 }, |
| 72 | { 0x0a0b8, 0xffffffff, 0x0000c350 }, |
| 73 | /* RP Settings */ |
| 74 | { 0x0a010, 0xffffffff, 0x000f4240 }, |
| 75 | { 0x0a014, 0xffffffff, 0x12060000 }, |
| 76 | { 0x0a02c, 0xffffffff, 0x0000e808 }, |
| 77 | { 0x0a030, 0xffffffff, 0x0003bd08 }, |
| 78 | { 0x0a068, 0xffffffff, 0x000101d0 }, |
| 79 | { 0x0a06c, 0xffffffff, 0x00055730 }, |
| 80 | { 0x0a070, 0xffffffff, 0x0000000a }, |
| 81 | /* RP Control */ |
| 82 | { 0x0a024, 0x00000000, 0x00000b92 }, |
| 83 | /* HW RC6 Control */ |
| 84 | { 0x0a090, 0x00000000, 0x88040000 }, |
| 85 | /* Video Frequency Request */ |
| 86 | { 0x0a00c, 0x00000000, 0x08000000 }, |
| 87 | { 0 }, |
| 88 | }; |
| 89 | |
| 90 | static const struct gt_reg haswell_gt_lock[] = { |
| 91 | { 0x0a248, 0xffffffff, 0x80000000 }, |
| 92 | { 0x0a004, 0xffffffff, 0x00000010 }, |
| 93 | { 0x0a080, 0xffffffff, 0x00000004 }, |
| 94 | { 0x0a180, 0xffffffff, 0x80000000 }, |
| 95 | { 0 }, |
| 96 | }; |
| 97 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 98 | /* some vga option roms are used for several chipsets but they only have one |
| 99 | * PCI ID in their header. If we encounter such an option rom, we need to do |
| 100 | * the mapping ourselfes |
| 101 | */ |
| 102 | |
| 103 | u32 map_oprom_vendev(u32 vendev) |
| 104 | { |
| 105 | u32 new_vendev=vendev; |
| 106 | |
| 107 | switch (vendev) { |
Aaron Durbin | 7116129 | 2012-12-13 16:43:32 -0600 | [diff] [blame] | 108 | case 0x80860402: /* GT1 Desktop */ |
| 109 | case 0x80860406: /* GT1 Mobile */ |
| 110 | case 0x8086040a: /* GT1 Server */ |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 111 | case 0x80860a06: /* GT1 ULT */ |
Aaron Durbin | 7116129 | 2012-12-13 16:43:32 -0600 | [diff] [blame] | 112 | |
| 113 | case 0x80860412: /* GT2 Desktop */ |
| 114 | case 0x80860416: /* GT2 Mobile */ |
| 115 | case 0x8086041a: /* GT2 Server */ |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 116 | case 0x80860a16: /* GT2 ULT */ |
Aaron Durbin | 7116129 | 2012-12-13 16:43:32 -0600 | [diff] [blame] | 117 | |
| 118 | case 0x80860422: /* GT3 Desktop */ |
| 119 | case 0x80860426: /* GT3 Mobile */ |
| 120 | case 0x8086042a: /* GT3 Server */ |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 121 | case 0x80860a26: /* GT3 ULT */ |
Aaron Durbin | 7116129 | 2012-12-13 16:43:32 -0600 | [diff] [blame] | 122 | |
| 123 | new_vendev=0x80860406; /* GT1 Mobile */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 124 | break; |
| 125 | } |
| 126 | |
| 127 | return new_vendev; |
| 128 | } |
| 129 | |
Ronald G. Minnich | 4c8465c | 2013-09-30 15:57:21 -0700 | [diff] [blame] | 130 | /* GTT is the Global Translation Table for the graphics pipeline. |
| 131 | * It is used to translate graphics addresses to physical |
| 132 | * memory addresses. As in the CPU, GTTs map 4K pages. |
| 133 | * The setgtt function adds a further bit of flexibility: |
| 134 | * it allows you to set a range (the first two parameters) to point |
| 135 | * to a physical address (third parameter);the physical address is |
| 136 | * incremented by a count (fourth parameter) for each GTT in the |
| 137 | * range. |
| 138 | * Why do it this way? For ultrafast startup, |
| 139 | * we can point all the GTT entries to point to one page, |
| 140 | * and set that page to 0s: |
| 141 | * memset(physbase, 0, 4096); |
| 142 | * setgtt(0, 4250, physbase, 0); |
| 143 | * this takes about 2 ms, and is a win because zeroing |
| 144 | * the page takes a up to 200 ms. |
| 145 | * This call sets the GTT to point to a linear range of pages |
| 146 | * starting at physbase. |
| 147 | */ |
| 148 | |
| 149 | #define GTT_PTE_BASE (2 << 20) |
| 150 | |
| 151 | void |
| 152 | set_translation_table(int start, int end, u64 base, int inc) |
| 153 | { |
| 154 | int i; |
| 155 | |
| 156 | for(i = start; i < end; i++){ |
| 157 | u64 physical_address = base + i*inc; |
| 158 | /* swizzle the 32:39 bits to 4:11 */ |
| 159 | u32 word = physical_address | ((physical_address >> 28) & 0xff0) | 1; |
| 160 | /* note: we've confirmed by checking |
| 161 | * the values that mrc does no |
| 162 | * useful setup before we run this. |
| 163 | */ |
| 164 | gtt_write(GTT_PTE_BASE + i * 4, word); |
| 165 | gtt_read(GTT_PTE_BASE + i * 4); |
| 166 | } |
| 167 | } |
| 168 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 169 | static struct resource *gtt_res = NULL; |
| 170 | |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 171 | u32 gtt_read(u32 reg) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 172 | { |
Ronald G. Minnich | 9518b56 | 2013-09-19 16:45:22 -0700 | [diff] [blame] | 173 | u32 val; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 174 | val = read32(res2mmio(gtt_res, reg, 0)); |
Ronald G. Minnich | 9518b56 | 2013-09-19 16:45:22 -0700 | [diff] [blame] | 175 | return val; |
| 176 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 177 | } |
| 178 | |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 179 | void gtt_write(u32 reg, u32 data) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 180 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 181 | write32(res2mmio(gtt_res, reg, 0), data); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 182 | } |
| 183 | |
Duncan Laurie | 356833d | 2013-07-09 15:40:27 -0700 | [diff] [blame] | 184 | static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask) |
| 185 | { |
| 186 | u32 val = gtt_read(reg); |
| 187 | val &= andmask; |
| 188 | val |= ormask; |
| 189 | gtt_write(reg, val); |
| 190 | } |
| 191 | |
| 192 | static inline void gtt_write_regs(const struct gt_reg *gt) |
| 193 | { |
| 194 | for (; gt && gt->reg; gt++) { |
| 195 | if (gt->andmask) |
| 196 | gtt_rmw(gt->reg, gt->andmask, gt->ormask); |
| 197 | else |
| 198 | gtt_write(gt->reg, gt->ormask); |
| 199 | } |
| 200 | } |
| 201 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 202 | #define GTT_RETRY 1000 |
Ronald G. Minnich | 9518b56 | 2013-09-19 16:45:22 -0700 | [diff] [blame] | 203 | int gtt_poll(u32 reg, u32 mask, u32 value) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 204 | { |
| 205 | unsigned try = GTT_RETRY; |
| 206 | u32 data; |
| 207 | |
| 208 | while (try--) { |
| 209 | data = gtt_read(reg); |
| 210 | if ((data & mask) == value) |
| 211 | return 1; |
| 212 | udelay(10); |
| 213 | } |
| 214 | |
| 215 | printk(BIOS_ERR, "GT init timeout\n"); |
| 216 | return 0; |
| 217 | } |
| 218 | |
Ronald G. Minnich | 5bcca7e | 2013-06-25 15:56:46 -0700 | [diff] [blame] | 219 | static void power_well_enable(void) |
| 220 | { |
| 221 | gtt_write(HSW_PWR_WELL_CTL1, HSW_PWR_WELL_ENABLE); |
| 222 | gtt_poll(HSW_PWR_WELL_CTL1, HSW_PWR_WELL_STATE, HSW_PWR_WELL_STATE); |
Ronald G. Minnich | 9518b56 | 2013-09-19 16:45:22 -0700 | [diff] [blame] | 223 | #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT |
| 224 | /* In the native graphics case, we've got about 20 ms. |
| 225 | * after we power up the the AUX channel until we can talk to it. |
| 226 | * So get that going right now. We can't turn on the panel, yet, just VDD. |
| 227 | */ |
| 228 | gtt_write(PCH_PP_CONTROL, PCH_PP_UNLOCK| EDP_FORCE_VDD | PANEL_POWER_RESET); |
| 229 | #endif |
Ronald G. Minnich | 5bcca7e | 2013-06-25 15:56:46 -0700 | [diff] [blame] | 230 | } |
| 231 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 232 | static void gma_pm_init_pre_vbios(struct device *dev) |
| 233 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 234 | printk(BIOS_DEBUG, "GT Power Management Init\n"); |
| 235 | |
| 236 | gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 237 | if (!gtt_res || !gtt_res->base) |
| 238 | return; |
| 239 | |
Ronald G. Minnich | 5bcca7e | 2013-06-25 15:56:46 -0700 | [diff] [blame] | 240 | power_well_enable(); |
| 241 | |
Duncan Laurie | 67113e9 | 2013-01-10 13:23:04 -0800 | [diff] [blame] | 242 | /* |
| 243 | * Enable RC6 |
| 244 | */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 245 | |
Duncan Laurie | 67113e9 | 2013-01-10 13:23:04 -0800 | [diff] [blame] | 246 | /* Enable Force Wake */ |
| 247 | gtt_write(0x0a180, 1 << 5); |
| 248 | gtt_write(0x0a188, 0x00010001); |
Edward O'Callaghan | 986e85c | 2014-10-29 12:15:34 +1100 | [diff] [blame] | 249 | gtt_poll(FORCEWAKE_ACK_HSW, 1 << 0, 1 << 0); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 250 | |
Duncan Laurie | 356833d | 2013-07-09 15:40:27 -0700 | [diff] [blame] | 251 | /* GT Settings */ |
| 252 | gtt_write_regs(haswell_gt_setup); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 253 | |
Duncan Laurie | 356833d | 2013-07-09 15:40:27 -0700 | [diff] [blame] | 254 | /* Wait for Mailbox Ready */ |
| 255 | gtt_poll(0x138124, (1 << 31), (0 << 31)); |
| 256 | /* Mailbox Data - RC6 VIDS */ |
| 257 | gtt_write(0x138128, 0x00000000); |
| 258 | /* Mailbox Command */ |
| 259 | gtt_write(0x138124, 0x80000004); |
| 260 | /* Wait for Mailbox Ready */ |
| 261 | gtt_poll(0x138124, (1 << 31), (0 << 31)); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 262 | |
Duncan Laurie | 356833d | 2013-07-09 15:40:27 -0700 | [diff] [blame] | 263 | /* Enable PM Interrupts */ |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 264 | gtt_write(GEN6_PMIER, GEN6_PM_MBOX_EVENT | GEN6_PM_THERMAL_EVENT | |
| 265 | GEN6_PM_RP_DOWN_TIMEOUT | GEN6_PM_RP_UP_THRESHOLD | |
| 266 | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_UP_EI_EXPIRED | |
| 267 | GEN6_PM_RP_DOWN_EI_EXPIRED); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 268 | |
Duncan Laurie | 67113e9 | 2013-01-10 13:23:04 -0800 | [diff] [blame] | 269 | /* Enable RC6 in idle */ |
| 270 | gtt_write(0x0a094, 0x00040000); |
Duncan Laurie | 356833d | 2013-07-09 15:40:27 -0700 | [diff] [blame] | 271 | |
| 272 | /* PM Lock Settings */ |
| 273 | gtt_write_regs(haswell_gt_lock); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 274 | } |
| 275 | |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 276 | static void init_display_planes(void) |
| 277 | { |
| 278 | int pipe, plane; |
| 279 | |
| 280 | /* Disable cursor mode */ |
| 281 | for (pipe = PIPE_A; pipe <= PIPE_C; pipe++) { |
| 282 | gtt_write(CURCNTR_IVB(pipe), CURSOR_MODE_DISABLE); |
| 283 | gtt_write(CURBASE_IVB(pipe), 0x00000000); |
| 284 | } |
| 285 | |
| 286 | /* Disable primary plane and set surface base address*/ |
| 287 | for (plane = PLANE_A; plane <= PLANE_C; plane++) { |
| 288 | gtt_write(DSPCNTR(plane), DISPLAY_PLANE_DISABLE); |
| 289 | gtt_write(DSPSURF(plane), 0x00000000); |
| 290 | } |
| 291 | |
| 292 | /* Disable VGA display */ |
| 293 | gtt_write(CPU_VGACNTRL, CPU_VGA_DISABLE); |
| 294 | } |
| 295 | |
Duncan Laurie | c7f2ab7 | 2013-05-28 07:49:09 -0700 | [diff] [blame] | 296 | static void gma_setup_panel(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 297 | { |
| 298 | struct northbridge_intel_haswell_config *conf = dev->chip_info; |
| 299 | u32 reg32; |
| 300 | |
| 301 | printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n"); |
| 302 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 303 | /* Setup Digital Port Hotplug */ |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 304 | reg32 = gtt_read(PCH_PORT_HOTPLUG); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 305 | if (!reg32) { |
| 306 | reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2; |
| 307 | reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10; |
| 308 | reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18; |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 309 | gtt_write(PCH_PORT_HOTPLUG, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 310 | } |
| 311 | |
| 312 | /* Setup Panel Power On Delays */ |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 313 | reg32 = gtt_read(PCH_PP_ON_DELAYS); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 314 | if (!reg32) { |
| 315 | reg32 = (conf->gpu_panel_port_select & 0x3) << 30; |
| 316 | reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; |
| 317 | reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 318 | gtt_write(PCH_PP_ON_DELAYS, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 319 | } |
| 320 | |
| 321 | /* Setup Panel Power Off Delays */ |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 322 | reg32 = gtt_read(PCH_PP_OFF_DELAYS); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 323 | if (!reg32) { |
| 324 | reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; |
| 325 | reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 326 | gtt_write(PCH_PP_OFF_DELAYS, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 327 | } |
| 328 | |
| 329 | /* Setup Panel Power Cycle Delay */ |
| 330 | if (conf->gpu_panel_power_cycle_delay) { |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 331 | reg32 = gtt_read(PCH_PP_DIVISOR); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 332 | reg32 &= ~0xff; |
| 333 | reg32 |= conf->gpu_panel_power_cycle_delay & 0xff; |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 334 | gtt_write(PCH_PP_DIVISOR, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 335 | } |
| 336 | |
| 337 | /* Enable Backlight if needed */ |
| 338 | if (conf->gpu_cpu_backlight) { |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 339 | gtt_write(BLC_PWM_CPU_CTL2, BLC_PWM2_ENABLE); |
| 340 | gtt_write(BLC_PWM_CPU_CTL, conf->gpu_cpu_backlight); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 341 | } |
| 342 | if (conf->gpu_pch_backlight) { |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 343 | gtt_write(BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE); |
| 344 | gtt_write(BLC_PWM_PCH_CTL2, conf->gpu_pch_backlight); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 345 | } |
Ronald G. Minnich | 5bcca7e | 2013-06-25 15:56:46 -0700 | [diff] [blame] | 346 | |
| 347 | /* Get display,pipeline,and DDI registers into a basic sane state */ |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 348 | power_well_enable(); |
| 349 | |
| 350 | init_display_planes(); |
| 351 | |
| 352 | /* DDI-A params set: |
| 353 | bit 0: Display detected (RO) |
| 354 | bit 4: DDI A supports 4 lanes and DDI E is not used |
| 355 | bit 7: DDI buffer is idle |
| 356 | */ |
| 357 | gtt_write(DDI_BUF_CTL_A, DDI_BUF_IS_IDLE | DDI_A_4_LANES | DDI_INIT_DISPLAY_DETECTED); |
| 358 | |
| 359 | /* Set FDI registers - is this required? */ |
Ronald G. Minnich | 5bcca7e | 2013-06-25 15:56:46 -0700 | [diff] [blame] | 360 | gtt_write(_FDI_RXA_MISC, 0x00200090); |
| 361 | gtt_write(_FDI_RXA_MISC, 0x0a000000); |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 362 | |
| 363 | /* Enable the handshake with PCH display when processing reset */ |
| 364 | gtt_write(NDE_RSTWRN_OPT, RST_PCH_HNDSHK_EN); |
| 365 | |
| 366 | /* undocumented */ |
Ronald G. Minnich | 5bcca7e | 2013-06-25 15:56:46 -0700 | [diff] [blame] | 367 | gtt_write(0x42090, 0x04000000); |
Ronald G. Minnich | 5bcca7e | 2013-06-25 15:56:46 -0700 | [diff] [blame] | 368 | gtt_write(0x9840, 0x00000000); |
| 369 | gtt_write(0x42090, 0xa4000000); |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 370 | |
| 371 | gtt_write(SOUTH_DSPCLK_GATE_D, PCH_LP_PARTITION_LEVEL_DISABLE); |
| 372 | |
| 373 | /* undocumented */ |
Ronald G. Minnich | 5bcca7e | 2013-06-25 15:56:46 -0700 | [diff] [blame] | 374 | gtt_write(0x42080, 0x00004000); |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 375 | |
| 376 | /* Prepare DDI buffers for DP and FDI */ |
| 377 | intel_prepare_ddi(); |
| 378 | |
| 379 | /* Hot plug detect buffer enabled for port A */ |
| 380 | gtt_write(DIGITAL_PORT_HOTPLUG_CNTRL, DIGITAL_PORTA_HOTPLUG_ENABLE); |
| 381 | |
| 382 | /* Enable HPD buffer for digital port D and B */ |
| 383 | gtt_write(PCH_PORT_HOTPLUG, PORTD_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE); |
| 384 | |
| 385 | /* Bits 4:0 - Power cycle delay (default 0x6 --> 500ms) |
| 386 | Bits 31:8 - Reference divider (0x0004af ----> 24MHz) |
| 387 | */ |
Ronald G. Minnich | 5bcca7e | 2013-06-25 15:56:46 -0700 | [diff] [blame] | 388 | gtt_write(PCH_PP_DIVISOR, 0x0004af06); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 389 | } |
| 390 | |
Duncan Laurie | c7f2ab7 | 2013-05-28 07:49:09 -0700 | [diff] [blame] | 391 | static void gma_pm_init_post_vbios(struct device *dev) |
| 392 | { |
Duncan Laurie | 356833d | 2013-07-09 15:40:27 -0700 | [diff] [blame] | 393 | int cdclk = 0; |
| 394 | int devid = pci_read_config16(dev, PCI_DEVICE_ID); |
| 395 | int gpu_is_ulx = 0; |
| 396 | |
| 397 | if (devid == 0x0a0e || devid == 0x0a1e) |
| 398 | gpu_is_ulx = 1; |
| 399 | |
| 400 | /* CD Frequency */ |
Duncan Laurie | 3106d0f | 2013-08-12 13:51:22 -0700 | [diff] [blame] | 401 | if ((gtt_read(0x42014) & 0x1000000) || gpu_is_ulx || haswell_is_ult()) |
| 402 | cdclk = 0; /* fixed frequency */ |
| 403 | else |
| 404 | cdclk = 2; /* variable frequency */ |
Duncan Laurie | 356833d | 2013-07-09 15:40:27 -0700 | [diff] [blame] | 405 | |
Duncan Laurie | 356833d | 2013-07-09 15:40:27 -0700 | [diff] [blame] | 406 | if (gpu_is_ulx || cdclk != 0) |
| 407 | gtt_rmw(0x130040, 0xf7ffffff, 0x04000000); |
| 408 | else |
| 409 | gtt_rmw(0x130040, 0xf3ffffff, 0x00000000); |
| 410 | |
| 411 | /* More magic */ |
| 412 | if (haswell_is_ult() || gpu_is_ulx) { |
Duncan Laurie | 3106d0f | 2013-08-12 13:51:22 -0700 | [diff] [blame] | 413 | if (!gpu_is_ulx) |
Duncan Laurie | 356833d | 2013-07-09 15:40:27 -0700 | [diff] [blame] | 414 | gtt_write(0x138128, 0x00000000); |
| 415 | else |
| 416 | gtt_write(0x138128, 0x00000001); |
| 417 | gtt_write(0x13812c, 0x00000000); |
| 418 | gtt_write(0x138124, 0x80000017); |
| 419 | } |
| 420 | |
Duncan Laurie | c7f2ab7 | 2013-05-28 07:49:09 -0700 | [diff] [blame] | 421 | /* Disable Force Wake */ |
| 422 | gtt_write(0x0a188, 0x00010000); |
Edward O'Callaghan | 986e85c | 2014-10-29 12:15:34 +1100 | [diff] [blame] | 423 | gtt_poll(FORCEWAKE_ACK_HSW, 1 << 0, 0 << 0); |
Duncan Laurie | 356833d | 2013-07-09 15:40:27 -0700 | [diff] [blame] | 424 | gtt_write(0x0a188, 0x00000001); |
Duncan Laurie | c7f2ab7 | 2013-05-28 07:49:09 -0700 | [diff] [blame] | 425 | } |
| 426 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 427 | static void gma_func0_init(struct device *dev) |
| 428 | { |
Ronald G. Minnich | 3a75e5e | 2013-10-28 15:01:54 -0700 | [diff] [blame] | 429 | #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT |
| 430 | struct northbridge_intel_haswell_config *conf = dev->chip_info; |
| 431 | struct intel_dp dp; |
| 432 | #endif |
| 433 | |
Ronald G. Minnich | 4f78b18 | 2013-04-17 16:57:30 -0700 | [diff] [blame] | 434 | int lightup_ok = 0; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 435 | u32 reg32; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 436 | /* IGD needs to be Bus Master */ |
| 437 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 438 | reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; |
| 439 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 440 | |
| 441 | /* Init graphics power management */ |
| 442 | gma_pm_init_pre_vbios(dev); |
| 443 | |
Duncan Laurie | c7f2ab7 | 2013-05-28 07:49:09 -0700 | [diff] [blame] | 444 | /* Post VBIOS init */ |
| 445 | gma_setup_panel(dev); |
| 446 | |
Ronald G. Minnich | 2a66d6b | 2013-03-28 17:01:43 -0700 | [diff] [blame] | 447 | #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT |
| 448 | printk(BIOS_SPEW, "NATIVE graphics, run native enable\n"); |
Furquan Shaikh | cb61ea7 | 2013-08-15 15:23:58 -0700 | [diff] [blame] | 449 | /* Default set to 1 since it might be required for |
| 450 | stuff like seabios */ |
| 451 | unsigned int init_fb = 1; |
Ronald G. Minnich | 3a75e5e | 2013-10-28 15:01:54 -0700 | [diff] [blame] | 452 | |
| 453 | /* the BAR for graphics space is a well known number for |
| 454 | * sandy and ivy. And the resource code renumbers it. |
| 455 | * So it's almost like having two hardcodes. |
| 456 | */ |
| 457 | dp.graphics = (void *)((uintptr_t)dev->resource_list[1].base); |
| 458 | dp.physbase = pci_read_config32(dev, 0x5c) & ~0xf; |
| 459 | dp.panel_power_down_delay = conf->gpu_panel_power_down_delay; |
| 460 | dp.panel_power_up_delay = conf->gpu_panel_power_up_delay; |
| 461 | dp.panel_power_cycle_delay = conf->gpu_panel_power_cycle_delay; |
| 462 | |
Furquan Shaikh | cb61ea7 | 2013-08-15 15:23:58 -0700 | [diff] [blame] | 463 | #ifdef CONFIG_CHROMEOS |
| 464 | init_fb = developer_mode_enabled() || recovery_mode_enabled(); |
| 465 | #endif |
Ronald G. Minnich | 3a75e5e | 2013-10-28 15:01:54 -0700 | [diff] [blame] | 466 | lightup_ok = panel_lightup(&dp, init_fb); |
Kyösti Mälkki | ab56b3b | 2013-11-28 16:44:51 +0200 | [diff] [blame] | 467 | gfx_set_init_done(1); |
Ronald G. Minnich | 2a66d6b | 2013-03-28 17:01:43 -0700 | [diff] [blame] | 468 | #endif |
Ronald G. Minnich | 4f78b18 | 2013-04-17 16:57:30 -0700 | [diff] [blame] | 469 | if (! lightup_ok) { |
| 470 | printk(BIOS_SPEW, "FUI did not run; using VBIOS\n"); |
Stefan Reinauer | f1aabec | 2014-01-22 15:16:30 -0800 | [diff] [blame] | 471 | mdelay(CONFIG_PRE_GRAPHICS_DELAY); |
Ronald G. Minnich | 4f78b18 | 2013-04-17 16:57:30 -0700 | [diff] [blame] | 472 | pci_dev_init(dev); |
| 473 | } |
| 474 | |
| 475 | /* Post VBIOS init */ |
| 476 | gma_pm_init_post_vbios(dev); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 477 | } |
| 478 | |
| 479 | static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 480 | { |
| 481 | if (!vendor || !device) { |
| 482 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 483 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 484 | } else { |
| 485 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 486 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 487 | } |
| 488 | } |
| 489 | |
| 490 | static struct pci_operations gma_pci_ops = { |
| 491 | .set_subsystem = gma_set_subsystem, |
| 492 | }; |
| 493 | |
| 494 | static struct device_operations gma_func0_ops = { |
Vladimir Serbinenko | 30fe612 | 2014-02-05 23:25:28 +0100 | [diff] [blame] | 495 | .read_resources = pci_dev_read_resources, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 496 | .set_resources = pci_dev_set_resources, |
| 497 | .enable_resources = pci_dev_enable_resources, |
| 498 | .init = gma_func0_init, |
| 499 | .scan_bus = 0, |
| 500 | .enable = 0, |
| 501 | .ops_pci = &gma_pci_ops, |
| 502 | }; |
| 503 | |
Duncan Laurie | df7be71 | 2012-12-17 11:22:57 -0800 | [diff] [blame] | 504 | static const unsigned short pci_device_ids[] = { |
| 505 | 0x0402, /* Desktop GT1 */ |
| 506 | 0x0412, /* Desktop GT2 */ |
| 507 | 0x0422, /* Desktop GT3 */ |
| 508 | 0x0406, /* Mobile GT1 */ |
| 509 | 0x0416, /* Mobile GT2 */ |
| 510 | 0x0426, /* Mobile GT3 */ |
| 511 | 0x0d16, /* Mobile 4+3 GT1 */ |
| 512 | 0x0d26, /* Mobile 4+3 GT2 */ |
| 513 | 0x0d36, /* Mobile 4+3 GT3 */ |
| 514 | 0x0a06, /* ULT GT1 */ |
| 515 | 0x0a16, /* ULT GT2 */ |
| 516 | 0x0a26, /* ULT GT3 */ |
| 517 | 0, |
| 518 | }; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 519 | |
| 520 | static const struct pci_driver pch_lpc __pci_driver = { |
| 521 | .ops = &gma_func0_ops, |
| 522 | .vendor = PCI_VENDOR_ID_INTEL, |
| 523 | .devices = pci_device_ids, |
| 524 | }; |