Gitiles
Code Review Sign In
review.coreboot.org / coreboot / f362bbd5c7ce5d96f4bed3adee9a8f3ccc2728e8 / . / src / security / tpm / Makefile.inc
blob: ade96569408be6076571f1f07f8c641e2ba91be2 [file] [log] [blame]
Martin Rothf362bbd2023-08-04 12:24:24 -0600[diff] [blame^]1## SPDX-License-Identifier: GPL-2.0-only
2
Jes B. Klinkec6b041a12022-04-19 14:00:33 -0700[diff] [blame]3subdirs-$(CONFIG_TPM_GOOGLE) += tss/vendor/cr50
Philipp Deppenwiesec07f8fb2018-02-27 19:40:52 +0100[diff] [blame]4
Philipp Deppenwiese86391f12017-10-18 21:54:24 +0200[diff] [blame]5## TSS
6
Philipp Deppenwiesec07f8fb2018-02-27 19:40:52 +0100[diff] [blame]7ifeq ($(CONFIG_TPM1),y)
Philipp Deppenwiese64e2d192017-10-18 17:13:07 +0200[diff] [blame]8
Philipp Deppenwiesec07f8fb2018-02-27 19:40:52 +0100[diff] [blame]9ramstage-y += tss/tcg-1.2/tss.c
10romstage-y += tss/tcg-1.2/tss.c
Bill XIEc79e96b2019-08-22 20:28:36 +0800[diff] [blame]11bootblock-y += tss/tcg-1.2/tss.c
12verstage-y += tss/tcg-1.2/tss.c
13postcar-y += tss/tcg-1.2/tss.c
Philipp Deppenwiesec07f8fb2018-02-27 19:40:52 +0100[diff] [blame]14
15## TSPI
16
Philipp Deppenwiesec9b7d1f2018-11-10 00:35:02 +0100[diff] [blame]17ramstage-y += tspi/tspi.c
18romstage-y += tspi/tspi.c
Bill XIEc79e96b2019-08-22 20:28:36 +0800[diff] [blame]19bootblock-y += tspi/tspi.c
20verstage-y += tspi/tspi.c
21postcar-y += tspi/tspi.c
Philipp Deppenwiesec07f8fb2018-02-27 19:40:52 +0100[diff] [blame]22
23endif # CONFIG_TPM1
24
25ifeq ($(CONFIG_TPM2),y)
26
27ramstage-y += tss/tcg-2.0/tss_marshaling.c
28ramstage-y += tss/tcg-2.0/tss.c
29
30romstage-y += tss/tcg-2.0/tss_marshaling.c
31romstage-y += tss/tcg-2.0/tss.c
32
33verstage-$(CONFIG_VBOOT) += tss/tcg-2.0/tss_marshaling.c
34verstage-$(CONFIG_VBOOT) += tss/tcg-2.0/tss.c
35
Frans Hendriks7c05d2a62019-06-13 15:46:12 +0200[diff] [blame]36postcar-y += tss/tcg-2.0/tss_marshaling.c
37postcar-y += tss/tcg-2.0/tss.c
Philipp Deppenwiesec07f8fb2018-02-27 19:40:52 +0100[diff] [blame]38
Bill XIEc79e96b2019-08-22 20:28:36 +0800[diff] [blame]39bootblock-y += tss/tcg-2.0/tss_marshaling.c
40bootblock-y += tss/tcg-2.0/tss.c
41
Philipp Deppenwiesec07f8fb2018-02-27 19:40:52 +0100[diff] [blame]42## TSPI
43
Philipp Deppenwiesec9b7d1f2018-11-10 00:35:02 +0100[diff] [blame]44ramstage-y += tspi/tspi.c
45romstage-y += tspi/tspi.c
Bill XIEc79e96b2019-08-22 20:28:36 +0800[diff] [blame]46bootblock-y += tspi/tspi.c
Philipp Deppenwiesec9b7d1f2018-11-10 00:35:02 +0100[diff] [blame]47verstage-$(CONFIG_VBOOT) += tspi/tspi.c
Bill XIEc79e96b2019-08-22 20:28:36 +0800[diff] [blame]48postcar-y += tspi/tspi.c
Philipp Deppenwiesec07f8fb2018-02-27 19:40:52 +0100[diff] [blame]49
50endif # CONFIG_TPM2
Bill XIEc79e96b2019-08-22 20:28:36 +0800[diff] [blame]51
52ifeq ($(CONFIG_TPM_MEASURED_BOOT),y)
53
54bootblock-y += tspi/crtm.c
55verstage-y += tspi/crtm.c
56romstage-y += tspi/crtm.c
57ramstage-y += tspi/crtm.c
58postcar-y += tspi/crtm.c
59
Sergii Dmytruk97fe17f2022-10-23 00:24:37 +0300[diff] [blame]60ramstage-$(CONFIG_TPM_LOG_CB) += tspi/log.c
61romstage-$(CONFIG_TPM_LOG_CB) += tspi/log.c
62verstage-$(CONFIG_TPM_LOG_CB) += tspi/log.c
63postcar-$(CONFIG_TPM_LOG_CB) += tspi/log.c
64bootblock-$(CONFIG_TPM_LOG_CB) += tspi/log.c
Bill XIEc79e96b2019-08-22 20:28:36 +0800[diff] [blame]65
Sergii Dmytruk4191dbf2022-10-23 00:34:32 +0300[diff] [blame]66ramstage-$(CONFIG_TPM_LOG_TPM1) += tspi/log-tpm1.c
67romstage-$(CONFIG_TPM_LOG_TPM1) += tspi/log-tpm1.c
68verstage-$(CONFIG_TPM_LOG_TPM1) += tspi/log-tpm1.c
69postcar-$(CONFIG_TPM_LOG_TPM1) += tspi/log-tpm1.c
70bootblock-$(CONFIG_TPM_LOG_TPM1) += tspi/log-tpm1.c
71
Sergii Dmytruk53db6772022-10-23 00:47:55 +0300[diff] [blame]72ramstage-$(CONFIG_TPM_LOG_TPM2) += tspi/log-tpm2.c
73romstage-$(CONFIG_TPM_LOG_TPM2) += tspi/log-tpm2.c
74verstage-$(CONFIG_TPM_LOG_TPM2) += tspi/log-tpm2.c
75postcar-$(CONFIG_TPM_LOG_TPM2) += tspi/log-tpm2.c
76bootblock-$(CONFIG_TPM_LOG_TPM2) += tspi/log-tpm2.c
77
Bill XIEc79e96b2019-08-22 20:28:36 +0800[diff] [blame]78endif # CONFIG_TPM_MEASURED_BOOT