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review.coreboot.org / coreboot / 7c05d2a6411ed11fa98fb7e85725c0b5dc82c442 / . / src / security / tpm / Makefile.inc
blob: a2d32cff8917a580384a6272d77939c4ee9100d6 [file] [log] [blame]
Philipp Deppenwiesec07f8fb2018-02-27 19:40:52 +0100[diff] [blame]1subdirs-$(CONFIG_TPM_CR50) += tss/vendor/cr50
2
Philipp Deppenwiese86391f12017-10-18 21:54:24 +0200[diff] [blame]3## TSS
4
Philipp Deppenwiesec07f8fb2018-02-27 19:40:52 +0100[diff] [blame]5ifeq ($(CONFIG_TPM1),y)
Philipp Deppenwiese64e2d192017-10-18 17:13:07 +0200[diff] [blame]6
Philipp Deppenwiesec07f8fb2018-02-27 19:40:52 +0100[diff] [blame]7ramstage-y += tss/tcg-1.2/tss.c
8romstage-y += tss/tcg-1.2/tss.c
Philipp Deppenwiese64e2d192017-10-18 17:13:07 +0200[diff] [blame]9
Philipp Deppenwiesec07f8fb2018-02-27 19:40:52 +0100[diff] [blame]10verstage-$(CONFIG_VBOOT) += tss/tcg-1.2/tss.c
11postcar-$(CONFIG_VBOOT) += tss/tcg-1.2/tss.c
12
13## TSPI
14
Philipp Deppenwiesec9b7d1f2018-11-10 00:35:02 +0100[diff] [blame]15ramstage-y += tspi/tspi.c
16romstage-y += tspi/tspi.c
Philipp Deppenwiesec07f8fb2018-02-27 19:40:52 +0100[diff] [blame]17
Philipp Deppenwiesec9b7d1f2018-11-10 00:35:02 +0100[diff] [blame]18verstage-$(CONFIG_VBOOT) += tspi/tspi.c
19postcar-$(CONFIG_VBOOT) += tspi/tspi.c
20
21ramstage-$(CONFIG_VBOOT_MEASURED_BOOT) += tspi/log.c
22romstage-$(CONFIG_VBOOT_MEASURED_BOOT) += tspi/log.c
23verstage-$(CONFIG_VBOOT_MEASURED_BOOT) += tspi/log.c
24postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += tspi/log.c
Philipp Deppenwiesec07f8fb2018-02-27 19:40:52 +0100[diff] [blame]25
26endif # CONFIG_TPM1
27
28ifeq ($(CONFIG_TPM2),y)
29
30ramstage-y += tss/tcg-2.0/tss_marshaling.c
31ramstage-y += tss/tcg-2.0/tss.c
32
33romstage-y += tss/tcg-2.0/tss_marshaling.c
34romstage-y += tss/tcg-2.0/tss.c
35
36verstage-$(CONFIG_VBOOT) += tss/tcg-2.0/tss_marshaling.c
37verstage-$(CONFIG_VBOOT) += tss/tcg-2.0/tss.c
38
Frans Hendriks7c05d2a62019-06-13 15:46:12 +0200[diff] [blame^]39postcar-y += tss/tcg-2.0/tss_marshaling.c
40postcar-y += tss/tcg-2.0/tss.c
Philipp Deppenwiesec07f8fb2018-02-27 19:40:52 +0100[diff] [blame]41
42## TSPI
43
Philipp Deppenwiesec9b7d1f2018-11-10 00:35:02 +0100[diff] [blame]44ramstage-y += tspi/tspi.c
45romstage-y += tspi/tspi.c
Philipp Deppenwiesec07f8fb2018-02-27 19:40:52 +0100[diff] [blame]46
Philipp Deppenwiesec9b7d1f2018-11-10 00:35:02 +0100[diff] [blame]47verstage-$(CONFIG_VBOOT) += tspi/tspi.c
48postcar-$(CONFIG_VBOOT) += tspi/tspi.c
49
50ramstage-$(CONFIG_VBOOT_MEASURED_BOOT) += tspi/log.c
51romstage-$(CONFIG_VBOOT_MEASURED_BOOT) += tspi/log.c
52verstage-$(CONFIG_VBOOT_MEASURED_BOOT) += tspi/log.c
53postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += tspi/log.c
Philipp Deppenwiesec07f8fb2018-02-27 19:40:52 +0100[diff] [blame]54
55endif # CONFIG_TPM2