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review.coreboot.org / coreboot / 53db677586e3e7c4a874f1ef16f34a6d01c269a0 / . / src / security / tpm / Makefile.inc
blob: ae06cb0ea6ce7a6c9a1c931b082f502404ec1cec [file] [log] [blame]
Jes B. Klinkec6b041a12022-04-19 14:00:33 -0700[diff] [blame]1subdirs-$(CONFIG_TPM_GOOGLE) += tss/vendor/cr50
Philipp Deppenwiesec07f8fb2018-02-27 19:40:52 +0100[diff] [blame]2
Philipp Deppenwiese86391f12017-10-18 21:54:24 +0200[diff] [blame]3## TSS
4
Philipp Deppenwiesec07f8fb2018-02-27 19:40:52 +0100[diff] [blame]5ifeq ($(CONFIG_TPM1),y)
Philipp Deppenwiese64e2d192017-10-18 17:13:07 +0200[diff] [blame]6
Philipp Deppenwiesec07f8fb2018-02-27 19:40:52 +0100[diff] [blame]7ramstage-y += tss/tcg-1.2/tss.c
8romstage-y += tss/tcg-1.2/tss.c
Bill XIEc79e96b2019-08-22 20:28:36 +0800[diff] [blame]9bootblock-y += tss/tcg-1.2/tss.c
10verstage-y += tss/tcg-1.2/tss.c
11postcar-y += tss/tcg-1.2/tss.c
Philipp Deppenwiesec07f8fb2018-02-27 19:40:52 +0100[diff] [blame]12
13## TSPI
14
Philipp Deppenwiesec9b7d1f2018-11-10 00:35:02 +0100[diff] [blame]15ramstage-y += tspi/tspi.c
16romstage-y += tspi/tspi.c
Bill XIEc79e96b2019-08-22 20:28:36 +0800[diff] [blame]17bootblock-y += tspi/tspi.c
18verstage-y += tspi/tspi.c
19postcar-y += tspi/tspi.c
Philipp Deppenwiesec07f8fb2018-02-27 19:40:52 +0100[diff] [blame]20
21endif # CONFIG_TPM1
22
23ifeq ($(CONFIG_TPM2),y)
24
25ramstage-y += tss/tcg-2.0/tss_marshaling.c
26ramstage-y += tss/tcg-2.0/tss.c
27
28romstage-y += tss/tcg-2.0/tss_marshaling.c
29romstage-y += tss/tcg-2.0/tss.c
30
31verstage-$(CONFIG_VBOOT) += tss/tcg-2.0/tss_marshaling.c
32verstage-$(CONFIG_VBOOT) += tss/tcg-2.0/tss.c
33
Frans Hendriks7c05d2a62019-06-13 15:46:12 +0200[diff] [blame]34postcar-y += tss/tcg-2.0/tss_marshaling.c
35postcar-y += tss/tcg-2.0/tss.c
Philipp Deppenwiesec07f8fb2018-02-27 19:40:52 +0100[diff] [blame]36
Bill XIEc79e96b2019-08-22 20:28:36 +0800[diff] [blame]37bootblock-y += tss/tcg-2.0/tss_marshaling.c
38bootblock-y += tss/tcg-2.0/tss.c
39
Philipp Deppenwiesec07f8fb2018-02-27 19:40:52 +0100[diff] [blame]40## TSPI
41
Philipp Deppenwiesec9b7d1f2018-11-10 00:35:02 +0100[diff] [blame]42ramstage-y += tspi/tspi.c
43romstage-y += tspi/tspi.c
Bill XIEc79e96b2019-08-22 20:28:36 +0800[diff] [blame]44bootblock-y += tspi/tspi.c
Philipp Deppenwiesec9b7d1f2018-11-10 00:35:02 +0100[diff] [blame]45verstage-$(CONFIG_VBOOT) += tspi/tspi.c
Bill XIEc79e96b2019-08-22 20:28:36 +0800[diff] [blame]46postcar-y += tspi/tspi.c
Philipp Deppenwiesec07f8fb2018-02-27 19:40:52 +0100[diff] [blame]47
48endif # CONFIG_TPM2
Bill XIEc79e96b2019-08-22 20:28:36 +0800[diff] [blame]49
50ifeq ($(CONFIG_TPM_MEASURED_BOOT),y)
51
52bootblock-y += tspi/crtm.c
53verstage-y += tspi/crtm.c
54romstage-y += tspi/crtm.c
55ramstage-y += tspi/crtm.c
56postcar-y += tspi/crtm.c
57
Sergii Dmytruk97fe17f2022-10-23 00:24:37 +0300[diff] [blame]58ramstage-$(CONFIG_TPM_LOG_CB) += tspi/log.c
59romstage-$(CONFIG_TPM_LOG_CB) += tspi/log.c
60verstage-$(CONFIG_TPM_LOG_CB) += tspi/log.c
61postcar-$(CONFIG_TPM_LOG_CB) += tspi/log.c
62bootblock-$(CONFIG_TPM_LOG_CB) += tspi/log.c
Bill XIEc79e96b2019-08-22 20:28:36 +0800[diff] [blame]63
Sergii Dmytruk4191dbf2022-10-23 00:34:32 +0300[diff] [blame]64ramstage-$(CONFIG_TPM_LOG_TPM1) += tspi/log-tpm1.c
65romstage-$(CONFIG_TPM_LOG_TPM1) += tspi/log-tpm1.c
66verstage-$(CONFIG_TPM_LOG_TPM1) += tspi/log-tpm1.c
67postcar-$(CONFIG_TPM_LOG_TPM1) += tspi/log-tpm1.c
68bootblock-$(CONFIG_TPM_LOG_TPM1) += tspi/log-tpm1.c
69
Sergii Dmytruk53db6772022-10-23 00:47:55 +0300[diff] [blame^]70ramstage-$(CONFIG_TPM_LOG_TPM2) += tspi/log-tpm2.c
71romstage-$(CONFIG_TPM_LOG_TPM2) += tspi/log-tpm2.c
72verstage-$(CONFIG_TPM_LOG_TPM2) += tspi/log-tpm2.c
73postcar-$(CONFIG_TPM_LOG_TPM2) += tspi/log-tpm2.c
74bootblock-$(CONFIG_TPM_LOG_TPM2) += tspi/log-tpm2.c
75
Bill XIEc79e96b2019-08-22 20:28:36 +0800[diff] [blame]76endif # CONFIG_TPM_MEASURED_BOOT