Angel Pons | f23ae0b | 2020-04-02 23:48:12 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 3 | |
| 4 | #include <console/console.h> |
| 5 | #include <device/device.h> |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 6 | #include <cpu/cpu.h> |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 7 | #include <cpu/x86/msr.h> |
Arthur Heymans | 6336d4c | 2018-01-25 21:38:25 +0100 | [diff] [blame] | 8 | #include <cpu/x86/mp.h> |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 9 | #include <cpu/x86/lapic.h> |
Stefan Reinauer | 2a27b20 | 2010-12-11 22:14:44 +0000 | [diff] [blame] | 10 | #include <cpu/intel/speedstep.h> |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 11 | #include <cpu/x86/cache.h> |
Uwe Hermann | aac8f66 | 2010-09-29 09:54:16 +0000 | [diff] [blame] | 12 | #include <cpu/x86/name.h> |
Kyösti Mälkki | f091f4d | 2019-08-14 03:49:21 +0300 | [diff] [blame] | 13 | #include <cpu/intel/smm_reloc.h> |
Matt DeVillier | ed6fe2f | 2016-12-14 16:12:43 -0600 | [diff] [blame] | 14 | #include <cpu/intel/common/common.h> |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 15 | #include "chip.h" |
| 16 | |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 17 | static void init_timer(void) |
| 18 | { |
Elyes HAOUAS | d6e9686 | 2016-08-21 10:12:15 +0200 | [diff] [blame] | 19 | /* Set the APIC timer to no interrupts and periodic mode */ |
Lee Leahy | 9d62e7e | 2017-03-15 17:40:50 -0700 | [diff] [blame] | 20 | lapic_write(LAPIC_LVTT, (1 << 17) | (1 << 16) | (0 << 12) | (0 << 0)); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 21 | |
| 22 | /* Set the divider to 1, no divider */ |
| 23 | lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1); |
| 24 | |
| 25 | /* Set the initial counter to 0xffffffff */ |
| 26 | lapic_write(LAPIC_TMICT, 0xffffffff); |
| 27 | } |
| 28 | |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 29 | #define MSR_BBL_CR_CTL3 0x11e |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 30 | |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 31 | static void configure_c_states(const int quad) |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 32 | { |
| 33 | msr_t msr; |
| 34 | |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 35 | /* Find pointer to CPU configuration. */ |
Edward O'Callaghan | 2c9d2cf | 2014-10-27 23:29:29 +1100 | [diff] [blame] | 36 | const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 37 | const struct cpu_intel_model_1067x_config *const conf = |
| 38 | (lapic && lapic->chip_info) ? lapic->chip_info : NULL; |
| 39 | |
| 40 | /* Is C5 requested and supported? */ |
| 41 | const int c5 = conf && conf->c5 && |
| 42 | (rdmsr(MSR_BBL_CR_CTL3).lo & (3 << 30)) && |
| 43 | !(rdmsr(MSR_FSB_FREQ).lo & (1 << 31)); |
| 44 | /* Is C6 requested and supported? */ |
| 45 | const int c6 = conf && conf->c6 && |
| 46 | ((cpuid_edx(5) >> (6 * 4)) & 0xf) && c5; |
| 47 | |
| 48 | const int cst_range = (c6 ? 6 : (c5 ? 5 : 4)) - 2; /* zero means lvl2 */ |
| 49 | |
Elyes HAOUAS | 4e6b790 | 2018-10-02 08:44:47 +0200 | [diff] [blame] | 50 | msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 51 | msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 52 | msr.lo |= (1 << 8); |
Lee Leahy | 26eeb0f | 2017-03-15 18:08:50 -0700 | [diff] [blame] | 53 | if (quad) |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 54 | msr.lo = (msr.lo & ~(7 << 0)) | (4 << 0); |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 55 | if (c5) { |
| 56 | msr.lo &= ~(1 << 13); |
| 57 | msr.lo &= ~(7 << 0); |
| 58 | msr.lo |= (1 << 3); /* Enable dynamic L2. */ |
| 59 | msr.lo |= (1 << 14); /* Enable deeper sleep */ |
| 60 | } |
| 61 | /* Next two fields seem to be mutually exclusive: */ |
| 62 | msr.lo &= ~(7 << 4); |
| 63 | msr.lo |= (1 << 10); /* Enable IO MWAIT redirection. */ |
| 64 | if (c6) |
| 65 | msr.lo |= (1 << 25); |
Elyes HAOUAS | 4e6b790 | 2018-10-02 08:44:47 +0200 | [diff] [blame] | 66 | wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 67 | |
| 68 | /* Set Processor MWAIT IO BASE */ |
| 69 | msr.hi = 0; |
Lee Leahy | cdc5048 | 2017-03-15 18:26:18 -0700 | [diff] [blame] | 70 | msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) |
| 71 | << 16); |
Patrick Georgi | 644e83b | 2013-02-09 15:35:30 +0100 | [diff] [blame] | 72 | wrmsr(MSR_PMG_IO_BASE_ADDR, msr); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 73 | |
| 74 | /* Set IO Capture Address */ |
| 75 | msr.hi = 0; |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 76 | msr.lo = ((PMB0_BASE + 4) & 0xffff) | ((cst_range & 0xffff) << 16); |
Patrick Georgi | 644e83b | 2013-02-09 15:35:30 +0100 | [diff] [blame] | 77 | wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 78 | |
| 79 | if (c5) { |
| 80 | msr = rdmsr(MSR_BBL_CR_CTL3); |
| 81 | msr.lo &= ~(7 << 25); |
| 82 | msr.lo |= (2 << 25); |
| 83 | msr.lo &= ~(3 << 30); |
| 84 | msr.lo |= (1 << 30); |
| 85 | wrmsr(MSR_BBL_CR_CTL3, msr); |
| 86 | } |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 87 | } |
| 88 | |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 89 | static void configure_p_states(const char stepping, const char cores) |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 90 | { |
| 91 | msr_t msr; |
| 92 | |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 93 | /* Find pointer to CPU configuration. */ |
Edward O'Callaghan | 2c9d2cf | 2014-10-27 23:29:29 +1100 | [diff] [blame] | 94 | const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 95 | struct cpu_intel_model_1067x_config *const conf = |
| 96 | (lapic && lapic->chip_info) ? lapic->chip_info : NULL; |
| 97 | |
| 98 | msr = rdmsr(MSR_EXTENDED_CONFIG); |
Patrick Georgi | f17c58b | 2014-08-09 20:48:12 +0200 | [diff] [blame] | 99 | /* Super LFM supported? */ |
| 100 | if (conf && conf->slfm && (msr.lo & (1 << 27))) |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 101 | msr.lo |= (1 << 28); /* Enable Super LFM. */ |
| 102 | wrmsr(MSR_EXTENDED_CONFIG, msr); |
| 103 | |
| 104 | if (rdmsr(MSR_FSB_CLOCK_VCC).hi & (1 << (63 - 32))) { |
| 105 | /* Turbo supported? */ |
| 106 | if ((stepping == 0xa) && (cores < 4)) { |
| 107 | msr = rdmsr(MSR_FSB_FREQ); |
| 108 | msr.lo |= (1 << 3); /* Enable hysteresis. */ |
| 109 | wrmsr(MSR_FSB_FREQ, msr); |
| 110 | } |
| 111 | msr = rdmsr(IA32_PERF_CTL); |
| 112 | msr.hi &= ~(1 << (32 - 32)); /* Clear turbo disable. */ |
| 113 | wrmsr(IA32_PERF_CTL, msr); |
| 114 | } |
| 115 | |
Elyes HAOUAS | 4e6b790 | 2018-10-02 08:44:47 +0200 | [diff] [blame] | 116 | msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 117 | msr.lo &= ~(1 << 11); /* Enable hw coordination. */ |
| 118 | msr.lo |= (1 << 15); /* Lock config until next reset. */ |
Elyes HAOUAS | 4e6b790 | 2018-10-02 08:44:47 +0200 | [diff] [blame] | 119 | wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 120 | } |
| 121 | |
| 122 | #define MSR_EMTTM_CR_TABLE(x) (0xa8 + (x)) |
| 123 | #define MSR_EMTTM_TABLE_NUM 6 |
| 124 | static void configure_emttm_tables(void) |
| 125 | { |
| 126 | int i; |
| 127 | int num_states, pstate_idx; |
| 128 | msr_t msr; |
| 129 | sst_table_t pstates; |
| 130 | |
| 131 | /* Gather p-state information. */ |
| 132 | speedstep_gen_pstates(&pstates); |
| 133 | |
| 134 | /* Never turbo mode or Super LFM. */ |
| 135 | num_states = pstates.num_states; |
| 136 | if (pstates.states[0].is_turbo) |
| 137 | --num_states; |
| 138 | if (pstates.states[pstates.num_states - 1].is_slfm) |
| 139 | --num_states; |
| 140 | /* Repeat lowest p-state if we haven't enough states. */ |
| 141 | const int num_lowest_pstate = |
| 142 | (num_states < MSR_EMTTM_TABLE_NUM) |
| 143 | ? (MSR_EMTTM_TABLE_NUM - num_states) + 1 |
| 144 | : 1; |
| 145 | /* Start from the lowest entry but skip Super LFM. */ |
| 146 | if (pstates.states[pstates.num_states - 1].is_slfm) |
| 147 | pstate_idx = pstates.num_states - 2; |
| 148 | else |
| 149 | pstate_idx = pstates.num_states - 1; |
| 150 | for (i = 0; i < MSR_EMTTM_TABLE_NUM; ++i) { |
| 151 | if (i >= num_lowest_pstate) |
| 152 | --pstate_idx; |
| 153 | const sst_state_t *const pstate = &pstates.states[pstate_idx]; |
| 154 | printk(BIOS_DEBUG, "writing P-State %d: %d, %d, " |
| 155 | "%2d, 0x%02x, %d; encoded: 0x%04x\n", |
| 156 | pstate_idx, pstate->dynfsb, pstate->nonint, |
| 157 | pstate->ratio, pstate->vid, pstate->power, |
| 158 | SPEEDSTEP_ENCODE_STATE(*pstate)); |
| 159 | msr.hi = 0; |
| 160 | msr.lo = SPEEDSTEP_ENCODE_STATE(pstates.states[pstate_idx]) & |
| 161 | /* Don't set half ratios. */ |
| 162 | ~SPEEDSTEP_RATIO_NONINT; |
| 163 | wrmsr(MSR_EMTTM_CR_TABLE(i), msr); |
| 164 | } |
| 165 | |
| 166 | msr = rdmsr(MSR_EMTTM_CR_TABLE(5)); |
| 167 | msr.lo |= (1 << 31); /* lock tables */ |
| 168 | wrmsr(MSR_EMTTM_CR_TABLE(5), msr); |
| 169 | } |
| 170 | |
| 171 | static void configure_misc(const int eist, const int tm2, const int emttm) |
| 172 | { |
| 173 | msr_t msr; |
| 174 | |
| 175 | const u32 sub_cstates = cpuid_edx(5); |
| 176 | |
Elyes HAOUAS | 419bfbc | 2018-10-01 08:47:51 +0200 | [diff] [blame] | 177 | msr = rdmsr(IA32_MISC_ENABLE); |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 178 | msr.lo |= (1 << 3); /* TM1 enable */ |
| 179 | if (tm2) |
| 180 | msr.lo |= (1 << 13); /* TM2 enable */ |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 181 | msr.lo |= (1 << 17); /* Bidirectional PROCHOT# */ |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 182 | msr.lo |= (1 << 18); /* MONITOR/MWAIT enable */ |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 183 | |
| 184 | msr.lo |= (1 << 10); /* FERR# multiplexing */ |
| 185 | |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 186 | if (eist) |
| 187 | msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 188 | |
| 189 | /* Enable C2E */ |
Lee Leahy | 26eeb0f | 2017-03-15 18:08:50 -0700 | [diff] [blame] | 190 | if (((sub_cstates >> (2 * 4)) & 0xf) >= 2) |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 191 | msr.lo |= (1 << 26); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 192 | |
| 193 | /* Enable C4E */ |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 194 | if (((sub_cstates >> (4 * 4)) & 0xf) >= 2) { |
| 195 | msr.hi |= (1 << (32 - 32)); // C4E |
| 196 | msr.hi |= (1 << (33 - 32)); // Hard C4E |
| 197 | } |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 198 | |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 199 | /* Enable EMTTM */ |
| 200 | if (emttm) |
| 201 | msr.hi |= (1 << (36 - 32)); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 202 | |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 203 | /* Enable turbo mode */ |
| 204 | if (rdmsr(MSR_FSB_CLOCK_VCC).hi & (1 << (63 - 32))) |
| 205 | msr.hi &= ~(1 << (38 - 32)); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 206 | |
Elyes HAOUAS | 419bfbc | 2018-10-01 08:47:51 +0200 | [diff] [blame] | 207 | wrmsr(IA32_MISC_ENABLE, msr); |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 208 | |
| 209 | if (eist) { |
| 210 | msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ |
Elyes HAOUAS | 419bfbc | 2018-10-01 08:47:51 +0200 | [diff] [blame] | 211 | wrmsr(IA32_MISC_ENABLE, msr); |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 212 | } |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 213 | } |
| 214 | |
| 215 | #define PIC_SENS_CFG 0x1aa |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 216 | static void configure_pic_thermal_sensors(const int tm2, const int quad) |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 217 | { |
| 218 | msr_t msr; |
| 219 | |
| 220 | msr = rdmsr(PIC_SENS_CFG); |
| 221 | |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 222 | if (quad) |
| 223 | msr.lo |= (1 << 31); |
| 224 | else |
| 225 | msr.lo &= ~(1 << 31); |
| 226 | if (tm2) |
| 227 | msr.lo |= (1 << 20); /* Enable TM1 if TM2 fails. */ |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 228 | msr.lo |= (1 << 21); // inter-core lock TM1 |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 229 | msr.lo |= (1 << 4); // Enable bypass filter /* What does it do? */ |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 230 | |
| 231 | wrmsr(PIC_SENS_CFG, msr); |
| 232 | } |
| 233 | |
Edward O'Callaghan | 2c9d2cf | 2014-10-27 23:29:29 +1100 | [diff] [blame] | 234 | static void model_1067x_init(struct device *cpu) |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 235 | { |
| 236 | char processor_name[49]; |
| 237 | |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 238 | |
| 239 | /* Gather some information: */ |
| 240 | |
| 241 | const struct cpuid_result cpuid1 = cpuid(1); |
| 242 | |
| 243 | /* Read stepping. */ |
| 244 | const char stepping = cpuid1.eax & 0xf; |
| 245 | /* Read number of cores. */ |
| 246 | const char cores = (cpuid1.ebx >> 16) & 0xf; |
| 247 | /* Is this a quad core? */ |
| 248 | const char quad = cores > 2; |
| 249 | /* Is this even a multiprocessor? */ |
| 250 | const char mp = cores > 1; |
| 251 | |
| 252 | /* Enable EMTTM on uni- and on multi-processors if it's not disabled. */ |
| 253 | const char emttm = !mp || !(rdmsr(MSR_EXTENDED_CONFIG).lo & 4); |
| 254 | |
| 255 | /* Is enhanced speedstep supported? */ |
| 256 | const char eist = (cpuid1.ecx & (1 << 7)) && |
| 257 | !(rdmsr(IA32_PLATFORM_ID).lo & (1 << 17)); |
| 258 | /* Test for TM2 only if EIST is available. */ |
| 259 | const char tm2 = eist && (cpuid1.ecx & (1 << 8)); |
| 260 | |
| 261 | |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 262 | /* Turn on caching if we haven't already */ |
| 263 | x86_enable_cache(); |
| 264 | |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 265 | /* Print processor name */ |
| 266 | fill_processor_name(processor_name); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 267 | printk(BIOS_INFO, "CPU: %s.\n", processor_name); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 268 | |
Elyes HAOUAS | d6e9686 | 2016-08-21 10:12:15 +0200 | [diff] [blame] | 269 | /* Enable the local CPU APICs */ |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 270 | setup_lapic(); |
| 271 | |
| 272 | /* Initialize the APIC timer */ |
| 273 | init_timer(); |
| 274 | |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 275 | /* Configure C States */ |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 276 | configure_c_states(quad); |
| 277 | |
| 278 | /* Configure P States */ |
| 279 | configure_p_states(stepping, cores); |
| 280 | |
| 281 | /* EMTTM */ |
| 282 | if (emttm) |
| 283 | configure_emttm_tables(); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 284 | |
| 285 | /* Configure Enhanced SpeedStep and Thermal Sensors */ |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 286 | configure_misc(eist, tm2, emttm); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 287 | |
| 288 | /* PIC thermal sensor control */ |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 289 | configure_pic_thermal_sensors(tm2, quad); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 290 | } |
| 291 | |
| 292 | static struct device_operations cpu_dev_ops = { |
| 293 | .init = model_1067x_init, |
| 294 | }; |
| 295 | |
Jonathan Neuschäfer | 8f06ce3 | 2017-11-20 01:56:44 +0100 | [diff] [blame] | 296 | static const struct cpu_device_id cpu_table[] = { |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 297 | { X86_VENDOR_INTEL, 0x10676 }, /* Intel Core 2 Solo/Core Duo */ |
Stefan Reinauer | c104cb0 | 2010-10-18 00:21:39 +0000 | [diff] [blame] | 298 | { X86_VENDOR_INTEL, 0x10677 }, |
| 299 | { X86_VENDOR_INTEL, 0x1067A }, |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 300 | { 0, 0 }, |
| 301 | }; |
| 302 | |
| 303 | static const struct cpu_driver driver __cpu_driver = { |
| 304 | .ops = &cpu_dev_ops, |
| 305 | .id_table = cpu_table, |
| 306 | }; |
| 307 | |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 308 | struct chip_operations cpu_intel_model_1067x_ops = { |
| 309 | CHIP_NAME("Intel Penryn CPU") |
| 310 | }; |