src: Move common IA-32 MSRs to <cpu/x86/msr.h>
Use "cpu/x86/msr.h" for common IA-32 MSRs and correct IA-32 MSRs names.
Change-Id: Ida7f2d608c55796abf9452f190a58802e498302d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28752
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index f304b94..7eb121e 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -190,7 +190,7 @@
const u32 sub_cstates = cpuid_edx(5);
- msr = rdmsr(IA32_MISC_ENABLES);
+ msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= (1 << 3); /* TM1 enable */
if (tm2)
msr.lo |= (1 << 13); /* TM2 enable */
@@ -220,11 +220,11 @@
if (rdmsr(MSR_FSB_CLOCK_VCC).hi & (1 << (63 - 32)))
msr.hi &= ~(1 << (38 - 32));
- wrmsr(IA32_MISC_ENABLES, msr);
+ wrmsr(IA32_MISC_ENABLE, msr);
if (eist) {
msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */
- wrmsr(IA32_MISC_ENABLES, msr);
+ wrmsr(IA32_MISC_ENABLE, msr);
}
}