Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <arch/io.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame^] | 18 | #include <device/pci_ops.h> |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 19 | #include <console/console.h> |
| 20 | #include <device/device.h> |
| 21 | #include <device/pci.h> |
| 22 | #include <device/pci_ids.h> |
| 23 | #include "pch.h" |
Vladimir Serbinenko | 6d6298d | 2014-01-11 07:46:50 +0100 | [diff] [blame] | 24 | #include <pc80/mc146818rtc.h> |
Alexander Couzens | 7bf47ee | 2015-04-16 02:00:21 +0200 | [diff] [blame] | 25 | #include <acpi/sata.h> |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 26 | |
| 27 | typedef struct southbridge_intel_bd82x6x_config config_t; |
| 28 | |
Stefan Reinauer | 16b022a | 2012-07-17 16:42:51 -0700 | [diff] [blame] | 29 | static inline u32 sir_read(struct device *dev, int idx) |
| 30 | { |
| 31 | pci_write_config32(dev, SATA_SIRI, idx); |
| 32 | return pci_read_config32(dev, SATA_SIRD); |
| 33 | } |
| 34 | |
| 35 | static inline void sir_write(struct device *dev, int idx, u32 value) |
| 36 | { |
| 37 | pci_write_config32(dev, SATA_SIRI, idx); |
| 38 | pci_write_config32(dev, SATA_SIRD, value); |
| 39 | } |
| 40 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 41 | static void sata_init(struct device *dev) |
| 42 | { |
| 43 | u32 reg32; |
| 44 | u16 reg16; |
| 45 | /* Get the chip configuration */ |
| 46 | config_t *config = dev->chip_info; |
Vladimir Serbinenko | 6d6298d | 2014-01-11 07:46:50 +0100 | [diff] [blame] | 47 | u8 sata_mode; |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 48 | |
Stefan Reinauer | 16b022a | 2012-07-17 16:42:51 -0700 | [diff] [blame] | 49 | printk(BIOS_DEBUG, "SATA: Initializing...\n"); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 50 | |
| 51 | if (config == NULL) { |
Stefan Reinauer | 16b022a | 2012-07-17 16:42:51 -0700 | [diff] [blame] | 52 | printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n"); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 53 | return; |
| 54 | } |
| 55 | |
Vladimir Serbinenko | 6d6298d | 2014-01-11 07:46:50 +0100 | [diff] [blame] | 56 | if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS) |
| 57 | /* Default to AHCI */ |
| 58 | sata_mode = 0; |
| 59 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 60 | /* SATA configuration */ |
| 61 | |
| 62 | /* Enable BARs */ |
| 63 | pci_write_config16(dev, PCI_COMMAND, 0x0007); |
| 64 | |
Vladimir Serbinenko | 6d6298d | 2014-01-11 07:46:50 +0100 | [diff] [blame] | 65 | /* AHCI */ |
| 66 | if (sata_mode == 0) { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 67 | u8 *abar; |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 68 | |
Stefan Reinauer | 16b022a | 2012-07-17 16:42:51 -0700 | [diff] [blame] | 69 | printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 70 | |
| 71 | /* Set Interrupt Line */ |
| 72 | /* Interrupt Pin is set by D31IP.PIP */ |
| 73 | pci_write_config8(dev, INTR_LN, 0x0a); |
| 74 | |
| 75 | /* Set timings */ |
| 76 | pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | |
| 77 | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | |
| 78 | IDE_PPE0 | IDE_IE0 | IDE_TIME0); |
| 79 | pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | |
| 80 | IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); |
| 81 | |
| 82 | /* Sync DMA */ |
| 83 | pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); |
| 84 | pci_write_config16(dev, IDE_SDMA_TIM, 0x0001); |
| 85 | |
| 86 | /* Set IDE I/O Configuration */ |
| 87 | reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; |
| 88 | pci_write_config32(dev, IDE_CONFIG, reg32); |
| 89 | |
| 90 | /* for AHCI, Port Enable is managed in memory mapped space */ |
| 91 | reg16 = pci_read_config16(dev, 0x92); |
| 92 | reg16 &= ~0x3f; /* 6 ports SKU + ORM */ |
| 93 | reg16 |= 0x8000 | config->sata_port_map; |
| 94 | pci_write_config16(dev, 0x92, reg16); |
| 95 | |
| 96 | /* SATA Initialization register */ |
| 97 | pci_write_config32(dev, 0x94, |
| 98 | ((config->sata_port_map ^ 0x3f) << 24) | 0x183); |
| 99 | |
| 100 | /* Initialize AHCI memory-mapped space */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 101 | abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); |
| 102 | printk(BIOS_DEBUG, "ABAR: %p\n", abar); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 103 | /* CAP (HBA Capabilities) : enable power management */ |
| 104 | reg32 = read32(abar + 0x00); |
| 105 | reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS |
| 106 | reg32 &= ~0x00020060; // clear SXS+EMS+PMS |
Shawn Nematbakhsh | c9fc029 | 2013-03-14 10:44:13 -0700 | [diff] [blame] | 107 | /* Set ISS, if available */ |
| 108 | if (config->sata_interface_speed_support) |
| 109 | { |
| 110 | reg32 &= ~0x00f00000; |
| 111 | reg32 |= (config->sata_interface_speed_support & 0x03) |
| 112 | << 20; |
| 113 | } |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 114 | write32(abar + 0x00, reg32); |
| 115 | /* PI (Ports implemented) */ |
| 116 | write32(abar + 0x0c, config->sata_port_map); |
| 117 | (void) read32(abar + 0x0c); /* Read back 1 */ |
| 118 | (void) read32(abar + 0x0c); /* Read back 2 */ |
| 119 | /* CAP2 (HBA Capabilities Extended)*/ |
| 120 | reg32 = read32(abar + 0x24); |
| 121 | reg32 &= ~0x00000002; |
| 122 | write32(abar + 0x24, reg32); |
| 123 | /* VSP (Vendor Specific Register */ |
| 124 | reg32 = read32(abar + 0xa0); |
| 125 | reg32 &= ~0x00000005; |
| 126 | write32(abar + 0xa0, reg32); |
| 127 | } else { |
Vladimir Serbinenko | 6d6298d | 2014-01-11 07:46:50 +0100 | [diff] [blame] | 128 | /* IDE */ |
Stefan Reinauer | 16b022a | 2012-07-17 16:42:51 -0700 | [diff] [blame] | 129 | printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 130 | |
| 131 | /* No AHCI: clear AHCI base */ |
| 132 | pci_write_config32(dev, 0x24, 0x00000000); |
| 133 | |
| 134 | /* And without AHCI BAR no memory decoding */ |
| 135 | reg16 = pci_read_config16(dev, PCI_COMMAND); |
| 136 | reg16 &= ~PCI_COMMAND_MEMORY; |
| 137 | pci_write_config16(dev, PCI_COMMAND, reg16); |
| 138 | |
| 139 | /* Native mode capable on both primary and secondary (0xa) |
| 140 | * or'ed with enabled (0x50) = 0xf |
| 141 | */ |
| 142 | pci_write_config8(dev, 0x09, 0x8f); |
| 143 | |
| 144 | /* Set Interrupt Line */ |
| 145 | /* Interrupt Pin is set by D31IP.PIP */ |
| 146 | pci_write_config8(dev, INTR_LN, 0xff); |
| 147 | |
| 148 | /* Set timings */ |
| 149 | pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | |
| 150 | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | |
| 151 | IDE_PPE0 | IDE_IE0 | IDE_TIME0); |
| 152 | pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | |
| 153 | IDE_SITRE | IDE_ISP_3_CLOCKS | |
| 154 | IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0); |
| 155 | |
| 156 | /* Sync DMA */ |
| 157 | pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0); |
| 158 | pci_write_config16(dev, IDE_SDMA_TIM, 0x0201); |
| 159 | |
| 160 | /* Set IDE I/O Configuration */ |
| 161 | reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; |
| 162 | pci_write_config32(dev, IDE_CONFIG, reg32); |
| 163 | |
| 164 | /* Port enable */ |
| 165 | reg16 = pci_read_config16(dev, 0x92); |
| 166 | reg16 &= ~0x3f; |
| 167 | reg16 |= config->sata_port_map; |
| 168 | pci_write_config16(dev, 0x92, reg16); |
| 169 | |
| 170 | /* SATA Initialization register */ |
| 171 | pci_write_config32(dev, 0x94, |
| 172 | ((config->sata_port_map ^ 0x3f) << 24) | 0x183); |
| 173 | } |
Duncan Laurie | cfb64bd | 2012-07-16 16:16:31 -0700 | [diff] [blame] | 174 | |
| 175 | /* Set Gen3 Transmitter settings if needed */ |
| 176 | if (config->sata_port0_gen3_tx) |
| 177 | pch_iobp_update(SATA_IOBP_SP0G3IR, 0, |
| 178 | config->sata_port0_gen3_tx); |
| 179 | |
| 180 | if (config->sata_port1_gen3_tx) |
| 181 | pch_iobp_update(SATA_IOBP_SP1G3IR, 0, |
| 182 | config->sata_port1_gen3_tx); |
Stefan Reinauer | 16b022a | 2012-07-17 16:42:51 -0700 | [diff] [blame] | 183 | |
| 184 | /* Additional Programming Requirements */ |
| 185 | sir_write(dev, 0x04, 0x00001600); |
| 186 | sir_write(dev, 0x28, 0xa0000033); |
| 187 | reg32 = sir_read(dev, 0x54); |
| 188 | reg32 &= 0xff000000; |
| 189 | reg32 |= 0x5555aa; |
| 190 | sir_write(dev, 0x54, reg32); |
| 191 | sir_write(dev, 0x64, 0xcccc8484); |
| 192 | reg32 = sir_read(dev, 0x68); |
| 193 | reg32 &= 0xffff0000; |
| 194 | reg32 |= 0xcccc; |
| 195 | sir_write(dev, 0x68, reg32); |
| 196 | reg32 = sir_read(dev, 0x78); |
| 197 | reg32 &= 0x0000ffff; |
| 198 | reg32 |= 0x88880000; |
| 199 | sir_write(dev, 0x78, reg32); |
| 200 | sir_write(dev, 0x84, 0x001c7000); |
| 201 | sir_write(dev, 0x88, 0x88338822); |
| 202 | sir_write(dev, 0xa0, 0x001c7000); |
| 203 | // a4 |
| 204 | sir_write(dev, 0xc4, 0x0c0c0c0c); |
| 205 | sir_write(dev, 0xc8, 0x0c0c0c0c); |
| 206 | sir_write(dev, 0xd4, 0x10000000); |
| 207 | |
| 208 | pch_iobp_update(0xea004001, 0x3fffffff, 0xc0000000); |
| 209 | pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 210 | } |
| 211 | |
Elyes HAOUAS | 4aec340 | 2018-05-25 08:29:27 +0200 | [diff] [blame] | 212 | static void sata_enable(struct device *dev) |
Stefan Reinauer | 816d081 | 2012-04-30 16:42:07 -0700 | [diff] [blame] | 213 | { |
| 214 | /* Get the chip configuration */ |
| 215 | config_t *config = dev->chip_info; |
| 216 | u16 map = 0; |
Vladimir Serbinenko | 6d6298d | 2014-01-11 07:46:50 +0100 | [diff] [blame] | 217 | u8 sata_mode; |
Stefan Reinauer | 816d081 | 2012-04-30 16:42:07 -0700 | [diff] [blame] | 218 | |
| 219 | if (!config) |
| 220 | return; |
| 221 | |
Vladimir Serbinenko | 6d6298d | 2014-01-11 07:46:50 +0100 | [diff] [blame] | 222 | if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS) |
| 223 | sata_mode = 0; |
| 224 | |
Stefan Reinauer | 816d081 | 2012-04-30 16:42:07 -0700 | [diff] [blame] | 225 | /* |
| 226 | * Set SATA controller mode early so the resource allocator can |
| 227 | * properly assign IO/Memory resources for the controller. |
| 228 | */ |
Vladimir Serbinenko | 6d6298d | 2014-01-11 07:46:50 +0100 | [diff] [blame] | 229 | if (sata_mode == 0) |
Stefan Reinauer | 816d081 | 2012-04-30 16:42:07 -0700 | [diff] [blame] | 230 | map = 0x0060; |
| 231 | |
| 232 | map |= (config->sata_port_map ^ 0x3f) << 8; |
| 233 | |
| 234 | pci_write_config16(dev, 0x90, map); |
| 235 | } |
| 236 | |
Elyes HAOUAS | 4aec340 | 2018-05-25 08:29:27 +0200 | [diff] [blame] | 237 | static void sata_set_subsystem(struct device *dev, unsigned vendor, |
| 238 | unsigned device) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 239 | { |
| 240 | if (!vendor || !device) { |
| 241 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 242 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 243 | } else { |
| 244 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 245 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 246 | } |
| 247 | } |
| 248 | |
Aaron Durbin | aa090cb | 2017-09-13 16:01:52 -0600 | [diff] [blame] | 249 | static const char *sata_acpi_name(const struct device *dev) |
Patrick Rudolph | 604f698 | 2017-06-07 09:46:52 +0200 | [diff] [blame] | 250 | { |
| 251 | return "SATA"; |
| 252 | } |
| 253 | |
Elyes HAOUAS | 4aec340 | 2018-05-25 08:29:27 +0200 | [diff] [blame] | 254 | static void sata_fill_ssdt(struct device *dev) |
Alexander Couzens | 7bf47ee | 2015-04-16 02:00:21 +0200 | [diff] [blame] | 255 | { |
| 256 | config_t *config = dev->chip_info; |
| 257 | generate_sata_ssdt_ports("\\_SB_.PCI0.SATA", config->sata_port_map); |
| 258 | } |
| 259 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 260 | static struct pci_operations sata_pci_ops = { |
| 261 | .set_subsystem = sata_set_subsystem, |
| 262 | }; |
| 263 | |
| 264 | static struct device_operations sata_ops = { |
| 265 | .read_resources = pci_dev_read_resources, |
| 266 | .set_resources = pci_dev_set_resources, |
| 267 | .enable_resources = pci_dev_enable_resources, |
Alexander Couzens | 7bf47ee | 2015-04-16 02:00:21 +0200 | [diff] [blame] | 268 | .acpi_fill_ssdt_generator |
| 269 | = sata_fill_ssdt, |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 270 | .init = sata_init, |
Stefan Reinauer | 816d081 | 2012-04-30 16:42:07 -0700 | [diff] [blame] | 271 | .enable = sata_enable, |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 272 | .scan_bus = 0, |
| 273 | .ops_pci = &sata_pci_ops, |
Patrick Rudolph | 604f698 | 2017-06-07 09:46:52 +0200 | [diff] [blame] | 274 | .acpi_name = sata_acpi_name, |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 275 | }; |
| 276 | |
Stefan Reinauer | 9a380ab | 2012-06-22 13:16:11 -0700 | [diff] [blame] | 277 | static const unsigned short pci_device_ids[] = { 0x1c00, 0x1c01, 0x1c02, 0x1c03, |
| 278 | 0x1e00, 0x1e01, 0x1e02, 0x1e03, |
| 279 | 0 }; |
| 280 | |
| 281 | static const struct pci_driver pch_sata __pci_driver = { |
| 282 | .ops = &sata_ops, |
| 283 | .vendor = PCI_VENDOR_ID_INTEL, |
| 284 | .devices = pci_device_ids, |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 285 | }; |