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Stefan Reinauer8e073822012-04-04 00:07:22 +02001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2008-2009 coresystems GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
9 * the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
Patrick Georgib890a122015-03-26 15:17:45 +010018 * Foundation, Inc.
Stefan Reinauer8e073822012-04-04 00:07:22 +020019 */
20
21#include <arch/io.h>
22#include <console/console.h>
23#include <device/device.h>
24#include <device/pci.h>
25#include <device/pci_ids.h>
26#include "pch.h"
Vladimir Serbinenko6d6298d2014-01-11 07:46:50 +010027#include <pc80/mc146818rtc.h>
Alexander Couzens7bf47ee2015-04-16 02:00:21 +020028#include <acpi/sata.h>
Stefan Reinauer8e073822012-04-04 00:07:22 +020029
30typedef struct southbridge_intel_bd82x6x_config config_t;
31
Stefan Reinauer16b022a2012-07-17 16:42:51 -070032static inline u32 sir_read(struct device *dev, int idx)
33{
34 pci_write_config32(dev, SATA_SIRI, idx);
35 return pci_read_config32(dev, SATA_SIRD);
36}
37
38static inline void sir_write(struct device *dev, int idx, u32 value)
39{
40 pci_write_config32(dev, SATA_SIRI, idx);
41 pci_write_config32(dev, SATA_SIRD, value);
42}
43
Stefan Reinauer8e073822012-04-04 00:07:22 +020044static void sata_init(struct device *dev)
45{
46 u32 reg32;
47 u16 reg16;
48 /* Get the chip configuration */
49 config_t *config = dev->chip_info;
Vladimir Serbinenko6d6298d2014-01-11 07:46:50 +010050 u8 sata_mode;
Stefan Reinauer8e073822012-04-04 00:07:22 +020051
Stefan Reinauer16b022a2012-07-17 16:42:51 -070052 printk(BIOS_DEBUG, "SATA: Initializing...\n");
Stefan Reinauer8e073822012-04-04 00:07:22 +020053
54 if (config == NULL) {
Stefan Reinauer16b022a2012-07-17 16:42:51 -070055 printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n");
Stefan Reinauer8e073822012-04-04 00:07:22 +020056 return;
57 }
58
Vladimir Serbinenko6d6298d2014-01-11 07:46:50 +010059 if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS)
60 /* Default to AHCI */
61 sata_mode = 0;
62
Stefan Reinauer8e073822012-04-04 00:07:22 +020063 /* SATA configuration */
64
65 /* Enable BARs */
66 pci_write_config16(dev, PCI_COMMAND, 0x0007);
67
Vladimir Serbinenko6d6298d2014-01-11 07:46:50 +010068 /* AHCI */
69 if (sata_mode == 0) {
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080070 u8 *abar;
Stefan Reinauer8e073822012-04-04 00:07:22 +020071
Stefan Reinauer16b022a2012-07-17 16:42:51 -070072 printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
Stefan Reinauer8e073822012-04-04 00:07:22 +020073
74 /* Set Interrupt Line */
75 /* Interrupt Pin is set by D31IP.PIP */
76 pci_write_config8(dev, INTR_LN, 0x0a);
77
78 /* Set timings */
79 pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
80 IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
81 IDE_PPE0 | IDE_IE0 | IDE_TIME0);
82 pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
83 IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
84
85 /* Sync DMA */
86 pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
87 pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
88
89 /* Set IDE I/O Configuration */
90 reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
91 pci_write_config32(dev, IDE_CONFIG, reg32);
92
93 /* for AHCI, Port Enable is managed in memory mapped space */
94 reg16 = pci_read_config16(dev, 0x92);
95 reg16 &= ~0x3f; /* 6 ports SKU + ORM */
96 reg16 |= 0x8000 | config->sata_port_map;
97 pci_write_config16(dev, 0x92, reg16);
98
99 /* SATA Initialization register */
100 pci_write_config32(dev, 0x94,
101 ((config->sata_port_map ^ 0x3f) << 24) | 0x183);
102
103 /* Initialize AHCI memory-mapped space */
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800104 abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
105 printk(BIOS_DEBUG, "ABAR: %p\n", abar);
Stefan Reinauer8e073822012-04-04 00:07:22 +0200106 /* CAP (HBA Capabilities) : enable power management */
107 reg32 = read32(abar + 0x00);
108 reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS
109 reg32 &= ~0x00020060; // clear SXS+EMS+PMS
Shawn Nematbakhshc9fc0292013-03-14 10:44:13 -0700110 /* Set ISS, if available */
111 if (config->sata_interface_speed_support)
112 {
113 reg32 &= ~0x00f00000;
114 reg32 |= (config->sata_interface_speed_support & 0x03)
115 << 20;
116 }
Stefan Reinauer8e073822012-04-04 00:07:22 +0200117 write32(abar + 0x00, reg32);
118 /* PI (Ports implemented) */
119 write32(abar + 0x0c, config->sata_port_map);
120 (void) read32(abar + 0x0c); /* Read back 1 */
121 (void) read32(abar + 0x0c); /* Read back 2 */
122 /* CAP2 (HBA Capabilities Extended)*/
123 reg32 = read32(abar + 0x24);
124 reg32 &= ~0x00000002;
125 write32(abar + 0x24, reg32);
126 /* VSP (Vendor Specific Register */
127 reg32 = read32(abar + 0xa0);
128 reg32 &= ~0x00000005;
129 write32(abar + 0xa0, reg32);
130 } else {
Vladimir Serbinenko6d6298d2014-01-11 07:46:50 +0100131 /* IDE */
Stefan Reinauer16b022a2012-07-17 16:42:51 -0700132 printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
Stefan Reinauer8e073822012-04-04 00:07:22 +0200133
134 /* No AHCI: clear AHCI base */
135 pci_write_config32(dev, 0x24, 0x00000000);
136
137 /* And without AHCI BAR no memory decoding */
138 reg16 = pci_read_config16(dev, PCI_COMMAND);
139 reg16 &= ~PCI_COMMAND_MEMORY;
140 pci_write_config16(dev, PCI_COMMAND, reg16);
141
142 /* Native mode capable on both primary and secondary (0xa)
143 * or'ed with enabled (0x50) = 0xf
144 */
145 pci_write_config8(dev, 0x09, 0x8f);
146
147 /* Set Interrupt Line */
148 /* Interrupt Pin is set by D31IP.PIP */
149 pci_write_config8(dev, INTR_LN, 0xff);
150
151 /* Set timings */
152 pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
153 IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
154 IDE_PPE0 | IDE_IE0 | IDE_TIME0);
155 pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
156 IDE_SITRE | IDE_ISP_3_CLOCKS |
157 IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0);
158
159 /* Sync DMA */
160 pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0);
161 pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
162
163 /* Set IDE I/O Configuration */
164 reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
165 pci_write_config32(dev, IDE_CONFIG, reg32);
166
167 /* Port enable */
168 reg16 = pci_read_config16(dev, 0x92);
169 reg16 &= ~0x3f;
170 reg16 |= config->sata_port_map;
171 pci_write_config16(dev, 0x92, reg16);
172
173 /* SATA Initialization register */
174 pci_write_config32(dev, 0x94,
175 ((config->sata_port_map ^ 0x3f) << 24) | 0x183);
176 }
Duncan Lauriecfb64bd2012-07-16 16:16:31 -0700177
178 /* Set Gen3 Transmitter settings if needed */
179 if (config->sata_port0_gen3_tx)
180 pch_iobp_update(SATA_IOBP_SP0G3IR, 0,
181 config->sata_port0_gen3_tx);
182
183 if (config->sata_port1_gen3_tx)
184 pch_iobp_update(SATA_IOBP_SP1G3IR, 0,
185 config->sata_port1_gen3_tx);
Stefan Reinauer16b022a2012-07-17 16:42:51 -0700186
187 /* Additional Programming Requirements */
188 sir_write(dev, 0x04, 0x00001600);
189 sir_write(dev, 0x28, 0xa0000033);
190 reg32 = sir_read(dev, 0x54);
191 reg32 &= 0xff000000;
192 reg32 |= 0x5555aa;
193 sir_write(dev, 0x54, reg32);
194 sir_write(dev, 0x64, 0xcccc8484);
195 reg32 = sir_read(dev, 0x68);
196 reg32 &= 0xffff0000;
197 reg32 |= 0xcccc;
198 sir_write(dev, 0x68, reg32);
199 reg32 = sir_read(dev, 0x78);
200 reg32 &= 0x0000ffff;
201 reg32 |= 0x88880000;
202 sir_write(dev, 0x78, reg32);
203 sir_write(dev, 0x84, 0x001c7000);
204 sir_write(dev, 0x88, 0x88338822);
205 sir_write(dev, 0xa0, 0x001c7000);
206 // a4
207 sir_write(dev, 0xc4, 0x0c0c0c0c);
208 sir_write(dev, 0xc8, 0x0c0c0c0c);
209 sir_write(dev, 0xd4, 0x10000000);
210
211 pch_iobp_update(0xea004001, 0x3fffffff, 0xc0000000);
212 pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100);
Stefan Reinauer8e073822012-04-04 00:07:22 +0200213}
214
Stefan Reinauer816d0812012-04-30 16:42:07 -0700215static void sata_enable(device_t dev)
216{
217 /* Get the chip configuration */
218 config_t *config = dev->chip_info;
219 u16 map = 0;
Vladimir Serbinenko6d6298d2014-01-11 07:46:50 +0100220 u8 sata_mode;
Stefan Reinauer816d0812012-04-30 16:42:07 -0700221
222 if (!config)
223 return;
224
Vladimir Serbinenko6d6298d2014-01-11 07:46:50 +0100225 if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS)
226 sata_mode = 0;
227
Stefan Reinauer816d0812012-04-30 16:42:07 -0700228 /*
229 * Set SATA controller mode early so the resource allocator can
230 * properly assign IO/Memory resources for the controller.
231 */
Vladimir Serbinenko6d6298d2014-01-11 07:46:50 +0100232 if (sata_mode == 0)
Stefan Reinauer816d0812012-04-30 16:42:07 -0700233 map = 0x0060;
234
235 map |= (config->sata_port_map ^ 0x3f) << 8;
236
237 pci_write_config16(dev, 0x90, map);
238}
239
Stefan Reinauer8e073822012-04-04 00:07:22 +0200240static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
241{
242 if (!vendor || !device) {
243 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
244 pci_read_config32(dev, PCI_VENDOR_ID));
245 } else {
246 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
247 ((device & 0xffff) << 16) | (vendor & 0xffff));
248 }
249}
250
Alexander Couzens7bf47ee2015-04-16 02:00:21 +0200251static void sata_fill_ssdt(device_t dev)
252{
253 config_t *config = dev->chip_info;
254 generate_sata_ssdt_ports("\\_SB_.PCI0.SATA", config->sata_port_map);
255}
256
Stefan Reinauer8e073822012-04-04 00:07:22 +0200257static struct pci_operations sata_pci_ops = {
258 .set_subsystem = sata_set_subsystem,
259};
260
261static struct device_operations sata_ops = {
262 .read_resources = pci_dev_read_resources,
263 .set_resources = pci_dev_set_resources,
264 .enable_resources = pci_dev_enable_resources,
Alexander Couzens7bf47ee2015-04-16 02:00:21 +0200265 .acpi_fill_ssdt_generator
266 = sata_fill_ssdt,
Stefan Reinauer8e073822012-04-04 00:07:22 +0200267 .init = sata_init,
Stefan Reinauer816d0812012-04-30 16:42:07 -0700268 .enable = sata_enable,
Stefan Reinauer8e073822012-04-04 00:07:22 +0200269 .scan_bus = 0,
270 .ops_pci = &sata_pci_ops,
271};
272
Stefan Reinauer9a380ab2012-06-22 13:16:11 -0700273static const unsigned short pci_device_ids[] = { 0x1c00, 0x1c01, 0x1c02, 0x1c03,
274 0x1e00, 0x1e01, 0x1e02, 0x1e03,
275 0 };
276
277static const struct pci_driver pch_sata __pci_driver = {
278 .ops = &sata_ops,
279 .vendor = PCI_VENDOR_ID_INTEL,
280 .devices = pci_device_ids,
Stefan Reinauer8e073822012-04-04 00:07:22 +0200281};