Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <stddef.h> |
Aaron Durbin | f5cfaa3 | 2016-07-13 23:20:07 -0500 | [diff] [blame] | 17 | #include <arch/acpi.h> |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 18 | #include <assert.h> |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 19 | #include <cbfs.h> |
| 20 | #include <cbmem.h> |
Patrick Rudolph | 45022ae | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 21 | #include <cf9_reset.h> |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 22 | #include <console/console.h> |
| 23 | #include <device/pci_def.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame^] | 24 | #include <device/pci_ops.h> |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 25 | #include <halt.h> |
Aaron Durbin | decd062 | 2017-12-15 12:26:40 -0700 | [diff] [blame] | 26 | #include <mrc_cache.h> |
Julius Werner | 18ea2d3 | 2014-10-07 16:42:17 -0700 | [diff] [blame] | 27 | #include <soc/gpio.h> |
Julius Werner | 18ea2d3 | 2014-10-07 16:42:17 -0700 | [diff] [blame] | 28 | #include <soc/iomap.h> |
| 29 | #include <soc/iosf.h> |
| 30 | #include <soc/pci_devs.h> |
Julius Werner | 18ea2d3 | 2014-10-07 16:42:17 -0700 | [diff] [blame] | 31 | #include <soc/romstage.h> |
Aaron Durbin | 107b71c | 2014-01-09 14:35:41 -0600 | [diff] [blame] | 32 | #include <ec/google/chromeec/ec.h> |
| 33 | #include <ec/google/chromeec/ec_commands.h> |
Philipp Deppenwiese | fea2429 | 2017-10-17 17:02:29 +0200 | [diff] [blame] | 34 | #include <security/vboot/vboot_common.h> |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 35 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 36 | static void enable_smbus(void) |
| 37 | { |
| 38 | uint32_t reg; |
| 39 | const uint32_t smbus_dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC); |
| 40 | |
| 41 | /* SMBus I/O BAR */ |
| 42 | reg = SMBUS_BASE_ADDRESS | 2; |
| 43 | pci_write_config32(smbus_dev, PCI_BASE_ADDRESS_4, reg); |
| 44 | /* Enable decode of I/O space. */ |
| 45 | reg = pci_read_config16(smbus_dev, PCI_COMMAND); |
| 46 | reg |= 0x1; |
| 47 | pci_write_config16(smbus_dev, PCI_COMMAND, reg); |
| 48 | /* Enable Host Controller */ |
| 49 | reg = pci_read_config8(smbus_dev, 0x40); |
| 50 | reg |= 1; |
| 51 | pci_write_config8(smbus_dev, 0x40, reg); |
| 52 | |
| 53 | /* Configure pads to be used for SMBus */ |
| 54 | score_select_func(PCU_SMB_CLK_PAD, 1); |
| 55 | score_select_func(PCU_SMB_DATA_PAD, 1); |
| 56 | } |
| 57 | |
Aaron Durbin | 833ff35 | 2013-10-02 11:06:31 -0500 | [diff] [blame] | 58 | static void ABI_X86 send_to_console(unsigned char b) |
| 59 | { |
Kyösti Mälkki | 657e0be | 2014-02-04 19:03:57 +0200 | [diff] [blame] | 60 | do_putchar(b); |
Aaron Durbin | 833ff35 | 2013-10-02 11:06:31 -0500 | [diff] [blame] | 61 | } |
| 62 | |
Aaron Durbin | 3ccb3ce | 2013-10-11 00:26:04 -0500 | [diff] [blame] | 63 | static void print_dram_info(void) |
| 64 | { |
| 65 | const int mrc_ver_reg = 0xf0; |
| 66 | const uint32_t soc_dev = PCI_DEV(0, SOC_DEV, SOC_FUNC); |
| 67 | uint32_t reg; |
| 68 | int num_channels; |
| 69 | int speed; |
| 70 | uint32_t ch0; |
| 71 | uint32_t ch1; |
| 72 | |
| 73 | reg = pci_read_config32(soc_dev, mrc_ver_reg); |
| 74 | |
| 75 | printk(BIOS_INFO, "MRC v%d.%02d\n", (reg >> 8) & 0xff, reg & 0xff); |
| 76 | |
| 77 | /* Number of channels enabled and DDR3 type. Determine number of |
| 78 | * channels by keying of the rank enable bits [3:0]. * */ |
| 79 | ch0 = iosf_dunit_ch0_read(DRP); |
| 80 | ch1 = iosf_dunit_ch1_read(DRP); |
| 81 | num_channels = 0; |
| 82 | if (ch0 & DRP_RANK_MASK) |
| 83 | num_channels++; |
| 84 | if (ch1 & DRP_RANK_MASK) |
| 85 | num_channels++; |
| 86 | |
| 87 | printk(BIOS_INFO, "%d channels of %sDDR3 @ ", num_channels, |
| 88 | (reg & (1 << 22)) ? "LP" : ""); |
| 89 | |
| 90 | /* DRAM frequency -- all channels run at same frequency. */ |
| 91 | reg = iosf_dunit_read(DTR0); |
| 92 | switch (reg & 0x3) { |
| 93 | case 0: |
| 94 | speed = 800; break; |
| 95 | case 1: |
| 96 | speed = 1066; break; |
| 97 | case 2: |
| 98 | speed = 1333; break; |
| 99 | case 3: |
| 100 | speed = 1600; break; |
| 101 | } |
| 102 | printk(BIOS_INFO, "%dMHz\n", speed); |
| 103 | } |
| 104 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 105 | void raminit(struct mrc_params *mp, int prev_sleep_state) |
| 106 | { |
| 107 | int ret; |
| 108 | mrc_wrapper_entry_t mrc_entry; |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 109 | struct region_device rdev; |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 110 | |
| 111 | /* Fill in default entries. */ |
| 112 | mp->version = MRC_PARAMS_VER; |
Aaron Durbin | 833ff35 | 2013-10-02 11:06:31 -0500 | [diff] [blame] | 113 | mp->console_out = &send_to_console; |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 114 | mp->prev_sleep_state = prev_sleep_state; |
Patrick Georgi | 5b33dc1 | 2014-05-07 20:20:10 +0200 | [diff] [blame] | 115 | mp->rmt_enabled = IS_ENABLED(CONFIG_MRC_RMT); |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 116 | |
| 117 | /* Default to 2GiB IO hole. */ |
| 118 | if (!mp->io_hole_mb) |
| 119 | mp->io_hole_mb = 2048; |
| 120 | |
Furquan Shaikh | 0325dc6 | 2016-07-25 13:02:36 -0700 | [diff] [blame] | 121 | if (vboot_recovery_mode_enabled()) { |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 122 | printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n"); |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 123 | } else if (!mrc_cache_get_current(MRC_TRAINING_DATA, 0, &rdev)) { |
| 124 | mp->saved_data_size = region_device_sz(&rdev); |
| 125 | mp->saved_data = rdev_mmap_full(&rdev); |
| 126 | /* Assume boot device is memory mapped. */ |
| 127 | assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); |
Aaron Durbin | f5cfaa3 | 2016-07-13 23:20:07 -0500 | [diff] [blame] | 128 | } else if (prev_sleep_state == ACPI_S3) { |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 129 | /* If waking from S3 and no cache then. */ |
| 130 | printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n"); |
| 131 | post_code(POST_RESUME_FAILURE); |
Patrick Rudolph | 45022ae | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 132 | system_reset(); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 133 | } else { |
| 134 | printk(BIOS_DEBUG, "No MRC cache found.\n"); |
| 135 | } |
| 136 | |
Aaron Durbin | 1131889 | 2014-04-02 20:46:13 -0500 | [diff] [blame] | 137 | /* Determine if mrc.bin is in the cbfs. */ |
Aaron Durbin | 899d13d | 2015-05-15 23:39:23 -0500 | [diff] [blame] | 138 | if (cbfs_boot_map_with_leak("mrc.bin", CBFS_TYPE_MRC, NULL) == NULL) { |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 139 | printk(BIOS_DEBUG, "Couldn't find mrc.bin\n"); |
| 140 | return; |
| 141 | } |
Aaron Durbin | 1131889 | 2014-04-02 20:46:13 -0500 | [diff] [blame] | 142 | |
| 143 | /* |
| 144 | * The entry point is currently the first instruction. Handle the |
| 145 | * case of an ELF file being put in the cbfs by setting the entry |
| 146 | * to the CONFIG_MRC_BIN_ADDRESS. |
| 147 | */ |
| 148 | mrc_entry = (void *)(uintptr_t)CONFIG_MRC_BIN_ADDRESS; |
| 149 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 150 | if (mp->mainboard.dram_info_location == DRAM_INFO_SPD_SMBUS) |
| 151 | enable_smbus(); |
| 152 | |
| 153 | ret = mrc_entry(mp); |
| 154 | |
Aaron Durbin | 3ccb3ce | 2013-10-11 00:26:04 -0500 | [diff] [blame] | 155 | print_dram_info(); |
| 156 | |
Aaron Durbin | f5cfaa3 | 2016-07-13 23:20:07 -0500 | [diff] [blame] | 157 | if (prev_sleep_state != ACPI_S3) { |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 158 | cbmem_initialize_empty(); |
Aaron Durbin | 42e6856 | 2015-06-09 13:55:51 -0500 | [diff] [blame] | 159 | } else if (cbmem_initialize()) { |
Martin Roth | e6ff159 | 2017-06-24 21:34:29 -0600 | [diff] [blame] | 160 | #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) |
Aaron Durbin | 42e6856 | 2015-06-09 13:55:51 -0500 | [diff] [blame] | 161 | printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); |
| 162 | /* Failed S3 resume, reset to come up cleanly */ |
Patrick Rudolph | 45022ae | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 163 | system_reset(); |
Aaron Durbin | 42e6856 | 2015-06-09 13:55:51 -0500 | [diff] [blame] | 164 | #endif |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 165 | } |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 166 | |
| 167 | printk(BIOS_DEBUG, "MRC Wrapper returned %d\n", ret); |
| 168 | printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", mp->data_to_save, |
| 169 | mp->data_to_save_size); |
| 170 | |
| 171 | if (mp->data_to_save != NULL && mp->data_to_save_size > 0) |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 172 | mrc_cache_stash_data(MRC_TRAINING_DATA, 0, mp->data_to_save, |
| 173 | mp->data_to_save_size); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 174 | } |