intel: Use CF9 reset (part 1)
Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to
perform a "system reset" in their hard_reset() implementation. Replace
all duplicate CF9 reset implementations for these platforms.
Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c
index 45bc75b..cc055c0 100644
--- a/src/soc/intel/baytrail/romstage/raminit.c
+++ b/src/soc/intel/baytrail/romstage/raminit.c
@@ -18,6 +18,7 @@
#include <assert.h>
#include <cbfs.h>
#include <cbmem.h>
+#include <cf9_reset.h>
#include <console/console.h>
#include <device/pci_def.h>
#include <halt.h>
@@ -26,18 +27,11 @@
#include <soc/iomap.h>
#include <soc/iosf.h>
#include <soc/pci_devs.h>
-#include <soc/reset.h>
#include <soc/romstage.h>
#include <ec/google/chromeec/ec.h>
#include <ec/google/chromeec/ec_commands.h>
#include <security/vboot/vboot_common.h>
-static void reset_system(void)
-{
- warm_reset();
- halt();
-}
-
static void enable_smbus(void)
{
uint32_t reg;
@@ -134,7 +128,7 @@
/* If waking from S3 and no cache then. */
printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n");
post_code(POST_RESUME_FAILURE);
- reset_system();
+ system_reset();
} else {
printk(BIOS_DEBUG, "No MRC cache found.\n");
}
@@ -165,7 +159,7 @@
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
/* Failed S3 resume, reset to come up cleanly */
- reset_system();
+ system_reset();
#endif
}