Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | |
| 18 | #include <device/device.h> |
| 19 | #include <device/pci.h> |
| 20 | #include <console/console.h> |
| 21 | #include <arch/io.h> |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 22 | #include <cpu/x86/cache.h> |
| 23 | #include <cpu/x86/smm.h> |
Kyösti Mälkki | f091f4d | 2019-08-14 03:49:21 +0300 | [diff] [blame^] | 24 | #include <cpu/intel/smm_reloc.h> |
Patrick Rudolph | ed3242e | 2018-06-29 10:34:37 +0200 | [diff] [blame] | 25 | #include <southbridge/intel/common/pmbase.h> |
Arthur Heymans | f0a017f | 2018-12-25 15:26:58 +0100 | [diff] [blame] | 26 | #include <southbridge/intel/common/pmutil.h> |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 27 | |
| 28 | #include "pmutil.h" |
| 29 | |
| 30 | #define DEBUG_PERIODIC_SMIS 0 |
| 31 | |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 32 | u16 get_pmbase(void) |
| 33 | { |
Patrick Rudolph | ed3242e | 2018-06-29 10:34:37 +0200 | [diff] [blame] | 34 | return lpc_get_pmbase(); |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 35 | } |
| 36 | |
| 37 | void southbridge_smm_init(void) |
| 38 | { |
| 39 | u32 smi_en; |
| 40 | u16 pm1_en; |
| 41 | u32 gpe0_en; |
| 42 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 43 | if (CONFIG(ELOG)) |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 44 | /* Log events from chipset before clearing */ |
Arthur Heymans | f0a017f | 2018-12-25 15:26:58 +0100 | [diff] [blame] | 45 | pch_log_state(); |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 46 | |
| 47 | printk(BIOS_DEBUG, "Initializing southbridge SMI..."); |
| 48 | |
Patrick Rudolph | ed3242e | 2018-06-29 10:34:37 +0200 | [diff] [blame] | 49 | printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", lpc_get_pmbase()); |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 50 | |
Patrick Rudolph | ed3242e | 2018-06-29 10:34:37 +0200 | [diff] [blame] | 51 | smi_en = read_pmbase32(SMI_EN); |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 52 | if (smi_en & APMC_EN) { |
| 53 | printk(BIOS_INFO, "SMI# handler already enabled?\n"); |
| 54 | return; |
| 55 | } |
| 56 | |
| 57 | printk(BIOS_DEBUG, "\n"); |
| 58 | dump_smi_status(reset_smi_status()); |
| 59 | dump_pm1_status(reset_pm1_status()); |
| 60 | dump_gpe0_status(reset_gpe0_status()); |
| 61 | dump_alt_gp_smi_status(reset_alt_gp_smi_status()); |
| 62 | dump_tco_status(reset_tco_status()); |
| 63 | |
| 64 | /* Disable GPE0 PME_B0 */ |
Patrick Rudolph | ed3242e | 2018-06-29 10:34:37 +0200 | [diff] [blame] | 65 | gpe0_en = read_pmbase32(GPE0_EN); |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 66 | gpe0_en &= ~PME_B0_EN; |
Patrick Rudolph | ed3242e | 2018-06-29 10:34:37 +0200 | [diff] [blame] | 67 | write_pmbase32(GPE0_EN, gpe0_en); |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 68 | |
| 69 | pm1_en = 0; |
| 70 | pm1_en |= PWRBTN_EN; |
| 71 | pm1_en |= GBL_EN; |
Patrick Rudolph | ed3242e | 2018-06-29 10:34:37 +0200 | [diff] [blame] | 72 | write_pmbase16(PM1_EN, pm1_en); |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 73 | |
| 74 | /* Enable SMI generation: |
| 75 | * - on TCO events |
| 76 | * - on APMC writes (io 0xb2) |
| 77 | * - on writes to SLP_EN (sleep states) |
| 78 | * - on writes to GBL_RLS (bios commands) |
| 79 | * No SMIs: |
| 80 | * - on microcontroller writes (io 0x62/0x66) |
| 81 | */ |
| 82 | |
| 83 | smi_en = 0; /* reset SMI enables */ |
| 84 | |
| 85 | #if 0 |
| 86 | smi_en |= LEGACY_USB2_EN | LEGACY_USB_EN; |
| 87 | #endif |
| 88 | smi_en |= TCO_EN; |
| 89 | smi_en |= APMC_EN; |
| 90 | #if DEBUG_PERIODIC_SMIS |
| 91 | /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using |
| 92 | * periodic SMIs. |
| 93 | */ |
| 94 | smi_en |= PERIODIC_EN; |
| 95 | #endif |
| 96 | smi_en |= SLP_SMI_EN; |
| 97 | #if 0 |
| 98 | smi_en |= BIOS_EN; |
| 99 | #endif |
| 100 | |
| 101 | /* The following need to be on for SMIs to happen */ |
| 102 | smi_en |= EOS | GBL_SMI_EN; |
| 103 | |
Patrick Rudolph | ed3242e | 2018-06-29 10:34:37 +0200 | [diff] [blame] | 104 | write_pmbase32(SMI_EN, smi_en); |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 105 | } |
| 106 | |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 107 | void smm_setup_structures(void *gnvs, void *tcg, void *smi1) |
| 108 | { |
| 109 | /* |
| 110 | * Issue SMI to set the gnvs pointer in SMM. |
| 111 | * tcg and smi1 are unused. |
| 112 | * |
| 113 | * EAX = APM_CNT_GNVS_UPDATE |
| 114 | * EBX = gnvs pointer |
| 115 | * EDX = APM_CNT |
| 116 | */ |
| 117 | asm volatile ( |
| 118 | "outb %%al, %%dx\n\t" |
| 119 | : /* ignore result */ |
| 120 | : "a" (APM_CNT_GNVS_UPDATE), |
Patrick Rudolph | 4af2add | 2018-11-26 15:56:11 +0100 | [diff] [blame] | 121 | "b" ((uintptr_t)gnvs), |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 122 | "d" (APM_CNT) |
| 123 | ); |
| 124 | } |
Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 125 | |
| 126 | void southbridge_smm_clear_state(void) |
| 127 | { |
| 128 | u32 smi_en; |
| 129 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 130 | if (CONFIG(ELOG)) |
Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 131 | /* Log events from chipset before clearing */ |
| 132 | pch_log_state(); |
| 133 | |
| 134 | printk(BIOS_DEBUG, "Initializing Southbridge SMI...\n"); |
| 135 | printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", get_pmbase()); |
| 136 | |
| 137 | smi_en = inl(get_pmbase() + SMI_EN); |
| 138 | if (smi_en & APMC_EN) { |
| 139 | printk(BIOS_INFO, "SMI# handler already enabled?\n"); |
| 140 | return; |
| 141 | } |
| 142 | |
| 143 | printk(BIOS_DEBUG, "\n"); |
| 144 | |
| 145 | /* Dump and clear status registers */ |
| 146 | reset_smi_status(); |
| 147 | reset_pm1_status(); |
| 148 | reset_tco_status(); |
| 149 | reset_gpe0_status(); |
| 150 | } |