Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | |
| 18 | #include <device/device.h> |
| 19 | #include <device/pci.h> |
| 20 | #include <console/console.h> |
| 21 | #include <arch/io.h> |
| 22 | #include <cpu/cpu.h> |
| 23 | #include <cpu/x86/cache.h> |
| 24 | #include <cpu/x86/smm.h> |
| 25 | #include <cpu/intel/smm/gen1/smi.h> |
Patrick Rudolph | ed3242e | 2018-06-29 10:34:37 +0200 | [diff] [blame^] | 26 | #include <southbridge/intel/common/pmbase.h> |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 27 | |
| 28 | #include "pmutil.h" |
| 29 | |
| 30 | #define DEBUG_PERIODIC_SMIS 0 |
| 31 | |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 32 | u16 get_pmbase(void) |
| 33 | { |
Patrick Rudolph | ed3242e | 2018-06-29 10:34:37 +0200 | [diff] [blame^] | 34 | return lpc_get_pmbase(); |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 35 | } |
| 36 | |
| 37 | void southbridge_smm_init(void) |
| 38 | { |
| 39 | u32 smi_en; |
| 40 | u16 pm1_en; |
| 41 | u32 gpe0_en; |
| 42 | |
| 43 | #if IS_ENABLED(CONFIG_ELOG) |
| 44 | /* Log events from chipset before clearing */ |
| 45 | pch_log_state(); |
| 46 | #endif |
| 47 | |
| 48 | printk(BIOS_DEBUG, "Initializing southbridge SMI..."); |
| 49 | |
Patrick Rudolph | ed3242e | 2018-06-29 10:34:37 +0200 | [diff] [blame^] | 50 | printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", lpc_get_pmbase()); |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 51 | |
Patrick Rudolph | ed3242e | 2018-06-29 10:34:37 +0200 | [diff] [blame^] | 52 | smi_en = read_pmbase32(SMI_EN); |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 53 | if (smi_en & APMC_EN) { |
| 54 | printk(BIOS_INFO, "SMI# handler already enabled?\n"); |
| 55 | return; |
| 56 | } |
| 57 | |
| 58 | printk(BIOS_DEBUG, "\n"); |
| 59 | dump_smi_status(reset_smi_status()); |
| 60 | dump_pm1_status(reset_pm1_status()); |
| 61 | dump_gpe0_status(reset_gpe0_status()); |
| 62 | dump_alt_gp_smi_status(reset_alt_gp_smi_status()); |
| 63 | dump_tco_status(reset_tco_status()); |
| 64 | |
| 65 | /* Disable GPE0 PME_B0 */ |
Patrick Rudolph | ed3242e | 2018-06-29 10:34:37 +0200 | [diff] [blame^] | 66 | gpe0_en = read_pmbase32(GPE0_EN); |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 67 | gpe0_en &= ~PME_B0_EN; |
Patrick Rudolph | ed3242e | 2018-06-29 10:34:37 +0200 | [diff] [blame^] | 68 | write_pmbase32(GPE0_EN, gpe0_en); |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 69 | |
| 70 | pm1_en = 0; |
| 71 | pm1_en |= PWRBTN_EN; |
| 72 | pm1_en |= GBL_EN; |
Patrick Rudolph | ed3242e | 2018-06-29 10:34:37 +0200 | [diff] [blame^] | 73 | write_pmbase16(PM1_EN, pm1_en); |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 74 | |
| 75 | /* Enable SMI generation: |
| 76 | * - on TCO events |
| 77 | * - on APMC writes (io 0xb2) |
| 78 | * - on writes to SLP_EN (sleep states) |
| 79 | * - on writes to GBL_RLS (bios commands) |
| 80 | * No SMIs: |
| 81 | * - on microcontroller writes (io 0x62/0x66) |
| 82 | */ |
| 83 | |
| 84 | smi_en = 0; /* reset SMI enables */ |
| 85 | |
| 86 | #if 0 |
| 87 | smi_en |= LEGACY_USB2_EN | LEGACY_USB_EN; |
| 88 | #endif |
| 89 | smi_en |= TCO_EN; |
| 90 | smi_en |= APMC_EN; |
| 91 | #if DEBUG_PERIODIC_SMIS |
| 92 | /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using |
| 93 | * periodic SMIs. |
| 94 | */ |
| 95 | smi_en |= PERIODIC_EN; |
| 96 | #endif |
| 97 | smi_en |= SLP_SMI_EN; |
| 98 | #if 0 |
| 99 | smi_en |= BIOS_EN; |
| 100 | #endif |
| 101 | |
| 102 | /* The following need to be on for SMIs to happen */ |
| 103 | smi_en |= EOS | GBL_SMI_EN; |
| 104 | |
Patrick Rudolph | ed3242e | 2018-06-29 10:34:37 +0200 | [diff] [blame^] | 105 | write_pmbase32(SMI_EN, smi_en); |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 106 | } |
| 107 | |
| 108 | void southbridge_trigger_smi(void) |
| 109 | { |
| 110 | /** |
| 111 | * There are several methods of raising a controlled SMI# via |
| 112 | * software, among them: |
| 113 | * - Writes to io 0xb2 (APMC) |
| 114 | * - Writes to the Local Apic ICR with Delivery mode SMI. |
| 115 | * |
| 116 | * Using the local apic is a bit more tricky. According to |
| 117 | * AMD Family 11 Processor BKDG no destination shorthand must be |
| 118 | * used. |
| 119 | * The whole SMM initialization is quite a bit hardware specific, so |
| 120 | * I'm not too worried about the better of the methods at the moment |
| 121 | */ |
| 122 | |
| 123 | /* raise an SMI interrupt */ |
| 124 | printk(BIOS_SPEW, " ... raise SMI#\n"); |
| 125 | outb(0x00, 0xb2); |
| 126 | } |
| 127 | |
| 128 | void southbridge_clear_smi_status(void) |
| 129 | { |
| 130 | /* Clear SMI status */ |
| 131 | reset_smi_status(); |
| 132 | |
| 133 | /* Clear PM1 status */ |
| 134 | reset_pm1_status(); |
| 135 | |
| 136 | /* Set EOS bit so other SMIs can occur. */ |
| 137 | smi_set_eos(); |
| 138 | } |
| 139 | |
| 140 | void smm_setup_structures(void *gnvs, void *tcg, void *smi1) |
| 141 | { |
| 142 | /* |
| 143 | * Issue SMI to set the gnvs pointer in SMM. |
| 144 | * tcg and smi1 are unused. |
| 145 | * |
| 146 | * EAX = APM_CNT_GNVS_UPDATE |
| 147 | * EBX = gnvs pointer |
| 148 | * EDX = APM_CNT |
| 149 | */ |
| 150 | asm volatile ( |
| 151 | "outb %%al, %%dx\n\t" |
| 152 | : /* ignore result */ |
| 153 | : "a" (APM_CNT_GNVS_UPDATE), |
| 154 | "b" ((u32)gnvs), |
| 155 | "d" (APM_CNT) |
| 156 | ); |
| 157 | } |