Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | |
| 18 | #include <device/device.h> |
| 19 | #include <device/pci.h> |
| 20 | #include <console/console.h> |
| 21 | #include <arch/io.h> |
| 22 | #include <cpu/cpu.h> |
| 23 | #include <cpu/x86/cache.h> |
| 24 | #include <cpu/x86/smm.h> |
| 25 | #include <cpu/intel/smm/gen1/smi.h> |
| 26 | |
| 27 | #include "pmutil.h" |
| 28 | |
| 29 | #define DEBUG_PERIODIC_SMIS 0 |
| 30 | |
| 31 | static u16 pmbase; |
| 32 | |
| 33 | u16 get_pmbase(void) |
| 34 | { |
| 35 | return pmbase; |
| 36 | } |
| 37 | |
| 38 | void southbridge_smm_init(void) |
| 39 | { |
| 40 | u32 smi_en; |
| 41 | u16 pm1_en; |
| 42 | u32 gpe0_en; |
| 43 | |
| 44 | #if IS_ENABLED(CONFIG_ELOG) |
| 45 | /* Log events from chipset before clearing */ |
| 46 | pch_log_state(); |
| 47 | #endif |
| 48 | |
| 49 | printk(BIOS_DEBUG, "Initializing southbridge SMI..."); |
| 50 | |
| 51 | pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), |
| 52 | D31F0_PMBASE) & 0xff80; |
| 53 | |
| 54 | printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); |
| 55 | |
| 56 | smi_en = inl(pmbase + SMI_EN); |
| 57 | if (smi_en & APMC_EN) { |
| 58 | printk(BIOS_INFO, "SMI# handler already enabled?\n"); |
| 59 | return; |
| 60 | } |
| 61 | |
| 62 | printk(BIOS_DEBUG, "\n"); |
| 63 | dump_smi_status(reset_smi_status()); |
| 64 | dump_pm1_status(reset_pm1_status()); |
| 65 | dump_gpe0_status(reset_gpe0_status()); |
| 66 | dump_alt_gp_smi_status(reset_alt_gp_smi_status()); |
| 67 | dump_tco_status(reset_tco_status()); |
| 68 | |
| 69 | /* Disable GPE0 PME_B0 */ |
| 70 | gpe0_en = inl(pmbase + GPE0_EN); |
| 71 | gpe0_en &= ~PME_B0_EN; |
| 72 | outl(gpe0_en, pmbase + GPE0_EN); |
| 73 | |
| 74 | pm1_en = 0; |
| 75 | pm1_en |= PWRBTN_EN; |
| 76 | pm1_en |= GBL_EN; |
| 77 | outw(pm1_en, pmbase + PM1_EN); |
| 78 | |
| 79 | /* Enable SMI generation: |
| 80 | * - on TCO events |
| 81 | * - on APMC writes (io 0xb2) |
| 82 | * - on writes to SLP_EN (sleep states) |
| 83 | * - on writes to GBL_RLS (bios commands) |
| 84 | * No SMIs: |
| 85 | * - on microcontroller writes (io 0x62/0x66) |
| 86 | */ |
| 87 | |
| 88 | smi_en = 0; /* reset SMI enables */ |
| 89 | |
| 90 | #if 0 |
| 91 | smi_en |= LEGACY_USB2_EN | LEGACY_USB_EN; |
| 92 | #endif |
| 93 | smi_en |= TCO_EN; |
| 94 | smi_en |= APMC_EN; |
| 95 | #if DEBUG_PERIODIC_SMIS |
| 96 | /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using |
| 97 | * periodic SMIs. |
| 98 | */ |
| 99 | smi_en |= PERIODIC_EN; |
| 100 | #endif |
| 101 | smi_en |= SLP_SMI_EN; |
| 102 | #if 0 |
| 103 | smi_en |= BIOS_EN; |
| 104 | #endif |
| 105 | |
| 106 | /* The following need to be on for SMIs to happen */ |
| 107 | smi_en |= EOS | GBL_SMI_EN; |
| 108 | |
| 109 | outl(smi_en, pmbase + SMI_EN); |
| 110 | } |
| 111 | |
| 112 | void southbridge_trigger_smi(void) |
| 113 | { |
| 114 | /** |
| 115 | * There are several methods of raising a controlled SMI# via |
| 116 | * software, among them: |
| 117 | * - Writes to io 0xb2 (APMC) |
| 118 | * - Writes to the Local Apic ICR with Delivery mode SMI. |
| 119 | * |
| 120 | * Using the local apic is a bit more tricky. According to |
| 121 | * AMD Family 11 Processor BKDG no destination shorthand must be |
| 122 | * used. |
| 123 | * The whole SMM initialization is quite a bit hardware specific, so |
| 124 | * I'm not too worried about the better of the methods at the moment |
| 125 | */ |
| 126 | |
| 127 | /* raise an SMI interrupt */ |
| 128 | printk(BIOS_SPEW, " ... raise SMI#\n"); |
| 129 | outb(0x00, 0xb2); |
| 130 | } |
| 131 | |
| 132 | void southbridge_clear_smi_status(void) |
| 133 | { |
| 134 | /* Clear SMI status */ |
| 135 | reset_smi_status(); |
| 136 | |
| 137 | /* Clear PM1 status */ |
| 138 | reset_pm1_status(); |
| 139 | |
| 140 | /* Set EOS bit so other SMIs can occur. */ |
| 141 | smi_set_eos(); |
| 142 | } |
| 143 | |
| 144 | void smm_setup_structures(void *gnvs, void *tcg, void *smi1) |
| 145 | { |
| 146 | /* |
| 147 | * Issue SMI to set the gnvs pointer in SMM. |
| 148 | * tcg and smi1 are unused. |
| 149 | * |
| 150 | * EAX = APM_CNT_GNVS_UPDATE |
| 151 | * EBX = gnvs pointer |
| 152 | * EDX = APM_CNT |
| 153 | */ |
| 154 | asm volatile ( |
| 155 | "outb %%al, %%dx\n\t" |
| 156 | : /* ignore result */ |
| 157 | : "a" (APM_CNT_GNVS_UPDATE), |
| 158 | "b" ((u32)gnvs), |
| 159 | "d" (APM_CNT) |
| 160 | ); |
| 161 | } |