Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <device/device.h> |
| 4 | #include <device/pci.h> |
| 5 | #include <fsp/api.h> |
| 6 | #include <fsp/util.h> |
Dinesh Gehlot | 166c75c7 | 2023-01-03 05:26:19 +0000 | [diff] [blame] | 7 | #include <gpio.h> |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 8 | #include <intelblocks/acpi.h> |
| 9 | #include <intelblocks/cfg.h> |
Subrata Banik | ad42d9c | 2023-04-19 18:30:53 +0530 | [diff] [blame] | 10 | #include <intelblocks/cse.h> |
Kapil Porwal | cca3c90 | 2022-12-19 23:57:15 +0530 | [diff] [blame] | 11 | #include <intelblocks/irq.h> |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 12 | #include <intelblocks/itss.h> |
John Zhao | 54a03e4 | 2022-08-03 20:07:03 -0700 | [diff] [blame] | 13 | #include <intelblocks/p2sb.h> |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 14 | #include <intelblocks/pcie_rp.h> |
| 15 | #include <intelblocks/systemagent.h> |
John Zhao | 54a03e4 | 2022-08-03 20:07:03 -0700 | [diff] [blame] | 16 | #include <intelblocks/tcss.h> |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 17 | #include <intelblocks/xdci.h> |
Subrata Banik | 9405541 | 2023-05-17 14:33:55 +0530 | [diff] [blame] | 18 | #include <soc/intel/common/reset.h> |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 19 | #include <soc/intel/common/vbt.h> |
John Zhao | 54a03e4 | 2022-08-03 20:07:03 -0700 | [diff] [blame] | 20 | #include <soc/iomap.h> |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 21 | #include <soc/itss.h> |
| 22 | #include <soc/p2sb.h> |
| 23 | #include <soc/pci_devs.h> |
| 24 | #include <soc/pcie.h> |
| 25 | #include <soc/ramstage.h> |
| 26 | #include <soc/soc_chip.h> |
John Zhao | 54a03e4 | 2022-08-03 20:07:03 -0700 | [diff] [blame] | 27 | #include <soc/tcss.h> |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 28 | |
| 29 | #if CONFIG(HAVE_ACPI_TABLES) |
| 30 | const char *soc_acpi_name(const struct device *dev) |
| 31 | { |
| 32 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 33 | return "PCI0"; |
| 34 | |
| 35 | if (dev->path.type == DEVICE_PATH_USB) { |
| 36 | switch (dev->path.usb.port_type) { |
| 37 | case 0: |
| 38 | /* Root Hub */ |
| 39 | return "RHUB"; |
| 40 | case 2: |
| 41 | /* USB2 ports */ |
| 42 | switch (dev->path.usb.port_id) { |
| 43 | case 0: return "HS01"; |
| 44 | case 1: return "HS02"; |
| 45 | case 2: return "HS03"; |
| 46 | case 3: return "HS04"; |
| 47 | case 4: return "HS05"; |
| 48 | case 5: return "HS06"; |
| 49 | case 6: return "HS07"; |
| 50 | case 7: return "HS08"; |
| 51 | case 8: return "HS09"; |
| 52 | case 9: return "HS10"; |
| 53 | } |
| 54 | break; |
| 55 | case 3: |
| 56 | /* USB3 ports */ |
| 57 | switch (dev->path.usb.port_id) { |
| 58 | case 0: return "SS01"; |
| 59 | case 1: return "SS02"; |
| 60 | case 2: return "SS03"; |
| 61 | case 3: return "SS04"; |
| 62 | } |
| 63 | break; |
| 64 | } |
| 65 | printk(BIOS_DEBUG, "dev->path.type=%x\n", dev->path.usb.port_type); |
| 66 | return NULL; |
| 67 | } |
| 68 | if (dev->path.type != DEVICE_PATH_PCI) { |
| 69 | printk(BIOS_DEBUG, "dev->path.type=%x\n", dev->path.type); |
| 70 | return NULL; |
| 71 | } |
| 72 | |
| 73 | switch (dev->path.pci.devfn) { |
| 74 | case PCI_DEVFN_ROOT: return "MCHC"; |
Won Chung | ede5564 | 2023-05-16 17:11:21 +0000 | [diff] [blame] | 75 | case PCI_DEVFN_IGD: return "GFX0"; |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 76 | case PCI_DEVFN_TCSS_XHCI: return "TXHC"; |
| 77 | case PCI_DEVFN_TCSS_XDCI: return "TXDC"; |
| 78 | case PCI_DEVFN_TCSS_DMA0: return "TDM0"; |
| 79 | case PCI_DEVFN_TCSS_DMA1: return "TDM1"; |
| 80 | case PCI_DEVFN_TBT0: return "TRP0"; |
| 81 | case PCI_DEVFN_TBT1: return "TRP1"; |
| 82 | case PCI_DEVFN_TBT2: return "TRP2"; |
| 83 | case PCI_DEVFN_TBT3: return "TRP3"; |
| 84 | case PCI_DEVFN_IPU: return "IPU0"; |
| 85 | case PCI_DEVFN_ISH: return "ISHB"; |
| 86 | case PCI_DEVFN_XHCI: return "XHCI"; |
| 87 | case PCI_DEVFN_I2C0: return "I2C0"; |
| 88 | case PCI_DEVFN_I2C1: return "I2C1"; |
| 89 | case PCI_DEVFN_I2C2: return "I2C2"; |
| 90 | case PCI_DEVFN_I2C3: return "I2C3"; |
| 91 | case PCI_DEVFN_I2C4: return "I2C4"; |
| 92 | case PCI_DEVFN_I2C5: return "I2C5"; |
| 93 | case PCI_DEVFN_SATA: return "SATA"; |
| 94 | case PCI_DEVFN_PCIE1: return "RP01"; |
| 95 | case PCI_DEVFN_PCIE2: return "RP02"; |
| 96 | case PCI_DEVFN_PCIE3: return "RP03"; |
| 97 | case PCI_DEVFN_PCIE4: return "RP04"; |
| 98 | case PCI_DEVFN_PCIE5: return "RP05"; |
| 99 | case PCI_DEVFN_PCIE6: return "RP06"; |
| 100 | case PCI_DEVFN_PCIE7: return "RP07"; |
| 101 | case PCI_DEVFN_PCIE8: return "RP08"; |
| 102 | case PCI_DEVFN_PCIE9: return "RP09"; |
| 103 | case PCI_DEVFN_PCIE10: return "RP10"; |
| 104 | case PCI_DEVFN_PCIE11: return "RP11"; |
| 105 | case PCI_DEVFN_PCIE12: return "RP12"; |
| 106 | case PCI_DEVFN_PMC: return "PMC"; |
| 107 | case PCI_DEVFN_UART0: return "UAR0"; |
| 108 | case PCI_DEVFN_UART1: return "UAR1"; |
| 109 | case PCI_DEVFN_UART2: return "UAR2"; |
| 110 | case PCI_DEVFN_GSPI0: return "SPI0"; |
| 111 | case PCI_DEVFN_GSPI1: return "SPI1"; |
Angel Pons | c7c746c | 2022-07-16 12:37:38 +0200 | [diff] [blame] | 112 | case PCI_DEVFN_GSPI2: return "SPI2"; |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 113 | /* Keeping ACPI device name coherent with ec.asl */ |
| 114 | case PCI_DEVFN_ESPI: return "LPCB"; |
| 115 | case PCI_DEVFN_HDA: return "HDAS"; |
| 116 | case PCI_DEVFN_SMBUS: return "SBUS"; |
| 117 | case PCI_DEVFN_GBE: return "GLAN"; |
| 118 | } |
Subrata Banik | e70bc42 | 2023-02-17 03:18:50 +0530 | [diff] [blame] | 119 | printk(BIOS_DEBUG, "Missing ACPI Name for PCI: 00:%02x.%01x\n", |
| 120 | PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn)); |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 121 | return NULL; |
| 122 | } |
| 123 | #endif |
| 124 | |
Subrata Banik | 5930263 | 2023-08-13 19:44:53 +0000 | [diff] [blame] | 125 | #if CONFIG(SOC_INTEL_STORE_ISH_FW_VERSION) |
| 126 | /* SoC override API to identify if ISH Firmware existed inside CSE FPT */ |
| 127 | bool soc_is_ish_partition_enabled(void) |
| 128 | { |
| 129 | struct device *ish = pcidev_path_on_root(PCI_DEVFN_ISH); |
| 130 | uint16_t ish_pci_id = ish ? pci_read_config16(ish, PCI_DEVICE_ID) : 0xFFFF; |
| 131 | |
| 132 | if (ish_pci_id == 0xFFFF) |
| 133 | return false; |
| 134 | |
| 135 | return true; |
| 136 | } |
| 137 | #endif |
| 138 | |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 139 | /* SoC routine to fill GPIO PM mask and value for GPIO_MISCCFG register */ |
| 140 | static void soc_fill_gpio_pm_configuration(void) |
| 141 | { |
| 142 | uint8_t value[TOTAL_GPIO_COMM]; |
| 143 | const config_t *config = config_of_soc(); |
| 144 | |
| 145 | if (config->gpio_override_pm) |
| 146 | memcpy(value, config->gpio_pm, sizeof(value)); |
| 147 | else |
| 148 | memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(value)); |
| 149 | |
| 150 | gpio_pm_configure(value, TOTAL_GPIO_COMM); |
| 151 | } |
| 152 | |
| 153 | void soc_init_pre_device(void *chip_info) |
| 154 | { |
John Zhao | 54a03e4 | 2022-08-03 20:07:03 -0700 | [diff] [blame] | 155 | config_t *config = config_of_soc(); |
| 156 | |
| 157 | /* Validate TBT image authentication */ |
| 158 | config->tbt_authentication = ioe_p2sb_sbi_read(PID_IOM, |
| 159 | IOM_CSME_IMR_TBT_STATUS) & TBT_VALID_AUTHENTICATION; |
| 160 | |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 161 | /* Perform silicon specific init. */ |
| 162 | fsp_silicon_init(); |
| 163 | |
| 164 | /* Display FIRMWARE_VERSION_INFO_HOB */ |
| 165 | fsp_display_fvi_version_hob(); |
| 166 | |
| 167 | soc_fill_gpio_pm_configuration(); |
| 168 | |
| 169 | /* Swap enabled PCI ports in device tree if needed. */ |
| 170 | pcie_rp_update_devicetree(get_pcie_rp_table()); |
Subrata Banik | ad42d9c | 2023-04-19 18:30:53 +0530 | [diff] [blame] | 171 | |
| 172 | /* |
| 173 | * Earlier when coreboot used to send EOP at late as possible caused |
| 174 | * issue of delayed response from CSE since CSE was busy loading payload. |
| 175 | * To resolve the issue, EOP should be sent earlier than current sequence |
| 176 | * in the boot sequence at BS_DEV_INIT. |
| 177 | * |
| 178 | * Intel CSE team recommends to send EOP close to FW init (between FSP-S |
| 179 | * exit and current boot sequence) to reduce message response time from |
| 180 | * CSE hence moving sending EOP to earlier stage. |
| 181 | */ |
| 182 | if (CONFIG(SOC_INTEL_CSE_SEND_EOP_EARLY) || |
| 183 | CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC)) { |
| 184 | printk(BIOS_INFO, "Sending EOP early from SoC\n"); |
| 185 | cse_send_end_of_post(); |
| 186 | } |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 187 | } |
| 188 | |
Kapil Porwal | cca3c90 | 2022-12-19 23:57:15 +0530 | [diff] [blame] | 189 | static void cpu_fill_ssdt(const struct device *dev) |
| 190 | { |
| 191 | if (!generate_pin_irq_map()) |
| 192 | printk(BIOS_ERR, "Failed to generate ACPI _PRT table!\n"); |
| 193 | |
| 194 | generate_cpu_entries(dev); |
| 195 | } |
| 196 | |
| 197 | static void cpu_set_north_irqs(struct device *dev) |
| 198 | { |
| 199 | irq_program_non_pch(); |
| 200 | } |
| 201 | |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 202 | static struct device_operations pci_domain_ops = { |
| 203 | .read_resources = &pci_domain_read_resources, |
| 204 | .set_resources = &pci_domain_set_resources, |
| 205 | .scan_bus = &pci_domain_scan_bus, |
| 206 | #if CONFIG(HAVE_ACPI_TABLES) |
| 207 | .acpi_name = &soc_acpi_name, |
| 208 | .acpi_fill_ssdt = ssdt_set_above_4g_pci, |
| 209 | #endif |
| 210 | }; |
| 211 | |
| 212 | static struct device_operations cpu_bus_ops = { |
| 213 | .read_resources = noop_read_resources, |
| 214 | .set_resources = noop_set_resources, |
Kapil Porwal | cca3c90 | 2022-12-19 23:57:15 +0530 | [diff] [blame] | 215 | .enable_resources = cpu_set_north_irqs, |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 216 | #if CONFIG(HAVE_ACPI_TABLES) |
Kapil Porwal | cca3c90 | 2022-12-19 23:57:15 +0530 | [diff] [blame] | 217 | .acpi_fill_ssdt = cpu_fill_ssdt, |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 218 | #endif |
| 219 | }; |
| 220 | |
| 221 | static void soc_enable(struct device *dev) |
| 222 | { |
| 223 | /* |
| 224 | * Set the operations if it is a special bus type or a hidden PCI |
| 225 | * device. |
| 226 | */ |
| 227 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 228 | dev->ops = &pci_domain_ops; |
| 229 | else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) |
| 230 | dev->ops = &cpu_bus_ops; |
| 231 | else if (dev->path.type == DEVICE_PATH_PCI && |
| 232 | dev->path.pci.devfn == PCI_DEVFN_PMC) |
| 233 | dev->ops = &pmc_ops; |
| 234 | else if (dev->path.type == DEVICE_PATH_PCI && |
Dinesh Gehlot | 095043f | 2023-08-18 10:04:53 +0530 | [diff] [blame] | 235 | dev->path.pci.devfn == PCI_DEVFN_IOE_PMC) |
| 236 | dev->ops = &ioe_pmc_ops; |
| 237 | else if (dev->path.type == DEVICE_PATH_PCI && |
Subrata Banik | 4ed30ca | 2022-10-27 15:44:54 +0530 | [diff] [blame] | 238 | dev->path.pci.devfn == PCI_DEVFN_P2SB) |
| 239 | dev->ops = &soc_p2sb_ops; |
| 240 | else if (dev->path.type == DEVICE_PATH_PCI && |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 241 | dev->path.pci.devfn == PCI_DEVFN_IOE_P2SB) |
| 242 | dev->ops = &ioe_p2sb_ops; |
| 243 | else if (dev->path.type == DEVICE_PATH_GPIO) |
| 244 | block_gpio_enable(dev); |
| 245 | } |
| 246 | |
Subrata Banik | 9405541 | 2023-05-17 14:33:55 +0530 | [diff] [blame] | 247 | static void soc_init_final_device(void *chip_info) |
| 248 | { |
| 249 | uint32_t reset_status = fsp_get_pch_reset_status(); |
| 250 | |
| 251 | if (reset_status == FSP_SUCCESS) |
| 252 | return; |
| 253 | |
| 254 | /* Handle any pending reset request from previously executed FSP APIs */ |
| 255 | fsp_handle_reset(reset_status); |
| 256 | |
| 257 | /* Control shouldn't return here */ |
lilacious | 40cb3fe | 2023-06-21 23:24:14 +0200 | [diff] [blame] | 258 | die_with_post_code(POSTCODE_HW_INIT_FAILURE, |
Subrata Banik | 9405541 | 2023-05-17 14:33:55 +0530 | [diff] [blame] | 259 | "Failed to handle the FSP reset request with error 0x%08x\n", reset_status); |
| 260 | } |
| 261 | |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 262 | struct chip_operations soc_intel_meteorlake_ops = { |
| 263 | CHIP_NAME("Intel Meteorlake") |
| 264 | .enable_dev = &soc_enable, |
| 265 | .init = &soc_init_pre_device, |
Subrata Banik | 9405541 | 2023-05-17 14:33:55 +0530 | [diff] [blame] | 266 | .final = &soc_init_final_device, |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 267 | }; |