Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2014 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <arch/cache.h> |
| 21 | #include <arch/cpu.h> |
| 22 | #include <arch/exception.h> |
Gabe Black | 4a12cfe | 2014-03-24 21:24:24 -0700 | [diff] [blame] | 23 | #include <arch/io.h> |
Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 24 | #include <cbfs.h> |
| 25 | #include <cbmem.h> |
| 26 | #include <console/console.h> |
Daisuke Nojiri | 512bfbc | 2014-08-15 17:07:39 -0700 | [diff] [blame] | 27 | #include <reset.h> |
Aaron Durbin | e4f3e7a | 2015-03-17 13:25:19 -0500 | [diff] [blame] | 28 | #include <program_loading.h> |
Aaron Durbin | cad7c4e | 2014-03-20 15:08:54 -0500 | [diff] [blame] | 29 | #include <romstage_handoff.h> |
| 30 | #include <vendorcode/google/chromeos/chromeos.h> |
Tom Warren | 64982c50 | 2014-01-23 13:37:50 -0700 | [diff] [blame] | 31 | #include "sdram_configs.h" |
Gabe Black | 4a12cfe | 2014-03-24 21:24:24 -0700 | [diff] [blame] | 32 | #include <soc/nvidia/tegra/i2c.h> |
Daisuke Nojiri | 1b05d88 | 2014-08-27 11:48:03 -0700 | [diff] [blame] | 33 | #include <soc/nvidia/tegra124/cache.h> |
Gabe Black | 4a12cfe | 2014-03-24 21:24:24 -0700 | [diff] [blame] | 34 | #include <soc/nvidia/tegra124/chip.h> |
| 35 | #include <soc/nvidia/tegra124/clk_rst.h> |
Daisuke Nojiri | 1b05d88 | 2014-08-27 11:48:03 -0700 | [diff] [blame] | 36 | #include <soc/nvidia/tegra124/early_configs.h> |
Gabe Black | c852206 | 2014-05-06 15:44:14 -0700 | [diff] [blame] | 37 | #include <soc/nvidia/tegra124/power.h> |
Gabe Black | 4a12cfe | 2014-03-24 21:24:24 -0700 | [diff] [blame] | 38 | #include <soc/nvidia/tegra124/sdram.h> |
| 39 | #include <soc/addressmap.h> |
| 40 | #include <soc/clock.h> |
Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 41 | #include <soc/display.h> |
| 42 | #include <timestamp.h> |
| 43 | |
Julius Werner | fd9defc | 2014-01-21 20:11:22 -0800 | [diff] [blame] | 44 | static void __attribute__((noinline)) romstage(void) |
Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 45 | { |
Kyösti Mälkki | f48b38b | 2014-12-31 08:50:36 +0200 | [diff] [blame] | 46 | timestamp_init(0); |
| 47 | timestamp_add_now(TS_START_ROMSTAGE); |
Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 48 | |
Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 49 | console_init(); |
| 50 | exception_init(); |
| 51 | |
Tom Warren | 64982c50 | 2014-01-23 13:37:50 -0700 | [diff] [blame] | 52 | sdram_init(get_sdram_config()); |
| 53 | |
Gabe Black | 5cbbc70 | 2014-02-08 05:17:38 -0800 | [diff] [blame] | 54 | /* used for MMU and CBMEM setup, in MB */ |
Tom Warren | 64982c50 | 2014-01-23 13:37:50 -0700 | [diff] [blame] | 55 | u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20); |
Gabe Black | 5cbbc70 | 2014-02-08 05:17:38 -0800 | [diff] [blame] | 56 | u32 dram_end = sdram_max_addressable_mb(); /* plus one... */ |
| 57 | u32 dram_size = dram_end - dram_start; |
Tom Warren | 64982c50 | 2014-01-23 13:37:50 -0700 | [diff] [blame] | 58 | |
Daisuke Nojiri | efddcfb | 2014-09-04 09:55:34 -0700 | [diff] [blame] | 59 | configure_l2_cache(); |
Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 60 | mmu_init(); |
Gabe Black | b9a4b71 | 2014-03-01 03:27:00 -0800 | [diff] [blame] | 61 | /* Device memory below DRAM is uncached. */ |
Tom Warren | 64982c50 | 2014-01-23 13:37:50 -0700 | [diff] [blame] | 62 | mmu_config_range(0, dram_start, DCACHE_OFF); |
Gabe Black | b9a4b71 | 2014-03-01 03:27:00 -0800 | [diff] [blame] | 63 | /* SRAM is cached. Round the size up to 2MB, the LPAE page size. */ |
| 64 | mmu_config_range(0x40000000 >> 20, 2, DCACHE_WRITEBACK); |
| 65 | /* DRAM is cached. */ |
Gabe Black | 5cbbc70 | 2014-02-08 05:17:38 -0800 | [diff] [blame] | 66 | mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK); |
Gabe Black | b9a4b71 | 2014-03-01 03:27:00 -0800 | [diff] [blame] | 67 | /* A window for DMA is uncached. */ |
Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 68 | mmu_config_range(CONFIG_DRAM_DMA_START >> 20, |
| 69 | CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF); |
Gabe Black | b9a4b71 | 2014-03-01 03:27:00 -0800 | [diff] [blame] | 70 | /* The space above DRAM is uncached. */ |
Gabe Black | 83ed805 | 2014-02-15 00:05:03 -0800 | [diff] [blame] | 71 | if (dram_end < 4096) |
| 72 | mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF); |
Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 73 | mmu_disable_range(0, 1); |
Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 74 | dcache_mmu_enable(); |
| 75 | |
Gabe Black | c852206 | 2014-05-06 15:44:14 -0700 | [diff] [blame] | 76 | /* |
| 77 | * A watchdog reset only resets part of the system so it ends up in |
| 78 | * a funny state. If that happens, we need to reset the whole machine. |
| 79 | */ |
| 80 | if (power_reset_status() == POWER_RESET_WATCHDOG) { |
| 81 | printk(BIOS_INFO, "Watchdog reset detected, rebooting.\n"); |
Daisuke Nojiri | 512bfbc | 2014-08-15 17:07:39 -0700 | [diff] [blame] | 82 | hard_reset(); |
Gabe Black | c852206 | 2014-05-06 15:44:14 -0700 | [diff] [blame] | 83 | } |
| 84 | |
Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 85 | cbmem_initialize_empty(); |
| 86 | |
Daisuke Nojiri | 1b05d88 | 2014-08-27 11:48:03 -0700 | [diff] [blame] | 87 | timestamp_init(0); |
| 88 | timestamp_add(TS_START_ROMSTAGE, romstage_start_time); |
Gabe Black | 4a12cfe | 2014-03-24 21:24:24 -0700 | [diff] [blame] | 89 | |
Daisuke Nojiri | 1b05d88 | 2014-08-27 11:48:03 -0700 | [diff] [blame] | 90 | early_mainboard_init(); |
Gabe Black | 4a12cfe | 2014-03-24 21:24:24 -0700 | [diff] [blame] | 91 | |
Aaron Durbin | cad7c4e | 2014-03-20 15:08:54 -0500 | [diff] [blame] | 92 | vboot_verify_firmware(romstage_handoff_find_or_add()); |
| 93 | |
Aaron Durbin | e4f3e7a | 2015-03-17 13:25:19 -0500 | [diff] [blame] | 94 | run_ramstage(); |
Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 95 | } |
Julius Werner | fd9defc | 2014-01-21 20:11:22 -0800 | [diff] [blame] | 96 | |
| 97 | /* Stub to force arm_init_caches to the top, before any stack/memory accesses */ |
| 98 | void main(void) |
| 99 | { |
Gabe Black | f220df6 | 2014-02-08 05:01:06 -0800 | [diff] [blame] | 100 | asm volatile ("bl arm_init_caches" |
| 101 | ::: "r0","r1","r2","r3","r4","r5","ip"); |
Julius Werner | fd9defc | 2014-01-21 20:11:22 -0800 | [diff] [blame] | 102 | romstage(); |
| 103 | } |