Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2014 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <arch/cache.h> |
| 21 | #include <arch/cpu.h> |
| 22 | #include <arch/exception.h> |
Gabe Black | 4a12cfe | 2014-03-24 21:24:24 -0700 | [diff] [blame] | 23 | #include <arch/io.h> |
Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 24 | #include <arch/stages.h> |
| 25 | #include <device/device.h> |
| 26 | #include <cbfs.h> |
| 27 | #include <cbmem.h> |
Gabe Black | 46e0975 | 2014-04-03 14:12:45 -0700 | [diff] [blame] | 28 | #include <console/cbmem_console.h> |
Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 29 | #include <console/console.h> |
Gabe Black | c852206 | 2014-05-06 15:44:14 -0700 | [diff] [blame^] | 30 | #include <mainboard/google/nyan/reset.h> |
Aaron Durbin | cad7c4e | 2014-03-20 15:08:54 -0500 | [diff] [blame] | 31 | #include <romstage_handoff.h> |
| 32 | #include <vendorcode/google/chromeos/chromeos.h> |
Tom Warren | 64982c50 | 2014-01-23 13:37:50 -0700 | [diff] [blame] | 33 | #include "sdram_configs.h" |
Gabe Black | 4a12cfe | 2014-03-24 21:24:24 -0700 | [diff] [blame] | 34 | #include <soc/nvidia/tegra/i2c.h> |
| 35 | #include <soc/nvidia/tegra124/chip.h> |
| 36 | #include <soc/nvidia/tegra124/clk_rst.h> |
Gabe Black | c852206 | 2014-05-06 15:44:14 -0700 | [diff] [blame^] | 37 | #include <soc/nvidia/tegra124/power.h> |
Gabe Black | 4a12cfe | 2014-03-24 21:24:24 -0700 | [diff] [blame] | 38 | #include <soc/nvidia/tegra124/sdram.h> |
| 39 | #include <soc/addressmap.h> |
| 40 | #include <soc/clock.h> |
Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 41 | #include <soc/display.h> |
| 42 | #include <timestamp.h> |
| 43 | |
Gabe Black | 4a12cfe | 2014-03-24 21:24:24 -0700 | [diff] [blame] | 44 | static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; |
| 45 | |
Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 46 | enum { |
| 47 | L2CTLR_ECC_PARITY = 0x1 << 21, |
| 48 | L2CTLR_TAG_RAM_LATENCY_MASK = 0x7 << 6, |
| 49 | L2CTLR_TAG_RAM_LATENCY_CYCLES_3 = 2 << 6, |
| 50 | L2CTLR_DATA_RAM_LATENCY_MASK = 0x7 << 0, |
| 51 | L2CTLR_DATA_RAM_LATENCY_CYCLES_3 = 2 << 0 |
| 52 | }; |
| 53 | |
| 54 | enum { |
| 55 | L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE = 0x1 << 27, |
| 56 | L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT = 0x1 << 7, |
| 57 | L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL = 0x1 << 3 |
| 58 | }; |
| 59 | |
| 60 | /* Configures L2 Control Register to use 3 cycles for DATA/TAG RAM latency. */ |
| 61 | static void configure_l2ctlr(void) |
| 62 | { |
| 63 | uint32_t val; |
| 64 | |
| 65 | val = read_l2ctlr(); |
| 66 | val &= ~(L2CTLR_DATA_RAM_LATENCY_MASK | L2CTLR_TAG_RAM_LATENCY_MASK); |
| 67 | val |= (L2CTLR_DATA_RAM_LATENCY_CYCLES_3 | L2CTLR_TAG_RAM_LATENCY_CYCLES_3 | |
| 68 | L2CTLR_ECC_PARITY); |
| 69 | write_l2ctlr(val); |
| 70 | } |
| 71 | |
| 72 | /* Configures L2 Auxiliary Control Register for Cortex A15. */ |
| 73 | static void configure_l2actlr(void) |
| 74 | { |
| 75 | uint32_t val; |
| 76 | |
| 77 | val = read_l2actlr(); |
| 78 | val |= (L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL | |
| 79 | L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT | |
| 80 | L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE); |
| 81 | write_l2actlr(val); |
| 82 | } |
| 83 | |
Gabe Black | 4a12cfe | 2014-03-24 21:24:24 -0700 | [diff] [blame] | 84 | static void setup_pinmux(void) |
| 85 | { |
| 86 | // Write protect. |
| 87 | gpio_input_pullup(GPIO(R1)); |
| 88 | // Recovery mode. |
| 89 | gpio_input_pullup(GPIO(Q7)); |
| 90 | // Lid switch. |
| 91 | gpio_input_pullup(GPIO(R4)); |
| 92 | // Power switch. |
| 93 | gpio_input_pullup(GPIO(Q0)); |
| 94 | // Developer mode. |
| 95 | gpio_input_pullup(GPIO(Q6)); |
| 96 | // EC in RW. |
| 97 | gpio_input_pullup(GPIO(U4)); |
| 98 | |
Tom Warren | c05a905 | 2014-04-14 10:01:21 -0700 | [diff] [blame] | 99 | // route PU4/5 to GMI to remove conflict w/PWM1/2. |
| 100 | pinmux_set_config(PINMUX_GPIO_PU4_INDEX, PINMUX_GPIO_PU4_FUNC_NOR); //s/b GMI |
| 101 | pinmux_set_config(PINMUX_GPIO_PU5_INDEX, PINMUX_GPIO_PU5_FUNC_NOR); //s/b GMI |
| 102 | |
Gabe Black | 4a12cfe | 2014-03-24 21:24:24 -0700 | [diff] [blame] | 103 | // SOC and TPM reset GPIO, active low. |
| 104 | gpio_output(GPIO(I5), 1); |
| 105 | |
| 106 | // SPI1 MOSI |
| 107 | pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 | |
| 108 | PINMUX_PULL_NONE | |
| 109 | PINMUX_INPUT_ENABLE); |
| 110 | // SPI1 MISO |
| 111 | pinmux_set_config(PINMUX_ULPI_DIR_INDEX, PINMUX_ULPI_DIR_FUNC_SPI1 | |
| 112 | PINMUX_PULL_NONE | |
| 113 | PINMUX_INPUT_ENABLE); |
| 114 | // SPI1 SCLK |
| 115 | pinmux_set_config(PINMUX_ULPI_NXT_INDEX, PINMUX_ULPI_NXT_FUNC_SPI1 | |
| 116 | PINMUX_PULL_NONE | |
| 117 | PINMUX_INPUT_ENABLE); |
| 118 | // SPI1 CS0 |
| 119 | pinmux_set_config(PINMUX_ULPI_STP_INDEX, PINMUX_ULPI_STP_FUNC_SPI1 | |
| 120 | PINMUX_PULL_NONE | |
| 121 | PINMUX_INPUT_ENABLE); |
| 122 | |
| 123 | // I2C3 (cam) clock. |
| 124 | pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX, |
| 125 | PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE); |
| 126 | // I2C3 (cam) data. |
| 127 | pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX, |
| 128 | PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE); |
| 129 | |
| 130 | // switch unused pin to GPIO |
| 131 | gpio_set_mode(GPIO(X3), GPIO_MODE_GPIO); |
| 132 | gpio_set_mode(GPIO(X4), GPIO_MODE_GPIO); |
| 133 | gpio_set_mode(GPIO(X5), GPIO_MODE_GPIO); |
| 134 | gpio_set_mode(GPIO(X6), GPIO_MODE_GPIO); |
| 135 | gpio_set_mode(GPIO(X7), GPIO_MODE_GPIO); |
| 136 | gpio_set_mode(GPIO(W3), GPIO_MODE_GPIO); |
| 137 | } |
| 138 | |
| 139 | static void configure_ec_spi_bus(void) |
| 140 | { |
Gabe Black | 92dfa9c | 2014-04-07 01:19:27 -0700 | [diff] [blame] | 141 | clock_configure_source(sbc1, CLK_M, 3000); |
Gabe Black | 4a12cfe | 2014-03-24 21:24:24 -0700 | [diff] [blame] | 142 | } |
| 143 | |
| 144 | static void configure_tpm_i2c_bus(void) |
| 145 | { |
Gabe Black | b19136f | 2014-03-26 21:58:06 -0700 | [diff] [blame] | 146 | clock_configure_i2c_scl_freq(i2c3, PLLP, 400); |
Gabe Black | 4a12cfe | 2014-03-24 21:24:24 -0700 | [diff] [blame] | 147 | |
| 148 | i2c_init(2); |
| 149 | } |
| 150 | |
Julius Werner | fd9defc | 2014-01-21 20:11:22 -0800 | [diff] [blame] | 151 | static void __attribute__((noinline)) romstage(void) |
Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 152 | { |
| 153 | #if CONFIG_COLLECT_TIMESTAMPS |
| 154 | uint64_t romstage_start_time = timestamp_get(); |
| 155 | #endif |
| 156 | |
Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 157 | configure_l2ctlr(); |
| 158 | configure_l2actlr(); |
| 159 | |
| 160 | console_init(); |
| 161 | exception_init(); |
| 162 | |
Tom Warren | 64982c50 | 2014-01-23 13:37:50 -0700 | [diff] [blame] | 163 | sdram_init(get_sdram_config()); |
| 164 | |
Gabe Black | 5cbbc70 | 2014-02-08 05:17:38 -0800 | [diff] [blame] | 165 | /* used for MMU and CBMEM setup, in MB */ |
Tom Warren | 64982c50 | 2014-01-23 13:37:50 -0700 | [diff] [blame] | 166 | u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20); |
Gabe Black | 5cbbc70 | 2014-02-08 05:17:38 -0800 | [diff] [blame] | 167 | u32 dram_end = sdram_max_addressable_mb(); /* plus one... */ |
| 168 | u32 dram_size = dram_end - dram_start; |
Tom Warren | 64982c50 | 2014-01-23 13:37:50 -0700 | [diff] [blame] | 169 | |
Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 170 | mmu_init(); |
Gabe Black | b9a4b71 | 2014-03-01 03:27:00 -0800 | [diff] [blame] | 171 | /* Device memory below DRAM is uncached. */ |
Tom Warren | 64982c50 | 2014-01-23 13:37:50 -0700 | [diff] [blame] | 172 | mmu_config_range(0, dram_start, DCACHE_OFF); |
Gabe Black | b9a4b71 | 2014-03-01 03:27:00 -0800 | [diff] [blame] | 173 | /* SRAM is cached. Round the size up to 2MB, the LPAE page size. */ |
| 174 | mmu_config_range(0x40000000 >> 20, 2, DCACHE_WRITEBACK); |
| 175 | /* DRAM is cached. */ |
Gabe Black | 5cbbc70 | 2014-02-08 05:17:38 -0800 | [diff] [blame] | 176 | mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK); |
Gabe Black | b9a4b71 | 2014-03-01 03:27:00 -0800 | [diff] [blame] | 177 | /* A window for DMA is uncached. */ |
Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 178 | mmu_config_range(CONFIG_DRAM_DMA_START >> 20, |
| 179 | CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF); |
Gabe Black | b9a4b71 | 2014-03-01 03:27:00 -0800 | [diff] [blame] | 180 | /* The space above DRAM is uncached. */ |
Gabe Black | 83ed805 | 2014-02-15 00:05:03 -0800 | [diff] [blame] | 181 | if (dram_end < 4096) |
| 182 | mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF); |
Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 183 | mmu_disable_range(0, 1); |
Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 184 | dcache_mmu_enable(); |
| 185 | |
Gabe Black | c852206 | 2014-05-06 15:44:14 -0700 | [diff] [blame^] | 186 | /* |
| 187 | * A watchdog reset only resets part of the system so it ends up in |
| 188 | * a funny state. If that happens, we need to reset the whole machine. |
| 189 | */ |
| 190 | if (power_reset_status() == POWER_RESET_WATCHDOG) { |
| 191 | printk(BIOS_INFO, "Watchdog reset detected, rebooting.\n"); |
| 192 | cpu_reset(); |
| 193 | } |
| 194 | |
Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 195 | /* For quality of the user experience, it's important to get |
| 196 | * the video going ASAP. Because there are long delays in some |
| 197 | * of the powerup steps, we do some very early setup here in |
| 198 | * romstage. The only thing setup_display does is manage |
| 199 | * 4 GPIOs, under control of the config struct members. |
| 200 | * In general, it is safe to enable panel power, and disable |
| 201 | * anything related to the backlight. If we get something wrong, |
| 202 | * we can easily fix it in ramstage by further GPIO manipulation, |
| 203 | * so we feel it is ok to do some setting at this point. |
| 204 | */ |
| 205 | |
| 206 | const struct device *soc = dev_find_slot(DEVICE_PATH_CPU_CLUSTER, 0); |
| 207 | printk(BIOS_SPEW, "s%s: soc is %p\n", __func__, soc); |
| 208 | if (soc && soc->chip_info) { |
| 209 | const struct soc_nvidia_tegra124_config *config = |
| 210 | soc->chip_info; |
| 211 | setup_display((struct soc_nvidia_tegra124_config *)config); |
| 212 | } |
| 213 | |
| 214 | cbmem_initialize_empty(); |
| 215 | |
Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 216 | timestamp_init(0); |
| 217 | timestamp_add(TS_START_ROMSTAGE, romstage_start_time); |
Gabe Black | 4a12cfe | 2014-03-24 21:24:24 -0700 | [diff] [blame] | 218 | |
| 219 | // Enable additional peripherals we need for ROM stage. |
| 220 | clock_enable_clear_reset(0, CLK_H_SBC1, CLK_U_I2C3, 0, 0, 0); |
| 221 | |
| 222 | setup_pinmux(); |
| 223 | |
| 224 | configure_ec_spi_bus(); |
| 225 | configure_tpm_i2c_bus(); |
| 226 | |
Gabe Black | a0b02e7 | 2014-04-21 19:51:15 -0700 | [diff] [blame] | 227 | #if CONFIG_CONSOLE_CBMEM |
| 228 | cbmemc_reinit(); |
| 229 | #endif |
| 230 | |
Aaron Durbin | cad7c4e | 2014-03-20 15:08:54 -0500 | [diff] [blame] | 231 | vboot_verify_firmware(romstage_handoff_find_or_add()); |
| 232 | |
| 233 | timestamp_add(TS_START_COPYRAM, timestamp_get()); |
Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 234 | void *entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, |
| 235 | "fallback/coreboot_ram"); |
Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 236 | timestamp_add(TS_END_COPYRAM, timestamp_get()); |
Aaron Durbin | cad7c4e | 2014-03-20 15:08:54 -0500 | [diff] [blame] | 237 | |
Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 238 | stage_exit(entry); |
| 239 | } |
Julius Werner | fd9defc | 2014-01-21 20:11:22 -0800 | [diff] [blame] | 240 | |
| 241 | /* Stub to force arm_init_caches to the top, before any stack/memory accesses */ |
| 242 | void main(void) |
| 243 | { |
Gabe Black | f220df6 | 2014-02-08 05:01:06 -0800 | [diff] [blame] | 244 | asm volatile ("bl arm_init_caches" |
| 245 | ::: "r0","r1","r2","r3","r4","r5","ip"); |
Julius Werner | fd9defc | 2014-01-21 20:11:22 -0800 | [diff] [blame] | 246 | romstage(); |
| 247 | } |