Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2014 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <arch/cache.h> |
| 21 | #include <arch/cpu.h> |
| 22 | #include <arch/exception.h> |
| 23 | #include <arch/stages.h> |
| 24 | #include <device/device.h> |
| 25 | #include <cbfs.h> |
| 26 | #include <cbmem.h> |
| 27 | #include <console/console.h> |
Tom Warren | 64982c50 | 2014-01-23 13:37:50 -0700 | [diff] [blame] | 28 | #include "sdram_configs.h" |
Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 29 | #include "soc/nvidia/tegra124/chip.h" |
Tom Warren | 64982c50 | 2014-01-23 13:37:50 -0700 | [diff] [blame] | 30 | #include "soc/nvidia/tegra124/sdram.h" |
Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 31 | #include <soc/display.h> |
| 32 | #include <timestamp.h> |
| 33 | |
Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 34 | enum { |
| 35 | L2CTLR_ECC_PARITY = 0x1 << 21, |
| 36 | L2CTLR_TAG_RAM_LATENCY_MASK = 0x7 << 6, |
| 37 | L2CTLR_TAG_RAM_LATENCY_CYCLES_3 = 2 << 6, |
| 38 | L2CTLR_DATA_RAM_LATENCY_MASK = 0x7 << 0, |
| 39 | L2CTLR_DATA_RAM_LATENCY_CYCLES_3 = 2 << 0 |
| 40 | }; |
| 41 | |
| 42 | enum { |
| 43 | L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE = 0x1 << 27, |
| 44 | L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT = 0x1 << 7, |
| 45 | L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL = 0x1 << 3 |
| 46 | }; |
| 47 | |
| 48 | /* Configures L2 Control Register to use 3 cycles for DATA/TAG RAM latency. */ |
| 49 | static void configure_l2ctlr(void) |
| 50 | { |
| 51 | uint32_t val; |
| 52 | |
| 53 | val = read_l2ctlr(); |
| 54 | val &= ~(L2CTLR_DATA_RAM_LATENCY_MASK | L2CTLR_TAG_RAM_LATENCY_MASK); |
| 55 | val |= (L2CTLR_DATA_RAM_LATENCY_CYCLES_3 | L2CTLR_TAG_RAM_LATENCY_CYCLES_3 | |
| 56 | L2CTLR_ECC_PARITY); |
| 57 | write_l2ctlr(val); |
| 58 | } |
| 59 | |
| 60 | /* Configures L2 Auxiliary Control Register for Cortex A15. */ |
| 61 | static void configure_l2actlr(void) |
| 62 | { |
| 63 | uint32_t val; |
| 64 | |
| 65 | val = read_l2actlr(); |
| 66 | val |= (L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL | |
| 67 | L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT | |
| 68 | L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE); |
| 69 | write_l2actlr(val); |
| 70 | } |
| 71 | |
Julius Werner | fd9defc | 2014-01-21 20:11:22 -0800 | [diff] [blame] | 72 | static void __attribute__((noinline)) romstage(void) |
Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 73 | { |
| 74 | #if CONFIG_COLLECT_TIMESTAMPS |
| 75 | uint64_t romstage_start_time = timestamp_get(); |
| 76 | #endif |
| 77 | |
Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 78 | configure_l2ctlr(); |
| 79 | configure_l2actlr(); |
| 80 | |
| 81 | console_init(); |
| 82 | exception_init(); |
| 83 | |
Tom Warren | 64982c50 | 2014-01-23 13:37:50 -0700 | [diff] [blame] | 84 | sdram_init(get_sdram_config()); |
| 85 | |
Gabe Black | 5cbbc70 | 2014-02-08 05:17:38 -0800 | [diff] [blame] | 86 | /* used for MMU and CBMEM setup, in MB */ |
Tom Warren | 64982c50 | 2014-01-23 13:37:50 -0700 | [diff] [blame] | 87 | u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20); |
Gabe Black | 5cbbc70 | 2014-02-08 05:17:38 -0800 | [diff] [blame] | 88 | u32 dram_end = sdram_max_addressable_mb(); /* plus one... */ |
| 89 | u32 dram_size = dram_end - dram_start; |
Tom Warren | 64982c50 | 2014-01-23 13:37:50 -0700 | [diff] [blame] | 90 | |
Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 91 | mmu_init(); |
Gabe Black | b9a4b71 | 2014-03-01 03:27:00 -0800 | [diff] [blame^] | 92 | /* Device memory below DRAM is uncached. */ |
Tom Warren | 64982c50 | 2014-01-23 13:37:50 -0700 | [diff] [blame] | 93 | mmu_config_range(0, dram_start, DCACHE_OFF); |
Gabe Black | b9a4b71 | 2014-03-01 03:27:00 -0800 | [diff] [blame^] | 94 | /* SRAM is cached. Round the size up to 2MB, the LPAE page size. */ |
| 95 | mmu_config_range(0x40000000 >> 20, 2, DCACHE_WRITEBACK); |
| 96 | /* DRAM is cached. */ |
Gabe Black | 5cbbc70 | 2014-02-08 05:17:38 -0800 | [diff] [blame] | 97 | mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK); |
Gabe Black | b9a4b71 | 2014-03-01 03:27:00 -0800 | [diff] [blame^] | 98 | /* A window for DMA is uncached. */ |
Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 99 | mmu_config_range(CONFIG_DRAM_DMA_START >> 20, |
| 100 | CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF); |
Gabe Black | b9a4b71 | 2014-03-01 03:27:00 -0800 | [diff] [blame^] | 101 | /* The space above DRAM is uncached. */ |
Gabe Black | 83ed805 | 2014-02-15 00:05:03 -0800 | [diff] [blame] | 102 | if (dram_end < 4096) |
| 103 | mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF); |
Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 104 | mmu_disable_range(0, 1); |
Gabe Black | 5c8d3d2 | 2014-01-17 22:11:35 -0800 | [diff] [blame] | 105 | dcache_mmu_enable(); |
| 106 | |
| 107 | /* For quality of the user experience, it's important to get |
| 108 | * the video going ASAP. Because there are long delays in some |
| 109 | * of the powerup steps, we do some very early setup here in |
| 110 | * romstage. The only thing setup_display does is manage |
| 111 | * 4 GPIOs, under control of the config struct members. |
| 112 | * In general, it is safe to enable panel power, and disable |
| 113 | * anything related to the backlight. If we get something wrong, |
| 114 | * we can easily fix it in ramstage by further GPIO manipulation, |
| 115 | * so we feel it is ok to do some setting at this point. |
| 116 | */ |
| 117 | |
| 118 | const struct device *soc = dev_find_slot(DEVICE_PATH_CPU_CLUSTER, 0); |
| 119 | printk(BIOS_SPEW, "s%s: soc is %p\n", __func__, soc); |
| 120 | if (soc && soc->chip_info) { |
| 121 | const struct soc_nvidia_tegra124_config *config = |
| 122 | soc->chip_info; |
| 123 | setup_display((struct soc_nvidia_tegra124_config *)config); |
| 124 | } |
| 125 | |
| 126 | cbmem_initialize_empty(); |
| 127 | |
| 128 | #if CONFIG_COLLECT_TIMESTAMPS |
| 129 | timestamp_init(0); |
| 130 | timestamp_add(TS_START_ROMSTAGE, romstage_start_time); |
| 131 | timestamp_add(TS_START_COPYRAM, timestamp_get()); |
| 132 | #endif |
| 133 | void *entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, |
| 134 | "fallback/coreboot_ram"); |
| 135 | #if CONFIG_COLLECT_TIMESTAMPS |
| 136 | timestamp_add(TS_END_COPYRAM, timestamp_get()); |
| 137 | #endif |
| 138 | stage_exit(entry); |
| 139 | } |
Julius Werner | fd9defc | 2014-01-21 20:11:22 -0800 | [diff] [blame] | 140 | |
| 141 | /* Stub to force arm_init_caches to the top, before any stack/memory accesses */ |
| 142 | void main(void) |
| 143 | { |
Gabe Black | f220df6 | 2014-02-08 05:01:06 -0800 | [diff] [blame] | 144 | asm volatile ("bl arm_init_caches" |
| 145 | ::: "r0","r1","r2","r3","r4","r5","ip"); |
Julius Werner | fd9defc | 2014-01-21 20:11:22 -0800 | [diff] [blame] | 146 | romstage(); |
| 147 | } |