Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
| 20 | * MA 02110-1301 USA |
| 21 | */ |
| 22 | |
| 23 | #include <console/console.h> |
| 24 | #include <device/device.h> |
| 25 | #include <arch/io.h> |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 26 | #include <delay.h> |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 27 | #include <device/pci_def.h> |
| 28 | #include <device/pci_ops.h> |
Jonathan A. Kollasch | 2596283 | 2012-07-10 10:14:17 -0500 | [diff] [blame] | 29 | #include <device/pci_ids.h> |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 30 | #include <arch/io.h> |
Denis 'GNUtoo' Carikli | 4062f17 | 2013-05-21 03:13:46 +0200 | [diff] [blame] | 31 | #include <arch/interrupt.h> |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 32 | #include <ec/lenovo/pmh7/pmh7.h> |
| 33 | #include <ec/acpi/ec.h> |
Sven Schnelle | ffcd143 | 2011-04-11 19:43:32 +0000 | [diff] [blame] | 34 | #include <ec/lenovo/h8/h8.h> |
Sven Schnelle | 8099cbf | 2011-04-04 10:57:17 +0000 | [diff] [blame] | 35 | #include <northbridge/intel/i945/i945.h> |
Sven Schnelle | d40d4f77 | 2011-06-12 15:08:58 +0200 | [diff] [blame] | 36 | #include <pc80/mc146818rtc.h> |
Sven Schnelle | 50270b8 | 2011-04-27 19:48:05 +0000 | [diff] [blame] | 37 | #include "dock.h" |
Sven Schnelle | 6eb8bef | 2011-10-23 16:57:50 +0200 | [diff] [blame] | 38 | #include <arch/x86/include/arch/acpigen.h> |
Denis 'GNUtoo' Carikli | 4062f17 | 2013-05-21 03:13:46 +0200 | [diff] [blame] | 39 | #include <x86emu/x86emu.h> |
| 40 | #define PANEL INT15_5F35_CL_DISPLAY_DEFAULT |
Sven Schnelle | 6eb8bef | 2011-10-23 16:57:50 +0200 | [diff] [blame] | 41 | |
Denis 'GNUtoo' Carikli | ed7e29e | 2013-02-24 12:01:44 +0100 | [diff] [blame] | 42 | int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio, |
| 43 | unsigned int gfx); |
| 44 | |
Stefan Reinauer | 4cc8c70 | 2012-04-27 21:34:16 +0200 | [diff] [blame] | 45 | static acpi_cstate_t cst_entries[] = { |
| 46 | { 1, 1, 1000, { 0x7f, 1, 2, { 0 }, 1, 0 } }, |
| 47 | { 2, 1, 500, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV2, 0 } }, |
| 48 | { 2, 17, 250, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV3, 0 } }, |
Sven Schnelle | 6eb8bef | 2011-10-23 16:57:50 +0200 | [diff] [blame] | 49 | }; |
| 50 | |
Denis 'GNUtoo' Carikli | 4062f17 | 2013-05-21 03:13:46 +0200 | [diff] [blame] | 51 | #if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE |
| 52 | static int int15_handler(void) |
| 53 | { |
| 54 | /* The right way to do this is to move this handler code into |
| 55 | * the mainboard or northbridge code. |
| 56 | * TODO: completely move to mainboards / chipsets. |
| 57 | */ |
| 58 | printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", |
| 59 | __func__, X86_AX, X86_BX, X86_CX, X86_DX); |
| 60 | |
| 61 | switch (X86_AX) { |
| 62 | case 0x5f35: /* Boot Display */ |
| 63 | X86_AX = 0x005f; // Success |
| 64 | X86_CL = PANEL; |
| 65 | break; |
| 66 | case 0x5f40: /* Boot Panel Type */ |
| 67 | X86_AX = 0x005f; // Success |
| 68 | X86_CL = 3; |
| 69 | printk(BIOS_DEBUG, "DISPLAY=%x\n", X86_CL); |
| 70 | break; |
| 71 | default: |
| 72 | /* Interrupt was not handled */ |
| 73 | printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); |
| 74 | return 0; |
| 75 | } |
| 76 | |
| 77 | /* Interrupt handled */ |
| 78 | return 1; |
| 79 | } |
| 80 | #endif |
| 81 | |
Stefan Reinauer | 4cc8c70 | 2012-04-27 21:34:16 +0200 | [diff] [blame] | 82 | int get_cst_entries(acpi_cstate_t **entries) |
Sven Schnelle | 6eb8bef | 2011-10-23 16:57:50 +0200 | [diff] [blame] | 83 | { |
| 84 | *entries = cst_entries; |
| 85 | return ARRAY_SIZE(cst_entries); |
| 86 | } |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 87 | |
Peter Stuge | eac9916 | 2013-07-06 20:05:13 +0200 | [diff] [blame^] | 88 | static void mainboard_init(device_t dev) |
Sven Schnelle | b31eb3e | 2011-04-05 13:00:14 +0000 | [diff] [blame] | 89 | { |
Jonathan A. Kollasch | 2596283 | 2012-07-10 10:14:17 -0500 | [diff] [blame] | 90 | device_t dev0, idedev, sdhci_dev; |
Sven Schnelle | b31eb3e | 2011-04-05 13:00:14 +0000 | [diff] [blame] | 91 | |
Sven Schnelle | 8d0b86c | 2011-07-11 18:36:16 +0200 | [diff] [blame] | 92 | ec_clr_bit(0x03, 2); |
| 93 | |
| 94 | if (inb(0x164c) & 0x08) { |
| 95 | ec_set_bit(0x03, 2); |
| 96 | ec_write(0x0c, 0x88); |
| 97 | } |
Denis 'GNUtoo' Carikli | 4062f17 | 2013-05-21 03:13:46 +0200 | [diff] [blame] | 98 | |
| 99 | #if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE |
| 100 | /* Install custom int15 handler for VGA OPROM */ |
| 101 | mainboard_interrupt_handlers(0x15, &int15_handler); |
| 102 | #endif |
| 103 | |
Sven Schnelle | 8099cbf | 2011-04-04 10:57:17 +0000 | [diff] [blame] | 104 | /* If we're resuming from suspend, blink suspend LED */ |
| 105 | dev0 = dev_find_slot(0, PCI_DEVFN(0,0)); |
Sven Schnelle | d8c68a9 | 2011-06-15 09:26:34 +0200 | [diff] [blame] | 106 | if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC) |
Sven Schnelle | 8099cbf | 2011-04-04 10:57:17 +0000 | [diff] [blame] | 107 | ec_write(0x0c, 0xc7); |
Sven Schnelle | 50270b8 | 2011-04-27 19:48:05 +0000 | [diff] [blame] | 108 | |
| 109 | idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1)); |
| 110 | if (idedev && idedev->chip_info && dock_ultrabay_device_present()) { |
| 111 | struct southbridge_intel_i82801gx_config *config = idedev->chip_info; |
| 112 | config->ide_enable_primary = 1; |
| 113 | /* enable Ultrabay power */ |
| 114 | outb(inb(0x1628) | 0x01, 0x1628); |
| 115 | ec_write(0x0c, 0x84); |
| 116 | } else { |
| 117 | /* disable Ultrabay power */ |
| 118 | outb(inb(0x1628) & ~0x01, 0x1628); |
| 119 | ec_write(0x0c, 0x04); |
| 120 | } |
Sven Schnelle | d40d4f77 | 2011-06-12 15:08:58 +0200 | [diff] [blame] | 121 | |
Jonathan A. Kollasch | 2596283 | 2012-07-10 10:14:17 -0500 | [diff] [blame] | 122 | /* Set SDHCI write protect polarity "SDWPPol" */ |
| 123 | sdhci_dev = dev_find_device(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C822, 0); |
| 124 | if (sdhci_dev) { |
| 125 | if (pci_read_config8(sdhci_dev, 0xfa) != 0x20) { |
| 126 | /* unlock */ |
| 127 | pci_write_config8(sdhci_dev, 0xf9, 0xfc); |
| 128 | /* set SDWPPol, keep CLKRUNDis, SDPWRPol clear */ |
| 129 | pci_write_config8(sdhci_dev, 0xfa, 0x20); |
| 130 | /* restore lock */ |
| 131 | pci_write_config8(sdhci_dev, 0xf9, 0x00); |
| 132 | } |
| 133 | } |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 134 | } |
| 135 | |
Peter Stuge | eac9916 | 2013-07-06 20:05:13 +0200 | [diff] [blame^] | 136 | static void mainboard_enable(device_t dev) |
| 137 | { |
| 138 | dev->ops->init = mainboard_init; |
| 139 | } |
| 140 | |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 141 | struct chip_operations mainboard_ops = { |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 142 | .enable_dev = mainboard_enable, |
| 143 | }; |
| 144 | |