Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
| 20 | * MA 02110-1301 USA |
| 21 | */ |
| 22 | |
| 23 | #include <console/console.h> |
| 24 | #include <device/device.h> |
| 25 | #include <arch/io.h> |
| 26 | #include <boot/tables.h> |
| 27 | #include <delay.h> |
| 28 | #include <arch/coreboot_tables.h> |
| 29 | #include "chip.h" |
| 30 | #include <device/pci_def.h> |
| 31 | #include <device/pci_ops.h> |
| 32 | #include <arch/io.h> |
| 33 | #include <ec/lenovo/pmh7/pmh7.h> |
| 34 | #include <ec/acpi/ec.h> |
Sven Schnelle | ffcd143 | 2011-04-11 19:43:32 +0000 | [diff] [blame] | 35 | #include <ec/lenovo/h8/h8.h> |
Sven Schnelle | 8099cbf | 2011-04-04 10:57:17 +0000 | [diff] [blame] | 36 | #include <northbridge/intel/i945/i945.h> |
Sven Schnelle | d40d4f77 | 2011-06-12 15:08:58 +0200 | [diff] [blame] | 37 | #include <pc80/mc146818rtc.h> |
Sven Schnelle | 50270b8 | 2011-04-27 19:48:05 +0000 | [diff] [blame] | 38 | #include "dock.h" |
Sven Schnelle | 6eb8bef | 2011-10-23 16:57:50 +0200 | [diff] [blame^] | 39 | #include <arch/x86/include/arch/acpigen.h> |
| 40 | |
| 41 | static struct cst_entry cst_entries[] = { |
| 42 | { 0x7f, 1, 2, 0, 1, 1, 1, 1000 }, |
| 43 | { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV2, 2, 1, 500 }, |
| 44 | { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV3, 2, 17, 250 }, |
| 45 | }; |
| 46 | |
| 47 | int get_cst_entries(struct cst_entry **entries) |
| 48 | { |
| 49 | *entries = cst_entries; |
| 50 | return ARRAY_SIZE(cst_entries); |
| 51 | } |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 52 | |
Sven Schnelle | b31eb3e | 2011-04-05 13:00:14 +0000 | [diff] [blame] | 53 | static void mainboard_enable(device_t dev) |
| 54 | { |
Sven Schnelle | 50270b8 | 2011-04-27 19:48:05 +0000 | [diff] [blame] | 55 | device_t dev0, idedev; |
Sven Schnelle | d40d4f77 | 2011-06-12 15:08:58 +0200 | [diff] [blame] | 56 | u8 defaults_loaded = 0; |
Sven Schnelle | b31eb3e | 2011-04-05 13:00:14 +0000 | [diff] [blame] | 57 | |
Sven Schnelle | 8d0b86c | 2011-07-11 18:36:16 +0200 | [diff] [blame] | 58 | ec_clr_bit(0x03, 2); |
| 59 | |
| 60 | if (inb(0x164c) & 0x08) { |
| 61 | ec_set_bit(0x03, 2); |
| 62 | ec_write(0x0c, 0x88); |
| 63 | } |
Sven Schnelle | 8099cbf | 2011-04-04 10:57:17 +0000 | [diff] [blame] | 64 | /* If we're resuming from suspend, blink suspend LED */ |
| 65 | dev0 = dev_find_slot(0, PCI_DEVFN(0,0)); |
Sven Schnelle | d8c68a9 | 2011-06-15 09:26:34 +0200 | [diff] [blame] | 66 | if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC) |
Sven Schnelle | 8099cbf | 2011-04-04 10:57:17 +0000 | [diff] [blame] | 67 | ec_write(0x0c, 0xc7); |
Sven Schnelle | 50270b8 | 2011-04-27 19:48:05 +0000 | [diff] [blame] | 68 | |
| 69 | idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1)); |
| 70 | if (idedev && idedev->chip_info && dock_ultrabay_device_present()) { |
| 71 | struct southbridge_intel_i82801gx_config *config = idedev->chip_info; |
| 72 | config->ide_enable_primary = 1; |
| 73 | /* enable Ultrabay power */ |
| 74 | outb(inb(0x1628) | 0x01, 0x1628); |
| 75 | ec_write(0x0c, 0x84); |
| 76 | } else { |
| 77 | /* disable Ultrabay power */ |
| 78 | outb(inb(0x1628) & ~0x01, 0x1628); |
| 79 | ec_write(0x0c, 0x04); |
| 80 | } |
Sven Schnelle | d40d4f77 | 2011-06-12 15:08:58 +0200 | [diff] [blame] | 81 | |
| 82 | if (get_option(&defaults_loaded, "cmos_defaults_loaded") < 0) { |
| 83 | printk(BIOS_INFO, "failed to get cmos_defaults_loaded"); |
| 84 | defaults_loaded = 0; |
| 85 | } |
| 86 | |
| 87 | if (!defaults_loaded) { |
| 88 | printk(BIOS_INFO, "Restoring CMOS defaults\n"); |
| 89 | set_option("tft_brightness", &(u8[]){ 0xff }); |
| 90 | set_option("volume", &(u8[]){ 0x03 }); |
| 91 | set_option("cmos_defaults_loaded", &(u8[]){ 0x01 }); |
| 92 | } |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 93 | } |
| 94 | |
| 95 | struct chip_operations mainboard_ops = { |
| 96 | CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER) |
| 97 | .enable_dev = mainboard_enable, |
| 98 | }; |
| 99 | |