Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include <acpi/acpi.h> |
Felix Held | 21c46c0 | 2021-03-05 00:13:16 +0100 | [diff] [blame] | 4 | #include <amdblocks/apob_cache.h> |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 5 | #include <assert.h> |
| 6 | #include <boot_device.h> |
Raul E Rangel | 73e0f18 | 2021-07-12 09:21:51 -0600 | [diff] [blame] | 7 | #include <bootstate.h> |
Raul E Rangel | fca5833 | 2021-06-25 11:15:41 -0600 | [diff] [blame] | 8 | #include <commonlib/helpers.h> |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 9 | #include <commonlib/region.h> |
| 10 | #include <console/console.h> |
| 11 | #include <fmap.h> |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 12 | #include <spi_flash.h> |
| 13 | #include <stdint.h> |
| 14 | #include <string.h> |
Raul E Rangel | fca5833 | 2021-06-25 11:15:41 -0600 | [diff] [blame] | 15 | #include <thread.h> |
Raul E Rangel | d742b5e | 2021-06-10 14:39:01 -0600 | [diff] [blame] | 16 | #include <timestamp.h> |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 17 | |
| 18 | #define DEFAULT_MRC_CACHE "RW_MRC_CACHE" |
| 19 | /* PSP requires this value to be 64KiB */ |
| 20 | #define DEFAULT_MRC_CACHE_SIZE 0x10000 |
| 21 | |
| 22 | #if !CONFIG_PSP_APOB_DRAM_ADDRESS |
| 23 | #error Incorrect APOB configuration setting(s) |
| 24 | #endif |
| 25 | |
| 26 | #define APOB_SIGNATURE 0x424F5041 /* 'APOB' */ |
| 27 | |
| 28 | /* APOB_BASE_HEADER from AGESA */ |
| 29 | struct apob_base_header { |
| 30 | uint32_t signature; /* APOB signature */ |
| 31 | uint32_t version; /* Version */ |
| 32 | uint32_t size; /* APOB Size */ |
| 33 | uint32_t offset_of_first_entry; /* APOB Header Size */ |
| 34 | }; |
| 35 | |
| 36 | static bool apob_header_valid(const struct apob_base_header *apob_header_ptr, const char *where) |
| 37 | { |
| 38 | if (apob_header_ptr->signature != APOB_SIGNATURE) { |
| 39 | printk(BIOS_WARNING, "Invalid %s APOB signature %x\n", |
| 40 | where, apob_header_ptr->signature); |
| 41 | return false; |
| 42 | } |
| 43 | |
| 44 | if (apob_header_ptr->size == 0 || apob_header_ptr->size > DEFAULT_MRC_CACHE_SIZE) { |
| 45 | printk(BIOS_WARNING, "%s APOB data is too large %x > %x\n", |
| 46 | where, apob_header_ptr->size, DEFAULT_MRC_CACHE_SIZE); |
| 47 | return false; |
| 48 | } |
| 49 | |
| 50 | return true; |
| 51 | } |
| 52 | |
| 53 | static void *get_apob_dram_address(void) |
| 54 | { |
| 55 | /* |
| 56 | * TODO: Find the APOB destination by parsing the PSP's tables |
| 57 | * (once vboot is implemented). |
| 58 | */ |
| 59 | void *apob_src_ram = (void *)(uintptr_t)CONFIG_PSP_APOB_DRAM_ADDRESS; |
| 60 | |
| 61 | if (apob_header_valid(apob_src_ram, "RAM") == false) |
| 62 | return NULL; |
| 63 | |
| 64 | return apob_src_ram; |
| 65 | } |
| 66 | |
Raul E Rangel | ce63dc4 | 2021-07-16 10:37:58 -0600 | [diff] [blame] | 67 | static int get_nv_rdev(struct region_device *r) |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 68 | { |
Raul E Rangel | ce63dc4 | 2021-07-16 10:37:58 -0600 | [diff] [blame] | 69 | if (fmap_locate_area_as_rdev(DEFAULT_MRC_CACHE, r) < 0) { |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame^] | 70 | printk(BIOS_ERR, "No APOB NV region is found in flash\n"); |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 71 | return -1; |
| 72 | } |
| 73 | |
| 74 | return 0; |
| 75 | } |
| 76 | |
Raul E Rangel | fca5833 | 2021-06-25 11:15:41 -0600 | [diff] [blame] | 77 | static struct apob_thread_context { |
| 78 | uint8_t buffer[DEFAULT_MRC_CACHE_SIZE] __attribute__((aligned(64))); |
| 79 | struct thread_handle handle; |
| 80 | struct region_device apob_rdev; |
| 81 | } global_apob_thread; |
| 82 | |
| 83 | static enum cb_err apob_thread_entry(void *arg) |
| 84 | { |
| 85 | ssize_t size; |
| 86 | struct apob_thread_context *thread = arg; |
| 87 | |
| 88 | printk(BIOS_DEBUG, "APOB thread running\n"); |
| 89 | size = rdev_readat(&thread->apob_rdev, thread->buffer, 0, |
| 90 | region_device_sz(&thread->apob_rdev)); |
| 91 | |
| 92 | printk(BIOS_DEBUG, "APOB thread done\n"); |
| 93 | |
| 94 | if (size == region_device_sz(&thread->apob_rdev)) |
| 95 | return CB_SUCCESS; |
| 96 | |
| 97 | return CB_ERR; |
| 98 | } |
| 99 | |
| 100 | void start_apob_cache_read(void) |
| 101 | { |
| 102 | struct apob_thread_context *thread = &global_apob_thread; |
| 103 | |
| 104 | if (!CONFIG(COOP_MULTITASKING)) |
| 105 | return; |
| 106 | |
| 107 | /* We don't perform any comparison on S3 resume */ |
| 108 | if (acpi_is_wakeup_s3()) |
| 109 | return; |
| 110 | |
| 111 | if (get_nv_rdev(&thread->apob_rdev) != 0) |
| 112 | return; |
| 113 | |
| 114 | assert(ARRAY_SIZE(thread->buffer) == region_device_sz(&thread->apob_rdev)); |
| 115 | |
| 116 | printk(BIOS_DEBUG, "Starting APOB preload\n"); |
| 117 | if (thread_run(&thread->handle, apob_thread_entry, thread)) |
| 118 | printk(BIOS_ERR, "Failed to start APOB preload thread\n"); |
| 119 | } |
| 120 | |
Raul E Rangel | ce63dc4 | 2021-07-16 10:37:58 -0600 | [diff] [blame] | 121 | static void *get_apob_from_nv_rdev(struct region_device *read_rdev) |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 122 | { |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 123 | struct apob_base_header apob_header; |
| 124 | |
Raul E Rangel | ce63dc4 | 2021-07-16 10:37:58 -0600 | [diff] [blame] | 125 | if (rdev_readat(read_rdev, &apob_header, 0, sizeof(apob_header)) < 0) { |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 126 | printk(BIOS_ERR, "Couldn't read APOB header!\n"); |
| 127 | return NULL; |
| 128 | } |
| 129 | |
| 130 | if (apob_header_valid(&apob_header, "ROM") == false) { |
| 131 | printk(BIOS_ERR, "No APOB NV data!\n"); |
| 132 | return NULL; |
| 133 | } |
| 134 | |
| 135 | assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); |
Raul E Rangel | ce63dc4 | 2021-07-16 10:37:58 -0600 | [diff] [blame] | 136 | return rdev_mmap_full(read_rdev); |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 137 | } |
| 138 | |
| 139 | /* Save APOB buffer to flash */ |
Raul E Rangel | 73e0f18 | 2021-07-12 09:21:51 -0600 | [diff] [blame] | 140 | static void soc_update_apob_cache(void *unused) |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 141 | { |
| 142 | struct apob_base_header *apob_rom; |
Raul E Rangel | ce63dc4 | 2021-07-16 10:37:58 -0600 | [diff] [blame] | 143 | struct region_device read_rdev, write_rdev; |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 144 | bool update_needed = false; |
| 145 | const struct apob_base_header *apob_src_ram; |
| 146 | |
| 147 | /* Nothing to update in case of S3 resume. */ |
| 148 | if (acpi_is_wakeup_s3()) |
| 149 | return; |
| 150 | |
| 151 | apob_src_ram = get_apob_dram_address(); |
| 152 | if (apob_src_ram == NULL) |
| 153 | return; |
| 154 | |
Raul E Rangel | ce63dc4 | 2021-07-16 10:37:58 -0600 | [diff] [blame] | 155 | if (get_nv_rdev(&read_rdev) != 0) |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 156 | return; |
| 157 | |
Raul E Rangel | d742b5e | 2021-06-10 14:39:01 -0600 | [diff] [blame] | 158 | timestamp_add_now(TS_AMD_APOB_READ_START); |
| 159 | |
Raul E Rangel | fca5833 | 2021-06-25 11:15:41 -0600 | [diff] [blame] | 160 | if (CONFIG(COOP_MULTITASKING) && thread_join(&global_apob_thread.handle) == CB_SUCCESS) |
| 161 | apob_rom = (struct apob_base_header *)global_apob_thread.buffer; |
| 162 | else |
| 163 | apob_rom = get_apob_from_nv_rdev(&read_rdev); |
| 164 | |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 165 | if (apob_rom == NULL) { |
| 166 | update_needed = true; |
| 167 | } else if (memcmp(apob_src_ram, apob_rom, apob_src_ram->size)) { |
| 168 | printk(BIOS_INFO, "APOB RAM copy differs from flash\n"); |
| 169 | update_needed = true; |
| 170 | } else |
| 171 | printk(BIOS_DEBUG, "APOB valid copy is already in flash\n"); |
| 172 | |
Raul E Rangel | d742b5e | 2021-06-10 14:39:01 -0600 | [diff] [blame] | 173 | if (!update_needed) { |
| 174 | timestamp_add_now(TS_AMD_APOB_DONE); |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 175 | return; |
Raul E Rangel | d742b5e | 2021-06-10 14:39:01 -0600 | [diff] [blame] | 176 | } |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 177 | |
Raul E Rangel | 7224043 | 2021-07-12 09:50:49 -0600 | [diff] [blame] | 178 | printk(BIOS_SPEW, "Copy APOB from RAM %p/%#x to flash %#zx/%#zx\n", |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 179 | apob_src_ram, apob_src_ram->size, |
Raul E Rangel | ce63dc4 | 2021-07-16 10:37:58 -0600 | [diff] [blame] | 180 | region_device_offset(&read_rdev), region_device_sz(&read_rdev)); |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 181 | |
Raul E Rangel | ce63dc4 | 2021-07-16 10:37:58 -0600 | [diff] [blame] | 182 | if (fmap_locate_area_as_rdev_rw(DEFAULT_MRC_CACHE, &write_rdev) < 0) { |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame^] | 183 | printk(BIOS_ERR, "No RW APOB NV region is found in flash\n"); |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 184 | return; |
| 185 | } |
| 186 | |
Raul E Rangel | d742b5e | 2021-06-10 14:39:01 -0600 | [diff] [blame] | 187 | timestamp_add_now(TS_AMD_APOB_ERASE_START); |
| 188 | |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 189 | /* write data to flash region */ |
| 190 | if (rdev_eraseat(&write_rdev, 0, DEFAULT_MRC_CACHE_SIZE) < 0) { |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame^] | 191 | printk(BIOS_ERR, "APOB flash region erase failed\n"); |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 192 | return; |
| 193 | } |
| 194 | |
Raul E Rangel | d742b5e | 2021-06-10 14:39:01 -0600 | [diff] [blame] | 195 | timestamp_add_now(TS_AMD_APOB_WRITE_START); |
| 196 | |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 197 | if (rdev_writeat(&write_rdev, apob_src_ram, 0, apob_src_ram->size) < 0) { |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame^] | 198 | printk(BIOS_ERR, "APOB flash region update failed\n"); |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 199 | return; |
| 200 | } |
| 201 | |
Raul E Rangel | d742b5e | 2021-06-10 14:39:01 -0600 | [diff] [blame] | 202 | timestamp_add_now(TS_AMD_APOB_DONE); |
| 203 | |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 204 | printk(BIOS_INFO, "Updated APOB in flash\n"); |
| 205 | } |
| 206 | |
| 207 | static void *get_apob_nv_address(void) |
| 208 | { |
Raul E Rangel | ce63dc4 | 2021-07-16 10:37:58 -0600 | [diff] [blame] | 209 | struct region_device rdev; |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 210 | |
Raul E Rangel | ce63dc4 | 2021-07-16 10:37:58 -0600 | [diff] [blame] | 211 | if (get_nv_rdev(&rdev) != 0) |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 212 | return NULL; |
| 213 | |
Raul E Rangel | ce63dc4 | 2021-07-16 10:37:58 -0600 | [diff] [blame] | 214 | return get_apob_from_nv_rdev(&rdev); |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 215 | } |
| 216 | |
Felix Held | 21c46c0 | 2021-03-05 00:13:16 +0100 | [diff] [blame] | 217 | void *soc_fill_apob_cache(void) |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 218 | { |
| 219 | /* If this is non-S3 boot, then use the APOB data placed by PSP in DRAM. */ |
| 220 | if (!acpi_is_wakeup_s3()) |
| 221 | return get_apob_dram_address(); |
| 222 | |
| 223 | /* |
| 224 | * In case of S3 resume, PSP does not copy APOB data to DRAM. Thus, coreboot needs to |
| 225 | * provide the APOB NV data from RW_MRC_CACHE on SPI flash so that FSP can use it |
| 226 | * without having to traverse the BIOS directory table. |
| 227 | */ |
| 228 | return get_apob_nv_address(); |
| 229 | } |
Raul E Rangel | fca5833 | 2021-06-25 11:15:41 -0600 | [diff] [blame] | 230 | |
| 231 | /* |
| 232 | * BS_POST_DEVICE was chosen because this gives start_apob_cache_read plenty of time to read |
| 233 | * the APOB from SPI. |
| 234 | */ |
Raul E Rangel | 73e0f18 | 2021-07-12 09:21:51 -0600 | [diff] [blame] | 235 | BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, soc_update_apob_cache, NULL); |