Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include <acpi/acpi.h> |
Felix Held | 21c46c0 | 2021-03-05 00:13:16 +0100 | [diff] [blame] | 4 | #include <amdblocks/apob_cache.h> |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 5 | #include <assert.h> |
| 6 | #include <boot_device.h> |
Raul E Rangel | 73e0f18 | 2021-07-12 09:21:51 -0600 | [diff] [blame^] | 7 | #include <bootstate.h> |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 8 | #include <commonlib/region.h> |
| 9 | #include <console/console.h> |
| 10 | #include <fmap.h> |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 11 | #include <spi_flash.h> |
| 12 | #include <stdint.h> |
| 13 | #include <string.h> |
Raul E Rangel | d742b5e | 2021-06-10 14:39:01 -0600 | [diff] [blame] | 14 | #include <timestamp.h> |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 15 | |
| 16 | #define DEFAULT_MRC_CACHE "RW_MRC_CACHE" |
| 17 | /* PSP requires this value to be 64KiB */ |
| 18 | #define DEFAULT_MRC_CACHE_SIZE 0x10000 |
| 19 | |
| 20 | #if !CONFIG_PSP_APOB_DRAM_ADDRESS |
| 21 | #error Incorrect APOB configuration setting(s) |
| 22 | #endif |
| 23 | |
| 24 | #define APOB_SIGNATURE 0x424F5041 /* 'APOB' */ |
| 25 | |
| 26 | /* APOB_BASE_HEADER from AGESA */ |
| 27 | struct apob_base_header { |
| 28 | uint32_t signature; /* APOB signature */ |
| 29 | uint32_t version; /* Version */ |
| 30 | uint32_t size; /* APOB Size */ |
| 31 | uint32_t offset_of_first_entry; /* APOB Header Size */ |
| 32 | }; |
| 33 | |
| 34 | static bool apob_header_valid(const struct apob_base_header *apob_header_ptr, const char *where) |
| 35 | { |
| 36 | if (apob_header_ptr->signature != APOB_SIGNATURE) { |
| 37 | printk(BIOS_WARNING, "Invalid %s APOB signature %x\n", |
| 38 | where, apob_header_ptr->signature); |
| 39 | return false; |
| 40 | } |
| 41 | |
| 42 | if (apob_header_ptr->size == 0 || apob_header_ptr->size > DEFAULT_MRC_CACHE_SIZE) { |
| 43 | printk(BIOS_WARNING, "%s APOB data is too large %x > %x\n", |
| 44 | where, apob_header_ptr->size, DEFAULT_MRC_CACHE_SIZE); |
| 45 | return false; |
| 46 | } |
| 47 | |
| 48 | return true; |
| 49 | } |
| 50 | |
| 51 | static void *get_apob_dram_address(void) |
| 52 | { |
| 53 | /* |
| 54 | * TODO: Find the APOB destination by parsing the PSP's tables |
| 55 | * (once vboot is implemented). |
| 56 | */ |
| 57 | void *apob_src_ram = (void *)(uintptr_t)CONFIG_PSP_APOB_DRAM_ADDRESS; |
| 58 | |
| 59 | if (apob_header_valid(apob_src_ram, "RAM") == false) |
| 60 | return NULL; |
| 61 | |
| 62 | return apob_src_ram; |
| 63 | } |
| 64 | |
| 65 | static int get_nv_region(struct region *r) |
| 66 | { |
| 67 | if (fmap_locate_area(DEFAULT_MRC_CACHE, r) < 0) { |
| 68 | printk(BIOS_ERR, "Error: No APOB NV region is found in flash\n"); |
| 69 | return -1; |
| 70 | } |
| 71 | |
| 72 | return 0; |
| 73 | } |
| 74 | |
| 75 | static void *get_apob_from_nv_region(struct region *region) |
| 76 | { |
| 77 | struct region_device read_rdev; |
| 78 | struct apob_base_header apob_header; |
| 79 | |
| 80 | if (boot_device_ro_subregion(region, &read_rdev) < 0) { |
| 81 | printk(BIOS_ERR, "Failed boot_device_ro_subregion\n"); |
| 82 | return NULL; |
| 83 | } |
| 84 | |
| 85 | if (rdev_readat(&read_rdev, &apob_header, 0, sizeof(apob_header)) < 0) { |
| 86 | printk(BIOS_ERR, "Couldn't read APOB header!\n"); |
| 87 | return NULL; |
| 88 | } |
| 89 | |
| 90 | if (apob_header_valid(&apob_header, "ROM") == false) { |
| 91 | printk(BIOS_ERR, "No APOB NV data!\n"); |
| 92 | return NULL; |
| 93 | } |
| 94 | |
| 95 | assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); |
| 96 | return rdev_mmap_full(&read_rdev); |
| 97 | } |
| 98 | |
| 99 | /* Save APOB buffer to flash */ |
Raul E Rangel | 73e0f18 | 2021-07-12 09:21:51 -0600 | [diff] [blame^] | 100 | static void soc_update_apob_cache(void *unused) |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 101 | { |
| 102 | struct apob_base_header *apob_rom; |
| 103 | struct region_device write_rdev; |
| 104 | struct region region; |
| 105 | bool update_needed = false; |
| 106 | const struct apob_base_header *apob_src_ram; |
| 107 | |
| 108 | /* Nothing to update in case of S3 resume. */ |
| 109 | if (acpi_is_wakeup_s3()) |
| 110 | return; |
| 111 | |
| 112 | apob_src_ram = get_apob_dram_address(); |
| 113 | if (apob_src_ram == NULL) |
| 114 | return; |
| 115 | |
| 116 | if (get_nv_region(®ion) != 0) |
| 117 | return; |
| 118 | |
Raul E Rangel | d742b5e | 2021-06-10 14:39:01 -0600 | [diff] [blame] | 119 | timestamp_add_now(TS_AMD_APOB_READ_START); |
| 120 | |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 121 | apob_rom = get_apob_from_nv_region(®ion); |
| 122 | if (apob_rom == NULL) { |
| 123 | update_needed = true; |
| 124 | } else if (memcmp(apob_src_ram, apob_rom, apob_src_ram->size)) { |
| 125 | printk(BIOS_INFO, "APOB RAM copy differs from flash\n"); |
| 126 | update_needed = true; |
| 127 | } else |
| 128 | printk(BIOS_DEBUG, "APOB valid copy is already in flash\n"); |
| 129 | |
Raul E Rangel | d742b5e | 2021-06-10 14:39:01 -0600 | [diff] [blame] | 130 | if (!update_needed) { |
| 131 | timestamp_add_now(TS_AMD_APOB_DONE); |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 132 | return; |
Raul E Rangel | d742b5e | 2021-06-10 14:39:01 -0600 | [diff] [blame] | 133 | } |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 134 | |
Raul E Rangel | 7224043 | 2021-07-12 09:50:49 -0600 | [diff] [blame] | 135 | printk(BIOS_SPEW, "Copy APOB from RAM %p/%#x to flash %#zx/%#zx\n", |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 136 | apob_src_ram, apob_src_ram->size, |
| 137 | region_offset(®ion), region_sz(®ion)); |
| 138 | |
| 139 | if (boot_device_rw_subregion(®ion, &write_rdev) < 0) { |
| 140 | printk(BIOS_ERR, "Failed boot_device_rw_subregion\n"); |
| 141 | return; |
| 142 | } |
| 143 | |
Raul E Rangel | d742b5e | 2021-06-10 14:39:01 -0600 | [diff] [blame] | 144 | timestamp_add_now(TS_AMD_APOB_ERASE_START); |
| 145 | |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 146 | /* write data to flash region */ |
| 147 | if (rdev_eraseat(&write_rdev, 0, DEFAULT_MRC_CACHE_SIZE) < 0) { |
| 148 | printk(BIOS_ERR, "Error: APOB flash region erase failed\n"); |
| 149 | return; |
| 150 | } |
| 151 | |
Raul E Rangel | d742b5e | 2021-06-10 14:39:01 -0600 | [diff] [blame] | 152 | timestamp_add_now(TS_AMD_APOB_WRITE_START); |
| 153 | |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 154 | if (rdev_writeat(&write_rdev, apob_src_ram, 0, apob_src_ram->size) < 0) { |
| 155 | printk(BIOS_ERR, "Error: APOB flash region update failed\n"); |
| 156 | return; |
| 157 | } |
| 158 | |
Raul E Rangel | d742b5e | 2021-06-10 14:39:01 -0600 | [diff] [blame] | 159 | timestamp_add_now(TS_AMD_APOB_DONE); |
| 160 | |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 161 | printk(BIOS_INFO, "Updated APOB in flash\n"); |
| 162 | } |
| 163 | |
| 164 | static void *get_apob_nv_address(void) |
| 165 | { |
| 166 | struct region region; |
| 167 | |
| 168 | if (get_nv_region(®ion) != 0) |
| 169 | return NULL; |
| 170 | |
| 171 | return get_apob_from_nv_region(®ion); |
| 172 | } |
| 173 | |
Felix Held | 21c46c0 | 2021-03-05 00:13:16 +0100 | [diff] [blame] | 174 | void *soc_fill_apob_cache(void) |
Furquan Shaikh | f9be2d1 | 2020-06-08 12:30:40 -0700 | [diff] [blame] | 175 | { |
| 176 | /* If this is non-S3 boot, then use the APOB data placed by PSP in DRAM. */ |
| 177 | if (!acpi_is_wakeup_s3()) |
| 178 | return get_apob_dram_address(); |
| 179 | |
| 180 | /* |
| 181 | * In case of S3 resume, PSP does not copy APOB data to DRAM. Thus, coreboot needs to |
| 182 | * provide the APOB NV data from RW_MRC_CACHE on SPI flash so that FSP can use it |
| 183 | * without having to traverse the BIOS directory table. |
| 184 | */ |
| 185 | return get_apob_nv_address(); |
| 186 | } |
Raul E Rangel | 73e0f18 | 2021-07-12 09:21:51 -0600 | [diff] [blame^] | 187 | BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, soc_update_apob_cache, NULL); |