Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 1 | config SOC_INTEL_ELKHARTLAKE |
| 2 | bool |
| 3 | help |
| 4 | Intel Elkhartlake support |
| 5 | |
| 6 | if SOC_INTEL_ELKHARTLAKE |
| 7 | |
| 8 | config CPU_SPECIFIC_OPTIONS |
| 9 | def_bool y |
| 10 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Angel Pons | 8e035e3 | 2021-06-22 12:58:20 +0200 | [diff] [blame] | 11 | select ARCH_X86 |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 12 | select BOOT_DEVICE_SUPPORTS_WRITES |
| 13 | select CACHE_MRC_SETTINGS |
| 14 | select CPU_INTEL_COMMON |
| 15 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Michael Niewöhner | fe6070f | 2020-10-04 15:16:04 +0200 | [diff] [blame] | 16 | select CPU_SUPPORTS_PM_TIMER_EMULATION |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 17 | select FSP_COMPRESS_FSP_S_LZ4 |
| 18 | select FSP_M_XIP |
Subrata Banik | 4ed9f9a | 2020-10-31 22:01:55 +0530 | [diff] [blame] | 19 | select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 20 | select GENERIC_GPIO_LIB |
| 21 | select HAVE_FSP_GOP |
| 22 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
| 23 | select HAVE_SMI_HANDLER |
| 24 | select IDT_IN_EVERY_STAGE |
Subrata Banik | e9d0653 | 2022-01-28 23:06:58 +0530 | [diff] [blame] | 25 | select INTEL_CAR_NEM |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 26 | select INTEL_GMA_ACPI |
| 27 | select INTEL_GMA_ADD_VBT if RUN_FSP_GOP |
Aamir Bohra | 30cca6c | 2021-02-04 20:57:51 +0530 | [diff] [blame] | 28 | select MP_SERVICES_PPI_V1 |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 29 | select MRC_SETTINGS_PROTECT |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 30 | select PARALLEL_MP_AP_WORK |
Tan, Lean Sheng | ece0fe3 | 2020-09-03 07:32:48 -0700 | [diff] [blame] | 31 | select PLATFORM_USES_FSP2_1 |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 32 | select PMC_GLOBAL_RESET_ENABLE_LOCK |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 33 | select SOC_INTEL_COMMON |
| 34 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
| 35 | select SOC_INTEL_COMMON_BLOCK |
| 36 | select SOC_INTEL_COMMON_BLOCK_ACPI |
Michael Niewöhner | 02275be | 2020-11-12 23:50:37 +0100 | [diff] [blame] | 37 | select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC |
Angel Pons | 98f672a | 2021-02-19 19:42:10 +0100 | [diff] [blame] | 38 | select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO |
Michael Niewöhner | 8a6c34e | 2021-01-01 21:26:42 +0100 | [diff] [blame] | 39 | select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT |
Tim Wawrzynczak | 46c5f8f | 2021-07-01 08:45:47 -0600 | [diff] [blame] | 40 | select SOC_INTEL_COMMON_BLOCK_ACPI_PEP |
Subrata Banik | 21974ab | 2020-10-31 21:40:43 +0530 | [diff] [blame] | 41 | select SOC_INTEL_COMMON_BLOCK_CAR |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 42 | select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
| 43 | select SOC_INTEL_COMMON_BLOCK_CPU |
| 44 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
Angel Pons | a4cd911 | 2021-02-19 19:23:38 +0100 | [diff] [blame] | 45 | select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 46 | select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT |
| 47 | select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 |
| 48 | select SOC_INTEL_COMMON_BLOCK_HDA |
Subrata Banik | e49a615 | 2022-01-28 23:03:55 +0530 | [diff] [blame^] | 49 | select HECI_DISABLE_USING_SMM if DISABLE_HECI1_AT_PRE_BOOT |
Lean Sheng Tan | 7502000 | 2021-06-30 01:47:48 -0700 | [diff] [blame] | 50 | select SOC_INTEL_COMMON_BLOCK_PMC_EPOC |
| 51 | select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 52 | select SOC_INTEL_COMMON_BLOCK_SA |
| 53 | select SOC_INTEL_COMMON_BLOCK_SCS |
| 54 | select SOC_INTEL_COMMON_BLOCK_SMM |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 55 | select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP |
Subrata Banik | 4ed9f9a | 2020-10-31 22:01:55 +0530 | [diff] [blame] | 56 | select SOC_INTEL_COMMON_FSP_RESET |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 57 | select SOC_INTEL_COMMON_PCH_BASE |
| 58 | select SOC_INTEL_COMMON_RESET |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 59 | select SSE2 |
| 60 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 61 | select TSC_MONOTONIC_TIMER |
| 62 | select UDELAY_TSC |
| 63 | select UDK_202005_BINDING |
| 64 | select DISPLAY_FSP_VERSION_INFO |
Lean Sheng Tan | 79fcadb | 2021-06-04 08:54:29 -0700 | [diff] [blame] | 65 | select HAVE_INTEL_FSP_REPO |
Tan, Lean Sheng | ece0fe3 | 2020-09-03 07:32:48 -0700 | [diff] [blame] | 66 | |
| 67 | config MAX_CPUS |
| 68 | int |
| 69 | default 4 |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 70 | |
| 71 | config DCACHE_RAM_BASE |
| 72 | default 0xfef00000 |
| 73 | |
| 74 | config DCACHE_RAM_SIZE |
Tan, Lean Sheng | ece0fe3 | 2020-09-03 07:32:48 -0700 | [diff] [blame] | 75 | default 0xc0000 |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 76 | help |
| 77 | The size of the cache-as-ram region required during bootblock |
| 78 | and/or romstage. |
| 79 | |
| 80 | config DCACHE_BSP_STACK_SIZE |
| 81 | hex |
Tan, Lean Sheng | ece0fe3 | 2020-09-03 07:32:48 -0700 | [diff] [blame] | 82 | default 0x30000 |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 83 | help |
| 84 | The amount of anticipated stack usage in CAR by bootblock and |
Tan, Lean Sheng | ece0fe3 | 2020-09-03 07:32:48 -0700 | [diff] [blame] | 85 | other stages. In the case of FSP_USES_CB_STACK default value will be |
| 86 | sum of FSP-M stack requirement (192KiB) and CB romstage stack requirement (~1KiB). |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 87 | |
| 88 | config FSP_TEMP_RAM_SIZE |
| 89 | hex |
Tan, Lean Sheng | ece0fe3 | 2020-09-03 07:32:48 -0700 | [diff] [blame] | 90 | default 0x40000 |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 91 | help |
| 92 | The amount of anticipated heap usage in CAR by FSP. |
| 93 | Refer to Platform FSP integration guide document to know |
| 94 | the exact FSP requirement for Heap setup. |
| 95 | |
| 96 | config IFD_CHIPSET |
| 97 | string |
| 98 | default "ehl" |
| 99 | |
| 100 | config IED_REGION_SIZE |
| 101 | hex |
Tan, Lean Sheng | ece0fe3 | 2020-09-03 07:32:48 -0700 | [diff] [blame] | 102 | default 0x0 |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 103 | |
| 104 | config HEAP_SIZE |
| 105 | hex |
| 106 | default 0x8000 |
| 107 | |
| 108 | config MAX_ROOT_PORTS |
| 109 | int |
Tan, Lean Sheng | ece0fe3 | 2020-09-03 07:32:48 -0700 | [diff] [blame] | 110 | default 7 |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 111 | |
Lean Sheng Tan | c6c5443 | 2021-05-30 09:08:35 -0700 | [diff] [blame] | 112 | config MAX_SATA_PORTS |
| 113 | int |
| 114 | default 2 |
| 115 | |
Rizwan Qureshi | a979460 | 2021-04-08 20:31:47 +0530 | [diff] [blame] | 116 | config MAX_PCIE_CLOCK_SRC |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 117 | int |
| 118 | default 6 |
| 119 | |
| 120 | config SMM_TSEG_SIZE |
| 121 | hex |
Tan, Lean Sheng | ece0fe3 | 2020-09-03 07:32:48 -0700 | [diff] [blame] | 122 | default 0x1000000 |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 123 | |
| 124 | config SMM_RESERVED_SIZE |
| 125 | hex |
| 126 | default 0x200000 |
| 127 | |
| 128 | config PCR_BASE_ADDRESS |
| 129 | hex |
| 130 | default 0xfd000000 |
| 131 | help |
| 132 | This option allows you to select MMIO Base Address of sideband bus. |
| 133 | |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 134 | config ECAM_MMCONF_BASE_ADDRESS |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 135 | default 0xc0000000 |
| 136 | |
| 137 | config CPU_BCLK_MHZ |
| 138 | int |
| 139 | default 100 |
| 140 | |
| 141 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
| 142 | int |
| 143 | default 120 |
| 144 | |
Michael Niewöhner | dadcbfb | 2020-10-04 14:48:05 +0200 | [diff] [blame] | 145 | config CPU_XTAL_HZ |
| 146 | default 38400000 |
| 147 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 148 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 149 | int |
| 150 | default 133 |
| 151 | |
| 152 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 153 | int |
| 154 | default 3 |
| 155 | |
| 156 | config SOC_INTEL_I2C_DEV_MAX |
| 157 | int |
Tan, Lean Sheng | ece0fe3 | 2020-09-03 07:32:48 -0700 | [diff] [blame] | 158 | default 8 |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 159 | |
| 160 | config SOC_INTEL_UART_DEV_MAX |
| 161 | int |
| 162 | default 3 |
| 163 | |
| 164 | config CONSOLE_UART_BASE_ADDRESS |
| 165 | hex |
Tan, Lean Sheng | ece0fe3 | 2020-09-03 07:32:48 -0700 | [diff] [blame] | 166 | default 0xfe042000 |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 167 | depends on INTEL_LPSS_UART_FOR_CONSOLE |
| 168 | |
| 169 | # Clock divider parameters for 115200 baud rate |
Lean Sheng Tan | 471dca7 | 2021-07-19 01:57:16 -0700 | [diff] [blame] | 170 | # Baudrate = (UART source clock * M) /(N *16) |
| 171 | # EHL UART source clock: 120MHz |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 172 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 173 | hex |
Lean Sheng Tan | 471dca7 | 2021-07-19 01:57:16 -0700 | [diff] [blame] | 174 | default 0x25a |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 175 | |
| 176 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 177 | hex |
Lean Sheng Tan | 471dca7 | 2021-07-19 01:57:16 -0700 | [diff] [blame] | 178 | default 0x7fff |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 179 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 180 | config VBOOT |
| 181 | select VBOOT_SEPARATE_VERSTAGE |
| 182 | select VBOOT_MUST_REQUEST_DISPLAY |
| 183 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 184 | select VBOOT_VBNV_CMOS |
| 185 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| 186 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 187 | config CBFS_SIZE |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 188 | default 0x200000 |
| 189 | |
| 190 | config FSP_HEADER_PATH |
Lean Sheng Tan | 79fcadb | 2021-06-04 08:54:29 -0700 | [diff] [blame] | 191 | default "3rdparty/fsp/ElkhartLakeFspBinPkg/Include/" |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 192 | |
| 193 | config FSP_FD_PATH |
Lean Sheng Tan | 79fcadb | 2021-06-04 08:54:29 -0700 | [diff] [blame] | 194 | string |
| 195 | depends on FSP_USE_REPO |
| 196 | default "3rdparty/fsp/ElkhartLakeFspBinPkg/FspBin/FSPRel.bin" |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 197 | |
Lean Sheng Tan | 5cd7579 | 2021-06-09 13:58:12 -0700 | [diff] [blame] | 198 | config PSE_ENABLE |
| 199 | bool "Enable PSE ARM controller" |
| 200 | help |
| 201 | Enable PSE IP. The PSE describes the integrated programmable |
| 202 | service engine that is designed together with x86 Atom cores |
| 203 | as an Asymmetric Multi-Processing (AMP) system. |
| 204 | |
| 205 | config ADD_PSE_IMAGE_TO_CBFS |
| 206 | bool "Add PSE Firmware to CBFS" |
| 207 | depends on PSE_ENABLE |
| 208 | default n |
| 209 | help |
| 210 | PSE FW binary is required to use PSE dedicated peripherals from |
| 211 | x86 subsystem. Once PSE is enabled, the FW will be loaded from |
| 212 | CBFS by FSP and executed. |
| 213 | |
| 214 | config PSE_IMAGE_FILE |
| 215 | string "PSE binary path and filename" |
| 216 | depends on ADD_PSE_IMAGE_TO_CBFS |
| 217 | help |
| 218 | The path and filename of the PSE binary. |
| 219 | |
| 220 | config PSE_FW_FILE_SIZE_KIB |
| 221 | hex "Memory buffer (KiB) for PSE FW image" |
| 222 | depends on ADD_PSE_IMAGE_TO_CBFS |
| 223 | default 0x200 |
| 224 | help |
| 225 | It is recommended to allocate at least 512 KiB for PSE FW. |
| 226 | |
| 227 | config PSE_CONFIG_BUFFER_SIZE_KIB |
| 228 | hex "Memory buffer (KiB) for PSE config data" |
| 229 | depends on ADD_PSE_IMAGE_TO_CBFS |
| 230 | default 0x100 |
| 231 | help |
| 232 | It is recommended to allocate at least 256 KiB for PSE config |
| 233 | data (FSP will append PSE config data to memory region right |
| 234 | after PSE FW memory region). |
| 235 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 236 | config SOC_INTEL_ELKHARTLAKE_DEBUG_CONSENT |
| 237 | int "Debug Consent for EHL" |
| 238 | # USB DBC is more common for developers so make this default to 3 if |
| 239 | # SOC_INTEL_DEBUG_CONSENT=y |
| 240 | default 3 if SOC_INTEL_DEBUG_CONSENT |
| 241 | default 0 |
| 242 | help |
| 243 | This is to control debug interface on SOC. |
| 244 | Setting non-zero value will allow to use DBC or DCI to debug SOC. |
| 245 | PlatformDebugConsent in FspmUpd.h has the details. |
| 246 | |
| 247 | Desired platform debug type are |
| 248 | 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), |
| 249 | 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), |
| 250 | 6:Enable (2-wire DCI OOB), 7:Manual |
| 251 | |
| 252 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 253 | hex |
| 254 | default 0x1400 |
Werner Zeh | 0099832 | 2022-01-18 12:31:08 +0100 | [diff] [blame] | 255 | |
| 256 | config SOC_INTEL_ELKHARTLAKE_TCO_NO_REBOOT_EN |
| 257 | bool "Disable reset on second TCO expiration" |
| 258 | depends on SOC_INTEL_COMMON_BLOCK_TCO |
| 259 | default n |
| 260 | help |
| 261 | Setting this option will prevent a host reset if the TCO timer expires |
| 262 | for the second time. Since this feature is not exposed to the OS in the |
| 263 | standard TCO interface, this setting can be enabled on firmware level. |
| 264 | This might be useful depending on the TCO policy. |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 265 | endif |