soc/intel/elkhartlake: Introduce Intel PSE
The Intel® Programmable Services Engine (Intel® PSE) is a
dedicated offload engine for IoT functions powered by an ARM
Cortex-M7 microcontroller. It provides independent, low-DMIPS
computing and low-speed I/Os for IoT applications, plus
dedicated services for real-time computing and time-sensitive
synchronization.
The PSE hosts new functions, including remote out-of-band
device management, network proxy, embedded controller lite
and sensor hub.
This CL enables the user to provide the base address of the
PSE FW blob which will then be loaded by the FSP-S onto the
ARM controller. PSE FW will do the initialization work of
PSE controller and its peripherals. The loading of PSE FW
should have negligible impact on boot time unless PSE
controller could not locate the PSE FW and FSP will attempt to
redo PSE FW loading and wait for PSE handshake until it times
out. Once PSE controller locate the PSE FW, it will do
initialization concurrently by itself with coreboot booting.
It also adds PSE related FSP-S UPD settings which enable the
setup of peripheral ownership (assigned to the PSE or x86
subsystem) and interrupts. These assignments need to take
place at a given point in the boot process and cannot be
changed later.
To verify if PSE FW is loaded properly, the user could enable
PchPseShellEnabled flag and the log will be printed at PSE UART
2.
For further info please refer to doc #611825 (for HW overview)
and #614110 (for PSE EDS).
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig
index fce2f90..3780789 100644
--- a/src/soc/intel/elkhartlake/Kconfig
+++ b/src/soc/intel/elkhartlake/Kconfig
@@ -194,6 +194,44 @@
depends on FSP_USE_REPO
default "3rdparty/fsp/ElkhartLakeFspBinPkg/FspBin/FSPRel.bin"
+config PSE_ENABLE
+ bool "Enable PSE ARM controller"
+ help
+ Enable PSE IP. The PSE describes the integrated programmable
+ service engine that is designed together with x86 Atom cores
+ as an Asymmetric Multi-Processing (AMP) system.
+
+config ADD_PSE_IMAGE_TO_CBFS
+ bool "Add PSE Firmware to CBFS"
+ depends on PSE_ENABLE
+ default n
+ help
+ PSE FW binary is required to use PSE dedicated peripherals from
+ x86 subsystem. Once PSE is enabled, the FW will be loaded from
+ CBFS by FSP and executed.
+
+config PSE_IMAGE_FILE
+ string "PSE binary path and filename"
+ depends on ADD_PSE_IMAGE_TO_CBFS
+ help
+ The path and filename of the PSE binary.
+
+config PSE_FW_FILE_SIZE_KIB
+ hex "Memory buffer (KiB) for PSE FW image"
+ depends on ADD_PSE_IMAGE_TO_CBFS
+ default 0x200
+ help
+ It is recommended to allocate at least 512 KiB for PSE FW.
+
+config PSE_CONFIG_BUFFER_SIZE_KIB
+ hex "Memory buffer (KiB) for PSE config data"
+ depends on ADD_PSE_IMAGE_TO_CBFS
+ default 0x100
+ help
+ It is recommended to allocate at least 256 KiB for PSE config
+ data (FSP will append PSE config data to memory region right
+ after PSE FW memory region).
+
config SOC_INTEL_ELKHARTLAKE_DEBUG_CONSENT
int "Debug Consent for EHL"
# USB DBC is more common for developers so make this default to 3 if