huang lin | c14b54d | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2016 Rockchip Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
huang lin | c14b54d | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 14 | */ |
| 15 | |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 16 | #include <assert.h> |
| 17 | #include <console/console.h> |
| 18 | #include <delay.h> |
| 19 | #include <soc/addressmap.h> |
huang lin | c14b54d | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 20 | #include <soc/clock.h> |
Lin Huang | f5702e7 | 2016-03-19 22:45:19 +0800 | [diff] [blame] | 21 | #include <soc/grf.h> |
huang lin | 4f17374 | 2016-03-02 18:46:24 +0800 | [diff] [blame] | 22 | #include <soc/i2c.h> |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 23 | #include <soc/soc.h> |
| 24 | #include <stdint.h> |
| 25 | #include <stdlib.h> |
| 26 | #include <string.h> |
| 27 | |
| 28 | struct pll_div { |
| 29 | u32 refdiv; |
| 30 | u32 fbdiv; |
| 31 | u32 postdiv1; |
| 32 | u32 postdiv2; |
| 33 | u32 frac; |
| 34 | }; |
| 35 | |
| 36 | #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ |
| 37 | .refdiv = _refdiv,\ |
| 38 | .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ |
| 39 | .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\ |
| 40 | _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\ |
| 41 | OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\ |
| 42 | #hz "Hz cannot be hit with PLL "\ |
| 43 | "divisors on line " STRINGIFY(__LINE__)) |
| 44 | |
| 45 | static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); |
| 46 | static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2); |
| 47 | static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1); |
| 48 | |
| 49 | static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1); |
| 50 | static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1); |
| 51 | |
| 52 | static const struct pll_div *apll_l_cfgs[] = { |
| 53 | [APLL_L_1600_MHZ] = &apll_l_1600_cfg, |
| 54 | [APLL_L_600_MHZ] = &apll_l_600_cfg, |
| 55 | }; |
| 56 | |
| 57 | enum { |
| 58 | /* PLL_CON0 */ |
| 59 | PLL_FBDIV_MASK = 0xfff, |
| 60 | PLL_FBDIV_SHIFT = 0, |
| 61 | |
| 62 | /* PLL_CON1 */ |
| 63 | PLL_POSTDIV2_MASK = 0x7, |
| 64 | PLL_POSTDIV2_SHIFT = 12, |
| 65 | PLL_POSTDIV1_MASK = 0x7, |
| 66 | PLL_POSTDIV1_SHIFT = 8, |
| 67 | PLL_REFDIV_MASK = 0x3f, |
| 68 | PLL_REFDIV_SHIFT = 0, |
| 69 | |
| 70 | /* PLL_CON2 */ |
| 71 | PLL_LOCK_STATUS_MASK = 1, |
| 72 | PLL_LOCK_STATUS_SHIFT = 31, |
| 73 | PLL_FRACDIV_MASK = 0xffffff, |
| 74 | PLL_FRACDIV_SHIFT = 0, |
| 75 | |
| 76 | /* PLL_CON3 */ |
| 77 | PLL_MODE_MASK = 3, |
| 78 | PLL_MODE_SHIFT = 8, |
| 79 | PLL_MODE_SLOW = 0, |
| 80 | PLL_MODE_NORM, |
| 81 | PLL_MODE_DEEP, |
| 82 | PLL_DSMPD_MASK = 1, |
| 83 | PLL_DSMPD_SHIFT = 3, |
| 84 | PLL_INTEGER_MODE = 1, |
| 85 | |
| 86 | /* PMUCRU_CLKSEL_CON0 */ |
| 87 | PMU_PCLK_DIV_CON_MASK = 0x1f, |
| 88 | PMU_PCLK_DIV_CON_SHIFT = 0, |
| 89 | |
Shunqian Zheng | 347c83c | 2016-04-13 22:34:39 +0800 | [diff] [blame] | 90 | /* PMUCRU_CLKSEL_CON1 */ |
| 91 | SPI3_PLL_SEL_MASK = 1, |
| 92 | SPI3_PLL_SEL_SHIFT = 7, |
| 93 | SPI3_PLL_SEL_24M = 0, |
| 94 | SPI3_PLL_SEL_PPLL = 1, |
| 95 | SPI3_DIV_CON_MASK = 0x7f, |
| 96 | SPI3_DIV_CON_SHIFT = 0x0, |
| 97 | |
huang lin | 4f17374 | 2016-03-02 18:46:24 +0800 | [diff] [blame] | 98 | /* PMUCRU_CLKSEL_CON2 */ |
| 99 | I2C_DIV_CON_MASK = 0x7f, |
| 100 | I2C8_DIV_CON_SHIFT = 8, |
| 101 | I2C0_DIV_CON_SHIFT = 0, |
| 102 | |
| 103 | /* PMUCRU_CLKSEL_CON3 */ |
| 104 | I2C4_DIV_CON_SHIFT = 0, |
| 105 | |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 106 | /* CLKSEL_CON0 */ |
| 107 | ACLKM_CORE_L_DIV_CON_MASK = 0x1f, |
| 108 | ACLKM_CORE_L_DIV_CON_SHIFT = 8, |
| 109 | CLK_CORE_L_PLL_SEL_MASK = 3, |
| 110 | CLK_CORE_L_PLL_SEL_SHIFT = 6, |
| 111 | CLK_CORE_L_PLL_SEL_ALPLL = 0x0, |
| 112 | CLK_CORE_L_PLL_SEL_ABPLL = 0x1, |
| 113 | CLK_CORE_L_PLL_SEL_DPLL = 0x10, |
| 114 | CLK_CORE_L_PLL_SEL_GPLL = 0x11, |
| 115 | CLK_CORE_L_DIV_MASK = 0x1f, |
| 116 | CLK_CORE_L_DIV_SHIFT = 0, |
| 117 | |
| 118 | /* CLKSEL_CON1 */ |
| 119 | PCLK_DBG_L_DIV_MASK = 0x1f, |
| 120 | PCLK_DBG_L_DIV_SHIFT = 0x8, |
| 121 | ATCLK_CORE_L_DIV_MASK = 0x1f, |
| 122 | ATCLK_CORE_L_DIV_SHIFT = 0, |
| 123 | |
| 124 | /* CLKSEL_CON14 */ |
| 125 | PCLK_PERIHP_DIV_CON_MASK = 0x7, |
| 126 | PCLK_PERIHP_DIV_CON_SHIFT = 12, |
| 127 | HCLK_PERIHP_DIV_CON_MASK = 3, |
| 128 | HCLK_PERIHP_DIV_CON_SHIFT = 8, |
| 129 | ACLK_PERIHP_PLL_SEL_MASK = 1, |
| 130 | ACLK_PERIHP_PLL_SEL_SHIFT = 7, |
| 131 | ACLK_PERIHP_PLL_SEL_CPLL = 0, |
| 132 | ACLK_PERIHP_PLL_SEL_GPLL = 1, |
| 133 | ACLK_PERIHP_DIV_CON_MASK = 0x1f, |
| 134 | ACLK_PERIHP_DIV_CON_SHIFT = 0, |
| 135 | |
Lin Huang | 2f7ed8d | 2016-04-08 18:56:20 +0800 | [diff] [blame] | 136 | /* CLKSEL_CON21 */ |
| 137 | ACLK_EMMC_PLL_SEL_MASK = 0x1, |
| 138 | ACLK_EMMC_PLL_SEL_SHIFT = 7, |
| 139 | ACLK_EMMC_PLL_SEL_GPLL = 0x1, |
| 140 | ACLK_EMMC_DIV_CON_MASK = 0x1f, |
| 141 | ACLK_EMMC_DIV_CON_SHIFT = 0, |
| 142 | |
| 143 | /* CLKSEL_CON22 */ |
| 144 | CLK_EMMC_PLL_MASK = 0x7, |
| 145 | CLK_EMMC_PLL_SHIFT = 8, |
| 146 | CLK_EMMC_PLL_SEL_GPLL = 0x1, |
| 147 | CLK_EMMC_DIV_CON_MASK = 0x7f, |
| 148 | CLK_EMMC_DIV_CON_SHIFT = 0, |
| 149 | |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 150 | /* CLKSEL_CON23 */ |
| 151 | PCLK_PERILP0_DIV_CON_MASK = 0x7, |
| 152 | PCLK_PERILP0_DIV_CON_SHIFT = 12, |
| 153 | HCLK_PERILP0_DIV_CON_MASK = 3, |
| 154 | HCLK_PERILP0_DIV_CON_SHIFT = 8, |
| 155 | ACLK_PERILP0_PLL_SEL_MASK = 1, |
| 156 | ACLK_PERILP0_PLL_SEL_SHIFT = 7, |
| 157 | ACLK_PERILP0_PLL_SEL_CPLL = 0, |
| 158 | ACLK_PERILP0_PLL_SEL_GPLL = 1, |
| 159 | ACLK_PERILP0_DIV_CON_MASK = 0x1f, |
| 160 | ACLK_PERILP0_DIV_CON_SHIFT = 0, |
| 161 | |
| 162 | /* CLKSEL_CON25 */ |
| 163 | PCLK_PERILP1_DIV_CON_MASK = 0x7, |
| 164 | PCLK_PERILP1_DIV_CON_SHIFT = 8, |
| 165 | HCLK_PERILP1_PLL_SEL_MASK = 1, |
| 166 | HCLK_PERILP1_PLL_SEL_SHIFT = 7, |
| 167 | HCLK_PERILP1_PLL_SEL_CPLL = 0, |
| 168 | HCLK_PERILP1_PLL_SEL_GPLL = 1, |
| 169 | HCLK_PERILP1_DIV_CON_MASK = 0x1f, |
| 170 | HCLK_PERILP1_DIV_CON_SHIFT = 0, |
Shunqian Zheng | ce60d5a | 2016-04-21 23:53:08 +0800 | [diff] [blame] | 171 | |
Lin Huang | bf48fbb | 2016-03-23 19:24:53 +0800 | [diff] [blame] | 172 | /* CLKSEL_CON26 */ |
| 173 | CLK_SARADC_DIV_CON_MASK = 0xff, |
| 174 | CLK_SARADC_DIV_CON_SHIFT = 8, |
| 175 | |
Shunqian Zheng | f4181ce | 2016-05-06 16:50:48 +0800 | [diff] [blame] | 176 | /* CLKSEL_CON27 */ |
| 177 | CLK_TSADC_SEL_X24M = 0x0, |
| 178 | CLK_TSADC_SEL_MASK = 1, |
| 179 | CLK_TSADC_SEL_SHIFT = 15, |
| 180 | CLK_TSADC_DIV_CON_MASK = 0x3ff, |
| 181 | CLK_TSADC_DIV_CON_SHIFT = 0, |
| 182 | |
Shunqian Zheng | c7f32a5 | 2016-05-04 15:54:37 +0800 | [diff] [blame] | 183 | /* CLKSEL_CON47 & CLKSEL_CON48 */ |
| 184 | ACLK_VOP_PLL_SEL_MASK = 0x3, |
| 185 | ACLK_VOP_PLL_SEL_SHIFT = 6, |
| 186 | ACLK_VOP_PLL_SEL_CPLL = 0x1, |
| 187 | ACLK_VOP_DIV_CON_MASK = 0x1f, |
| 188 | ACLK_VOP_DIV_CON_SHIFT = 0, |
| 189 | |
| 190 | /* CLKSEL_CON49 & CLKSEL_CON50 */ |
| 191 | DCLK_VOP_DCLK_SEL_MASK = 1, |
| 192 | DCLK_VOP_DCLK_SEL_SHIFT = 11, |
| 193 | DCLK_VOP_DCLK_SEL_DIVOUT = 0, |
| 194 | DCLK_VOP_PLL_SEL_MASK = 3, |
| 195 | DCLK_VOP_PLL_SEL_SHIFT = 8, |
| 196 | DCLK_VOP_PLL_SEL_VPLL = 0, |
| 197 | DCLK_VOP_DIV_CON_MASK = 0xff, |
| 198 | DCLK_VOP_DIV_CON_SHIFT = 0, |
| 199 | |
Shunqian Zheng | 347c83c | 2016-04-13 22:34:39 +0800 | [diff] [blame] | 200 | /* CLKSEL_CON58 */ |
| 201 | CLK_SPI_PLL_SEL_MASK = 1, |
| 202 | CLK_SPI_PLL_SEL_CPLL = 0, |
| 203 | CLK_SPI_PLL_SEL_GPLL = 1, |
| 204 | CLK_SPI_PLL_DIV_CON_MASK = 0x7f, |
| 205 | CLK_SPI5_PLL_DIV_CON_SHIFT = 8, |
| 206 | CLK_SPI5_PLL_SEL_SHIFT = 15, |
| 207 | |
| 208 | /* CLKSEL_CON59 */ |
| 209 | CLK_SPI1_PLL_SEL_SHIFT = 15, |
| 210 | CLK_SPI1_PLL_DIV_CON_SHIFT = 8, |
| 211 | CLK_SPI0_PLL_SEL_SHIFT = 7, |
| 212 | CLK_SPI0_PLL_DIV_CON_SHIFT = 0, |
| 213 | |
| 214 | /* CLKSEL_CON60 */ |
| 215 | CLK_SPI4_PLL_SEL_SHIFT = 15, |
| 216 | CLK_SPI4_PLL_DIV_CON_SHIFT = 8, |
| 217 | CLK_SPI2_PLL_SEL_SHIFT = 7, |
| 218 | CLK_SPI2_PLL_DIV_CON_SHIFT = 0, |
| 219 | |
huang lin | 4f17374 | 2016-03-02 18:46:24 +0800 | [diff] [blame] | 220 | /* CLKSEL_CON61 */ |
| 221 | CLK_I2C_PLL_SEL_MASK = 1, |
| 222 | CLK_I2C_PLL_SEL_CPLL = 0, |
| 223 | CLK_I2C_PLL_SEL_GPLL = 1, |
| 224 | CLK_I2C5_PLL_SEL_SHIFT = 15, |
| 225 | CLK_I2C5_DIV_CON_SHIFT = 8, |
| 226 | CLK_I2C1_PLL_SEL_SHIFT = 7, |
| 227 | CLK_I2C1_DIV_CON_SHIFT = 0, |
| 228 | |
| 229 | /* CLKSEL_CON62 */ |
| 230 | CLK_I2C6_PLL_SEL_SHIFT = 15, |
| 231 | CLK_I2C6_DIV_CON_SHIFT = 8, |
| 232 | CLK_I2C2_PLL_SEL_SHIFT = 7, |
| 233 | CLK_I2C2_DIV_CON_SHIFT = 0, |
| 234 | |
| 235 | /* CLKSEL_CON63 */ |
| 236 | CLK_I2C7_PLL_SEL_SHIFT = 15, |
| 237 | CLK_I2C7_DIV_CON_SHIFT = 8, |
| 238 | CLK_I2C3_PLL_SEL_SHIFT = 7, |
| 239 | CLK_I2C3_DIV_CON_SHIFT = 0, |
| 240 | |
Shunqian Zheng | ce60d5a | 2016-04-21 23:53:08 +0800 | [diff] [blame] | 241 | /* CRU_SOFTRST_CON4 */ |
| 242 | RESETN_DDR0_REQ_MASK = 1, |
| 243 | RESETN_DDR0_REQ_SHIFT = 8, |
| 244 | RESETN_DDRPHY0_REQ_MASK = 1, |
| 245 | RESETN_DDRPHY0_REQ_SHIFT = 9, |
| 246 | RESETN_DDR1_REQ_MASK = 1, |
| 247 | RESETN_DDR1_REQ_SHIFT = 12, |
| 248 | RESETN_DDRPHY1_REQ_MASK = 1, |
| 249 | RESETN_DDRPHY1_REQ_SHIFT = 13, |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 250 | }; |
| 251 | |
| 252 | #define VCO_MAX_KHZ (3200 * (MHz / KHz)) |
| 253 | #define VCO_MIN_KHZ (800 * (MHz / KHz)) |
| 254 | #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz)) |
| 255 | #define OUTPUT_MIN_KHZ (16 * (MHz / KHz)) |
| 256 | |
| 257 | /* the div restrictions of pll in integer mode, |
| 258 | * these are defined in * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0 |
| 259 | */ |
| 260 | #define PLL_DIV_MIN 16 |
| 261 | #define PLL_DIV_MAX 3200 |
| 262 | |
| 263 | /* How to calculate the PLL(from TRM V0.3 Part 1 Page 63): |
| 264 | * Formulas also embedded within the Fractional PLL Verilog model: |
| 265 | * If DSMPD = 1 (DSM is disabled, "integer mode") |
| 266 | * FOUTVCO = FREF / REFDIV * FBDIV |
| 267 | * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 |
| 268 | * Where: |
| 269 | * FOUTVCO = Fractional PLL non-divided output frequency |
| 270 | * FOUTPOSTDIV = Fractional PLL divided output frequency |
| 271 | * (output of second post divider) |
| 272 | * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input) |
| 273 | * REFDIV = Fractional PLL input reference clock divider |
| 274 | * FBDIV = Integer value programmed into feedback divide |
| 275 | * |
| 276 | */ |
| 277 | static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div) |
| 278 | { |
| 279 | /* All 8 PLLs have same VCO and output frequency range restrictions. */ |
| 280 | u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; |
| 281 | u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; |
| 282 | |
| 283 | printk(BIOS_DEBUG, "PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, " |
| 284 | "postdiv2=%d, vco=%u khz, output=%u khz\n", |
| 285 | pll_con, div->fbdiv, div->refdiv, div->postdiv1, |
| 286 | div->postdiv2, vco_khz, output_khz); |
| 287 | assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ && |
| 288 | output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ && |
| 289 | div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); |
| 290 | |
| 291 | /* When power on or changing PLL setting, |
| 292 | * we must force PLL into slow mode to ensure output stable clock. |
| 293 | */ |
| 294 | write32(&pll_con[3], RK_CLRSETBITS(PLL_MODE_MASK << PLL_MODE_SHIFT, |
| 295 | PLL_MODE_SLOW << PLL_MODE_SHIFT)); |
| 296 | |
| 297 | /* use integer mode */ |
| 298 | write32(&pll_con[3], |
| 299 | RK_CLRSETBITS(PLL_DSMPD_MASK << PLL_DSMPD_SHIFT, |
| 300 | PLL_INTEGER_MODE << PLL_DSMPD_SHIFT)); |
| 301 | |
| 302 | write32(&pll_con[0], RK_CLRSETBITS(PLL_FBDIV_MASK << PLL_FBDIV_SHIFT, |
| 303 | div->fbdiv << PLL_FBDIV_SHIFT)); |
| 304 | write32(&pll_con[1], |
| 305 | RK_CLRSETBITS(PLL_POSTDIV2_MASK << PLL_POSTDIV2_SHIFT | |
| 306 | PLL_POSTDIV1_MASK << PLL_POSTDIV1_SHIFT | |
| 307 | PLL_REFDIV_MASK | PLL_REFDIV_SHIFT, |
| 308 | (div->postdiv2 << PLL_POSTDIV2_SHIFT) | |
| 309 | (div->postdiv1 << PLL_POSTDIV1_SHIFT) | |
| 310 | (div->refdiv << PLL_REFDIV_SHIFT))); |
| 311 | |
| 312 | /* waiting for pll lock */ |
| 313 | while (!(read32(&pll_con[2]) & (1 << PLL_LOCK_STATUS_SHIFT))) |
| 314 | udelay(1); |
| 315 | |
| 316 | /* pll enter normal mode */ |
| 317 | write32(&pll_con[3], RK_CLRSETBITS(PLL_MODE_MASK << PLL_MODE_SHIFT, |
| 318 | PLL_MODE_NORM << PLL_MODE_SHIFT)); |
| 319 | } |
| 320 | |
Shunqian Zheng | c7f32a5 | 2016-05-04 15:54:37 +0800 | [diff] [blame] | 321 | static int pll_para_config(u32 freq_hz, struct pll_div *div) |
| 322 | { |
| 323 | u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; |
| 324 | u32 postdiv1, postdiv2 = 1; |
| 325 | u32 fref_khz; |
| 326 | u32 diff_khz, best_diff_khz; |
| 327 | const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16; |
| 328 | const u32 max_postdiv1 = 7, max_postdiv2 = 7; |
| 329 | u32 vco_khz; |
| 330 | u32 freq_khz = freq_hz / KHz; |
| 331 | |
| 332 | if (!freq_hz) { |
| 333 | printk(BIOS_ERR, "%s: the frequency can't be 0 Hz\n", __func__); |
| 334 | return -1; |
| 335 | } |
| 336 | |
| 337 | postdiv1 = div_round_up(VCO_MIN_KHZ, freq_khz); |
| 338 | if (postdiv1 > max_postdiv1) { |
| 339 | postdiv2 = div_round_up(postdiv1, max_postdiv1); |
| 340 | postdiv1 = div_round_up(postdiv1, postdiv2); |
| 341 | } |
| 342 | |
| 343 | vco_khz = freq_khz * postdiv1 * postdiv2; |
| 344 | |
| 345 | if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || |
| 346 | postdiv2 > max_postdiv2) { |
| 347 | printk(BIOS_ERR, "%s: Cannot find out a supported VCO" |
| 348 | " for Frequency (%uHz).\n", __func__, freq_hz); |
| 349 | return -1; |
| 350 | } |
| 351 | |
| 352 | div->postdiv1 = postdiv1; |
| 353 | div->postdiv2 = postdiv2; |
| 354 | |
| 355 | best_diff_khz = vco_khz; |
| 356 | for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) { |
| 357 | fref_khz = ref_khz / refdiv; |
| 358 | |
| 359 | fbdiv = vco_khz / fref_khz; |
| 360 | if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv)) |
| 361 | continue; |
| 362 | diff_khz = vco_khz - fbdiv * fref_khz; |
| 363 | if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) { |
| 364 | fbdiv++; |
| 365 | diff_khz = fref_khz - diff_khz; |
| 366 | } |
| 367 | |
| 368 | if (diff_khz >= best_diff_khz) |
| 369 | continue; |
| 370 | |
| 371 | best_diff_khz = diff_khz; |
| 372 | div->refdiv = refdiv; |
| 373 | div->fbdiv = fbdiv; |
| 374 | } |
| 375 | |
| 376 | if (best_diff_khz > 4 * (MHz/KHz)) { |
| 377 | printk(BIOS_ERR, "%s: Failed to match output frequency %u, " |
| 378 | "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz, |
| 379 | best_diff_khz * KHz); |
| 380 | return -1; |
| 381 | } |
| 382 | return 0; |
| 383 | } |
| 384 | |
Lin Huang | a1f82a3 | 2016-03-09 18:08:20 +0800 | [diff] [blame] | 385 | void rkclk_init(void) |
| 386 | { |
| 387 | u32 aclk_div; |
| 388 | u32 hclk_div; |
| 389 | u32 pclk_div; |
| 390 | |
| 391 | /* some cru registers changed by bootrom, we'd better reset them to |
| 392 | * reset/default values described in TRM to avoid confusion in kernel. |
| 393 | * Please consider these threee lines as a fix of bootrom bug. |
| 394 | */ |
| 395 | write32(&cru_ptr->clksel_con[12], 0xffff4101); |
| 396 | write32(&cru_ptr->clksel_con[19], 0xffff033f); |
| 397 | write32(&cru_ptr->clksel_con[56], 0x00030003); |
| 398 | |
| 399 | /* configure pmu pll(ppll) */ |
| 400 | rkclk_set_pll(&pmucru_ptr->ppll_con[0], &ppll_init_cfg); |
| 401 | |
| 402 | /* configure pmu pclk */ |
| 403 | pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1; |
| 404 | assert((pclk_div + 1) * PMU_PCLK_HZ == PPLL_HZ && pclk_div < 0x1f); |
| 405 | write32(&pmucru_ptr->pmucru_clksel[0], |
| 406 | RK_CLRSETBITS(PMU_PCLK_DIV_CON_MASK << PMU_PCLK_DIV_CON_SHIFT, |
| 407 | pclk_div << PMU_PCLK_DIV_CON_SHIFT)); |
| 408 | |
| 409 | /* configure gpll cpll */ |
| 410 | rkclk_set_pll(&cru_ptr->gpll_con[0], &gpll_init_cfg); |
| 411 | rkclk_set_pll(&cru_ptr->cpll_con[0], &cpll_init_cfg); |
| 412 | |
| 413 | /* configure perihp aclk, hclk, pclk */ |
| 414 | aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1; |
| 415 | assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); |
| 416 | |
| 417 | hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1; |
| 418 | assert((hclk_div + 1) * PERIHP_HCLK_HZ == |
| 419 | PERIHP_ACLK_HZ && (hclk_div < 0x4)); |
| 420 | |
| 421 | pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1; |
| 422 | assert((pclk_div + 1) * PERIHP_PCLK_HZ == |
| 423 | PERIHP_ACLK_HZ && (pclk_div < 0x7)); |
| 424 | |
| 425 | write32(&cru_ptr->clksel_con[14], |
| 426 | RK_CLRSETBITS(PCLK_PERIHP_DIV_CON_MASK << |
| 427 | PCLK_PERIHP_DIV_CON_SHIFT | |
| 428 | HCLK_PERIHP_DIV_CON_MASK << |
| 429 | HCLK_PERIHP_DIV_CON_SHIFT | |
| 430 | ACLK_PERIHP_PLL_SEL_MASK << |
| 431 | ACLK_PERIHP_PLL_SEL_SHIFT | |
| 432 | ACLK_PERIHP_DIV_CON_MASK << |
| 433 | ACLK_PERIHP_DIV_CON_SHIFT, |
| 434 | pclk_div << PCLK_PERIHP_DIV_CON_SHIFT | |
| 435 | hclk_div << HCLK_PERIHP_DIV_CON_SHIFT | |
| 436 | ACLK_PERIHP_PLL_SEL_GPLL << |
| 437 | ACLK_PERIHP_PLL_SEL_SHIFT | |
| 438 | aclk_div << ACLK_PERIHP_DIV_CON_SHIFT)); |
| 439 | |
| 440 | /* configure perilp0 aclk, hclk, pclk */ |
| 441 | aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1; |
| 442 | assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); |
| 443 | |
| 444 | hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1; |
| 445 | assert((hclk_div + 1) * PERILP0_HCLK_HZ == |
| 446 | PERILP0_ACLK_HZ && (hclk_div < 0x4)); |
| 447 | |
| 448 | pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1; |
| 449 | assert((pclk_div + 1) * PERILP0_PCLK_HZ == |
| 450 | PERILP0_ACLK_HZ && (pclk_div < 0x7)); |
| 451 | |
| 452 | write32(&cru_ptr->clksel_con[23], |
| 453 | RK_CLRSETBITS(PCLK_PERILP0_DIV_CON_MASK << |
| 454 | PCLK_PERILP0_DIV_CON_SHIFT | |
| 455 | HCLK_PERILP0_DIV_CON_MASK << |
| 456 | HCLK_PERILP0_DIV_CON_SHIFT | |
| 457 | ACLK_PERILP0_PLL_SEL_MASK << |
| 458 | ACLK_PERILP0_PLL_SEL_SHIFT | |
| 459 | ACLK_PERILP0_DIV_CON_MASK << |
| 460 | ACLK_PERILP0_DIV_CON_SHIFT, |
| 461 | pclk_div << PCLK_PERILP0_DIV_CON_SHIFT | |
| 462 | hclk_div << HCLK_PERILP0_DIV_CON_SHIFT | |
| 463 | ACLK_PERILP0_PLL_SEL_GPLL << |
| 464 | ACLK_PERILP0_PLL_SEL_SHIFT | |
| 465 | aclk_div << ACLK_PERILP0_DIV_CON_SHIFT)); |
| 466 | |
| 467 | /* perilp1 hclk select gpll as source */ |
| 468 | hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1; |
| 469 | assert((hclk_div + 1) * PERILP1_HCLK_HZ == |
| 470 | GPLL_HZ && (hclk_div < 0x1f)); |
| 471 | |
| 472 | pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1; |
| 473 | assert((pclk_div + 1) * PERILP1_HCLK_HZ == |
| 474 | PERILP1_HCLK_HZ && (hclk_div < 0x7)); |
| 475 | |
| 476 | write32(&cru_ptr->clksel_con[25], |
| 477 | RK_CLRSETBITS(PCLK_PERILP1_DIV_CON_MASK << |
| 478 | PCLK_PERILP1_DIV_CON_SHIFT | |
| 479 | HCLK_PERILP1_DIV_CON_MASK << |
| 480 | HCLK_PERILP1_DIV_CON_SHIFT | |
| 481 | HCLK_PERILP1_PLL_SEL_MASK << |
| 482 | HCLK_PERILP1_PLL_SEL_SHIFT, |
| 483 | pclk_div << PCLK_PERILP1_DIV_CON_SHIFT | |
| 484 | hclk_div << HCLK_PERILP1_DIV_CON_SHIFT | |
| 485 | HCLK_PERILP1_PLL_SEL_GPLL << |
| 486 | HCLK_PERILP1_PLL_SEL_SHIFT)); |
| 487 | } |
| 488 | |
| 489 | void rkclk_configure_cpu(enum apll_l_frequencies apll_l_freq) |
| 490 | { |
| 491 | u32 aclkm_div; |
| 492 | u32 pclk_dbg_div; |
| 493 | u32 atclk_div; |
| 494 | |
| 495 | rkclk_set_pll(&cru_ptr->apll_l_con[0], apll_l_cfgs[apll_l_freq]); |
| 496 | |
| 497 | aclkm_div = APLL_HZ / ACLKM_CORE_HZ - 1; |
| 498 | assert((aclkm_div + 1) * ACLKM_CORE_HZ == APLL_HZ && |
| 499 | aclkm_div < 0x1f); |
| 500 | |
| 501 | pclk_dbg_div = APLL_HZ / PCLK_DBG_HZ - 1; |
| 502 | assert((pclk_dbg_div + 1) * PCLK_DBG_HZ == APLL_HZ && |
| 503 | pclk_dbg_div < 0x1f); |
| 504 | |
| 505 | atclk_div = APLL_HZ / ATCLK_CORE_HZ - 1; |
| 506 | assert((atclk_div + 1) * ATCLK_CORE_HZ == APLL_HZ && |
| 507 | atclk_div < 0x1f); |
| 508 | |
| 509 | write32(&cru_ptr->clksel_con[0], |
| 510 | RK_CLRSETBITS(ACLKM_CORE_L_DIV_CON_MASK << |
| 511 | ACLKM_CORE_L_DIV_CON_SHIFT | |
| 512 | CLK_CORE_L_PLL_SEL_MASK << |
| 513 | CLK_CORE_L_PLL_SEL_SHIFT | |
| 514 | CLK_CORE_L_DIV_MASK << CLK_CORE_L_DIV_SHIFT, |
| 515 | aclkm_div << ACLKM_CORE_L_DIV_CON_SHIFT | |
| 516 | CLK_CORE_L_PLL_SEL_ALPLL << |
| 517 | CLK_CORE_L_PLL_SEL_SHIFT | |
| 518 | 0 << CLK_CORE_L_DIV_SHIFT)); |
| 519 | |
| 520 | write32(&cru_ptr->clksel_con[1], |
| 521 | RK_CLRSETBITS(PCLK_DBG_L_DIV_MASK << PCLK_DBG_L_DIV_SHIFT | |
| 522 | ATCLK_CORE_L_DIV_MASK << ATCLK_CORE_L_DIV_SHIFT, |
| 523 | pclk_dbg_div << PCLK_DBG_L_DIV_SHIFT | |
| 524 | atclk_div << ATCLK_CORE_L_DIV_SHIFT)); |
| 525 | } |
Lin Huang | f5702e7 | 2016-03-19 22:45:19 +0800 | [diff] [blame] | 526 | |
Shunqian Zheng | ce60d5a | 2016-04-21 23:53:08 +0800 | [diff] [blame] | 527 | void rkclk_configure_ddr(unsigned int hz) |
| 528 | { |
| 529 | struct pll_div dpll_cfg; |
| 530 | |
| 531 | /* IC ECO bug, need to set this register */ |
| 532 | write32(&rk3399_pmusgrf->ddr_rgn_con[16], 0xc000c000); |
| 533 | |
| 534 | /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */ |
| 535 | switch (hz) { |
| 536 | case 200*MHz: |
| 537 | dpll_cfg = (struct pll_div) |
| 538 | {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1}; |
| 539 | break; |
| 540 | case 300*MHz: |
| 541 | dpll_cfg = (struct pll_div) |
| 542 | {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1}; |
| 543 | break; |
| 544 | case 666*MHz: |
| 545 | dpll_cfg = (struct pll_div) |
| 546 | {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1}; |
| 547 | break; |
| 548 | case 800*MHz: |
| 549 | dpll_cfg = (struct pll_div) |
| 550 | {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}; |
| 551 | break; |
Shunqian Zheng | 0d9839b | 2016-05-11 15:18:17 +0800 | [diff] [blame] | 552 | case 928*MHz: |
| 553 | dpll_cfg = (struct pll_div) |
| 554 | {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1}; |
| 555 | break; |
Shunqian Zheng | ce60d5a | 2016-04-21 23:53:08 +0800 | [diff] [blame] | 556 | default: |
| 557 | die("Unsupported SDRAM frequency, add to clock.c!"); |
| 558 | } |
| 559 | rkclk_set_pll(&cru_ptr->dpll_con[0], &dpll_cfg); |
| 560 | } |
| 561 | |
Shunqian Zheng | 347c83c | 2016-04-13 22:34:39 +0800 | [diff] [blame] | 562 | #define SPI_CLK_REG_VALUE(bus, clk_div) \ |
| 563 | RK_CLRSETBITS(CLK_SPI_PLL_SEL_MASK << \ |
| 564 | CLK_SPI ##bus## _PLL_SEL_SHIFT | \ |
| 565 | CLK_SPI_PLL_DIV_CON_MASK << \ |
| 566 | CLK_SPI ##bus## _PLL_DIV_CON_SHIFT, \ |
| 567 | CLK_SPI_PLL_SEL_GPLL << \ |
| 568 | CLK_SPI ##bus## _PLL_SEL_SHIFT | \ |
| 569 | (clk_div - 1) << \ |
| 570 | CLK_SPI ##bus## _PLL_DIV_CON_SHIFT) |
| 571 | |
huang lin | c14b54d | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 572 | void rkclk_configure_spi(unsigned int bus, unsigned int hz) |
| 573 | { |
Shunqian Zheng | 347c83c | 2016-04-13 22:34:39 +0800 | [diff] [blame] | 574 | int src_clk_div; |
| 575 | int pll; |
| 576 | |
| 577 | /* spi3 src clock from ppll, while spi0,1,2,4,5 src clock from gpll */ |
| 578 | pll = (bus == 3) ? PPLL_HZ : GPLL_HZ; |
| 579 | src_clk_div = pll / hz; |
| 580 | assert((src_clk_div - 1 < 127) && (src_clk_div * hz == pll)); |
| 581 | |
| 582 | switch (bus) { |
| 583 | case 0: |
| 584 | write32(&cru_ptr->clksel_con[59], |
| 585 | SPI_CLK_REG_VALUE(0, src_clk_div)); |
| 586 | break; |
| 587 | case 1: |
| 588 | write32(&cru_ptr->clksel_con[59], |
| 589 | SPI_CLK_REG_VALUE(1, src_clk_div)); |
| 590 | break; |
| 591 | case 2: |
| 592 | write32(&cru_ptr->clksel_con[60], |
| 593 | SPI_CLK_REG_VALUE(2, src_clk_div)); |
| 594 | break; |
| 595 | case 3: |
| 596 | write32(&pmucru_ptr->pmucru_clksel[1], |
| 597 | RK_CLRSETBITS(SPI3_PLL_SEL_MASK << SPI3_PLL_SEL_SHIFT | |
| 598 | SPI3_DIV_CON_MASK << SPI3_DIV_CON_SHIFT, |
| 599 | SPI3_PLL_SEL_PPLL << SPI3_PLL_SEL_SHIFT | |
| 600 | (src_clk_div - 1) << SPI3_DIV_CON_SHIFT)); |
| 601 | break; |
| 602 | case 4: |
| 603 | write32(&cru_ptr->clksel_con[60], |
| 604 | SPI_CLK_REG_VALUE(4, src_clk_div)); |
| 605 | break; |
| 606 | case 5: |
| 607 | write32(&cru_ptr->clksel_con[58], |
| 608 | SPI_CLK_REG_VALUE(5, src_clk_div)); |
| 609 | break; |
| 610 | default: |
| 611 | printk(BIOS_ERR, "do not support this spi bus\n"); |
| 612 | } |
huang lin | c14b54d | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 613 | } |
huang lin | 4f17374 | 2016-03-02 18:46:24 +0800 | [diff] [blame] | 614 | |
| 615 | #define I2C_CLK_REG_VALUE(bus, clk_div) \ |
| 616 | RK_CLRSETBITS(I2C_DIV_CON_MASK << \ |
| 617 | CLK_I2C ##bus## _DIV_CON_SHIFT | \ |
| 618 | CLK_I2C_PLL_SEL_MASK << \ |
| 619 | CLK_I2C ##bus## _PLL_SEL_SHIFT, \ |
| 620 | (clk_div - 1) << \ |
| 621 | CLK_I2C ##bus## _DIV_CON_SHIFT | \ |
| 622 | CLK_I2C_PLL_SEL_GPLL << \ |
| 623 | CLK_I2C ##bus## _PLL_SEL_SHIFT) |
| 624 | #define PMU_I2C_CLK_REG_VALUE(bus, clk_div) \ |
| 625 | RK_CLRSETBITS(I2C_DIV_CON_MASK << I2C ##bus## _DIV_CON_SHIFT, \ |
| 626 | (clk_div - 1) << I2C ##bus## _DIV_CON_SHIFT) |
| 627 | |
| 628 | static void rkclk_configure_i2c(unsigned int bus, unsigned int hz) |
| 629 | { |
| 630 | int src_clk_div; |
| 631 | int pll; |
| 632 | |
| 633 | /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/ |
| 634 | pll = (bus == 0 || bus == 4 || bus == 8) ? PPLL_HZ : GPLL_HZ; |
| 635 | src_clk_div = pll / hz; |
| 636 | assert((src_clk_div - 1 < 127) && (src_clk_div * hz == pll)); |
| 637 | |
| 638 | switch (bus) { |
| 639 | case 0: |
| 640 | write32(&pmucru_ptr->pmucru_clksel[2], |
| 641 | PMU_I2C_CLK_REG_VALUE(0, src_clk_div)); |
| 642 | break; |
| 643 | case 1: |
| 644 | write32(&cru_ptr->clksel_con[61], |
| 645 | I2C_CLK_REG_VALUE(1, src_clk_div)); |
| 646 | break; |
| 647 | case 2: |
| 648 | write32(&cru_ptr->clksel_con[62], |
| 649 | I2C_CLK_REG_VALUE(2, src_clk_div)); |
| 650 | break; |
| 651 | case 3: |
| 652 | write32(&cru_ptr->clksel_con[63], |
| 653 | I2C_CLK_REG_VALUE(3, src_clk_div)); |
| 654 | break; |
| 655 | case 4: |
| 656 | write32(&pmucru_ptr->pmucru_clksel[3], |
| 657 | PMU_I2C_CLK_REG_VALUE(4, src_clk_div)); |
| 658 | break; |
| 659 | case 5: |
| 660 | write32(&cru_ptr->clksel_con[61], |
| 661 | I2C_CLK_REG_VALUE(5, src_clk_div)); |
| 662 | break; |
| 663 | case 6: |
| 664 | write32(&cru_ptr->clksel_con[62], |
| 665 | I2C_CLK_REG_VALUE(6, src_clk_div)); |
| 666 | break; |
| 667 | case 7: |
| 668 | write32(&cru_ptr->clksel_con[63], |
| 669 | I2C_CLK_REG_VALUE(7, src_clk_div)); |
| 670 | break; |
| 671 | case 8: |
| 672 | write32(&pmucru_ptr->pmucru_clksel[2], |
| 673 | PMU_I2C_CLK_REG_VALUE(8, src_clk_div)); |
| 674 | break; |
| 675 | default: |
| 676 | printk(BIOS_ERR, "do not support this i2c bus\n"); |
| 677 | } |
| 678 | } |
| 679 | |
| 680 | uint32_t rkclk_i2c_clock_for_bus(unsigned bus) |
| 681 | { |
| 682 | uint32_t freq = 198 * 1000 * 1000; |
| 683 | |
| 684 | rkclk_configure_i2c(bus, freq); |
| 685 | |
| 686 | return freq; |
| 687 | } |
Lin Huang | bf48fbb | 2016-03-23 19:24:53 +0800 | [diff] [blame] | 688 | |
Xing Zheng | 96fbc31 | 2016-05-19 11:39:20 +0800 | [diff] [blame] | 689 | static u32 clk_gcd(u32 a, u32 b) |
| 690 | { |
| 691 | while (b != 0) { |
| 692 | int r = b; |
| 693 | b = a % b; |
| 694 | a = r; |
| 695 | } |
| 696 | return a; |
| 697 | } |
| 698 | |
| 699 | void rkclk_configure_i2s(unsigned int hz) |
| 700 | { |
| 701 | int n, d; |
| 702 | int v; |
| 703 | |
| 704 | /** |
| 705 | * clk_i2s0_sel: divider ouput from fraction |
| 706 | * clk_i2s0_pll_sel source clock: cpll |
| 707 | * clk_i2s0_div_con: 1 (div+1) |
| 708 | */ |
| 709 | write32(&cru_ptr->clksel_con[28], |
| 710 | RK_CLRSETBITS(3 << 8 | 1 << 7 | 0x7f << 0, |
| 711 | 1 << 8 | 0 << 7 | 0 << 0)); |
| 712 | |
| 713 | /* make sure and enable i2s0 path gates */ |
| 714 | write32(&cru_ptr->clkgate_con[8], |
| 715 | RK_CLRBITS(1 << 12 | 1 << 5 | 1 << 4 | 1 << 3)); |
| 716 | |
| 717 | /* set frac divider */ |
| 718 | v = clk_gcd(CPLL_HZ, hz); |
| 719 | n = (CPLL_HZ / v) & (0xffff); |
| 720 | d = (hz / v) & (0xffff); |
| 721 | assert(hz == CPLL_HZ / n * d); |
| 722 | write32(&cru_ptr->clksel_con[96], d << 16 | n); |
| 723 | |
| 724 | /** |
| 725 | * clk_i2sout_sel clk_i2s |
| 726 | * clk_i2s_ch_sel: clk_i2s0 |
| 727 | */ |
| 728 | write32(&cru_ptr->clksel_con[31], |
| 729 | RK_CLRSETBITS(1 << 2 | 3 << 0, |
| 730 | 0 << 2 | 0 << 0)); |
| 731 | } |
| 732 | |
Lin Huang | bf48fbb | 2016-03-23 19:24:53 +0800 | [diff] [blame] | 733 | void rkclk_configure_saradc(unsigned int hz) |
| 734 | { |
| 735 | int src_clk_div; |
| 736 | |
| 737 | /* saradc src clk from 24MHz */ |
| 738 | src_clk_div = 24 * MHz / hz; |
| 739 | assert((src_clk_div - 1 < 255) && (src_clk_div * hz == 24 * MHz)); |
| 740 | |
| 741 | write32(&cru_ptr->clksel_con[26], |
| 742 | RK_CLRSETBITS(CLK_SARADC_DIV_CON_MASK << |
| 743 | CLK_SARADC_DIV_CON_SHIFT, |
| 744 | (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT)); |
| 745 | } |
Shunqian Zheng | c7f32a5 | 2016-05-04 15:54:37 +0800 | [diff] [blame] | 746 | |
| 747 | void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz) |
| 748 | { |
| 749 | u32 div; |
| 750 | void *reg_addr = vop_id ? &cru_ptr->clksel_con[48] : |
| 751 | &cru_ptr->clksel_con[47]; |
| 752 | |
| 753 | /* vop aclk source clk: cpll */ |
| 754 | div = CPLL_HZ / aclk_hz; |
| 755 | assert((div - 1 < 32) && (div * aclk_hz == CPLL_HZ)); |
| 756 | |
| 757 | write32(reg_addr, RK_CLRSETBITS( |
| 758 | ACLK_VOP_PLL_SEL_MASK << ACLK_VOP_PLL_SEL_SHIFT | |
| 759 | ACLK_VOP_DIV_CON_MASK << ACLK_VOP_DIV_CON_SHIFT, |
| 760 | ACLK_VOP_PLL_SEL_CPLL << ACLK_VOP_PLL_SEL_SHIFT | |
| 761 | (div - 1) << ACLK_VOP_DIV_CON_SHIFT)); |
| 762 | } |
| 763 | |
| 764 | int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz) |
| 765 | { |
| 766 | struct pll_div vpll_config = {0}; |
| 767 | void *reg_addr = vop_id ? &cru_ptr->clksel_con[50] : |
| 768 | &cru_ptr->clksel_con[49]; |
| 769 | |
| 770 | /* vop dclk source from vpll, and equals to vpll(means div == 1) */ |
| 771 | if (pll_para_config(dclk_hz, &vpll_config)) |
| 772 | return -1; |
| 773 | |
| 774 | rkclk_set_pll(&cru_ptr->vpll_con[0], &vpll_config); |
| 775 | |
| 776 | write32(reg_addr, RK_CLRSETBITS( |
| 777 | DCLK_VOP_DCLK_SEL_MASK << DCLK_VOP_DCLK_SEL_SHIFT | |
| 778 | DCLK_VOP_PLL_SEL_MASK << DCLK_VOP_PLL_SEL_SHIFT | |
| 779 | DCLK_VOP_DIV_CON_MASK << DCLK_VOP_DIV_CON_SHIFT, |
| 780 | DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT | |
| 781 | DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT | |
| 782 | (1 - 1) << DCLK_VOP_DIV_CON_SHIFT)); |
| 783 | |
| 784 | return 0; |
| 785 | } |
Shunqian Zheng | f4181ce | 2016-05-06 16:50:48 +0800 | [diff] [blame] | 786 | |
| 787 | void rkclk_configure_tsadc(unsigned int hz) |
| 788 | { |
| 789 | int src_clk_div; |
| 790 | |
| 791 | /* use 24M as src clock */ |
| 792 | src_clk_div = OSC_HZ / hz; |
| 793 | assert((src_clk_div - 1 < 1024) && (src_clk_div * hz == OSC_HZ)); |
| 794 | |
| 795 | write32(&cru_ptr->clksel_con[27], RK_CLRSETBITS( |
| 796 | CLK_TSADC_DIV_CON_MASK << CLK_TSADC_DIV_CON_SHIFT | |
| 797 | CLK_TSADC_SEL_MASK << CLK_TSADC_SEL_SHIFT, |
| 798 | src_clk_div << CLK_TSADC_DIV_CON_SHIFT | |
| 799 | CLK_TSADC_SEL_X24M << CLK_TSADC_SEL_SHIFT)); |
| 800 | } |
Lin Huang | 2f7ed8d | 2016-04-08 18:56:20 +0800 | [diff] [blame] | 801 | |
| 802 | void rkclk_configure_emmc(void) |
| 803 | { |
| 804 | int src_clk_div; |
| 805 | int aclk_emmc = 198*MHz; |
| 806 | int clk_emmc = 198*MHz; |
| 807 | |
| 808 | /* Select aclk_emmc source from GPLL */ |
| 809 | src_clk_div = GPLL_HZ / aclk_emmc; |
| 810 | assert((src_clk_div - 1 < 31) && (src_clk_div * aclk_emmc == GPLL_HZ)); |
| 811 | |
| 812 | write32(&cru_ptr->clksel_con[21], |
| 813 | RK_CLRSETBITS(ACLK_EMMC_PLL_SEL_MASK << |
| 814 | ACLK_EMMC_PLL_SEL_SHIFT | |
| 815 | ACLK_EMMC_DIV_CON_MASK << ACLK_EMMC_DIV_CON_SHIFT, |
| 816 | ACLK_EMMC_PLL_SEL_GPLL << |
| 817 | ACLK_EMMC_PLL_SEL_SHIFT | |
| 818 | (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT)); |
| 819 | |
| 820 | /* Select clk_emmc source from GPLL too */ |
| 821 | src_clk_div = GPLL_HZ / clk_emmc; |
| 822 | assert((src_clk_div - 1 < 127) && (src_clk_div * clk_emmc == GPLL_HZ)); |
| 823 | |
| 824 | write32(&cru_ptr->clksel_con[22], |
| 825 | RK_CLRSETBITS(CLK_EMMC_PLL_MASK << CLK_EMMC_PLL_SHIFT | |
| 826 | CLK_EMMC_DIV_CON_MASK << CLK_EMMC_DIV_CON_SHIFT, |
| 827 | CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT | |
| 828 | (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT)); |
| 829 | } |