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review.coreboot.org / coreboot / e32d3991d04e896bcb9fd8315bab68d54146e017 / . / src / mainboard / kontron / 986lcd-m / mptable.c
blob: ce7a6c5fc2b716b6c133ef153ca6e19acf35a9aa [file] [log] [blame]
Stefan Reinauer36a22682008-10-29 04:52:57 +0000[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2008 coresystems GmbH
5 *
Uwe Hermann2bb4acf2010-03-01 17:19:55 +0000[diff] [blame]6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
Stefan Reinauer36a22682008-10-29 04:52:57 +0000[diff] [blame]9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
Uwe Hermann2bb4acf2010-03-01 17:19:55 +0000[diff] [blame]17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Stefan Reinauer36a22682008-10-29 04:52:57 +0000[diff] [blame]18 */
19
20
21#include <device/device.h>
22#include <device/pci.h>
23#include <console/console.h>
24#include <arch/smp/mpspec.h>
25#include <string.h>
26#include <stdint.h>
27
Stefan Reinauerde3206a2010-02-22 06:09:43 +0000[diff] [blame]28static void *smp_write_config_table(void *v)
Stefan Reinauer36a22682008-10-29 04:52:57 +0000[diff] [blame]29{
30 static const char sig[4] = "PCMP";
31 static const char oem[8] = "COREBOOT";
32 static const char productid[12] = "986LCD-M ";
33 struct mp_config_table *mc;
Stefan Reinauer762a2302010-01-19 21:15:37 +0000[diff] [blame]34 struct device *riser = NULL, *firewire = NULL;
Patrick Georgiab272662010-06-25 13:43:22 +0000[diff] [blame]35 int firewire_bus = 0, riser_bus = 0, isa_bus;
Stefan Reinauerde3206a2010-02-22 06:09:43 +0000[diff] [blame]36 int ioapic_id;
Stefan Reinauer36a22682008-10-29 04:52:57 +0000[diff] [blame]37
38 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
39 memset(mc, 0, sizeof(*mc));
40
41 memcpy(mc->mpc_signature, sig, sizeof(sig));
42 mc->mpc_length = sizeof(*mc); /* initially just the header */
43 mc->mpc_spec = 0x04;
44 mc->mpc_checksum = 0; /* not yet computed */
45 memcpy(mc->mpc_oem, oem, sizeof(oem));
46 memcpy(mc->mpc_productid, productid, sizeof(productid));
47 mc->mpc_oemptr = 0;
48 mc->mpc_oemsize = 0;
49 mc->mpc_entry_count = 0; /* No entries yet... */
50 mc->mpc_lapic = LAPIC_ADDR;
51 mc->mpe_length = 0;
52 mc->mpe_checksum = 0;
53 mc->reserved = 0;
54
55 smp_write_processors(mc);
56
Stefan Reinauer762a2302010-01-19 21:15:37 +0000[diff] [blame]57 firewire = dev_find_device(0x104c, 0x8023, 0);
58 if (firewire) {
59 firewire_bus = firewire->bus->secondary;
Stefan Reinauer762a2302010-01-19 21:15:37 +0000[diff] [blame]60 }
61
62 // If a riser card is used, this riser is detected on bus 4, so its secondary bus is the
63 // highest bus number on the pci bus.
64 riser = dev_find_device(0x3388, 0x0021, 0);
65 if (!riser)
66 riser = dev_find_device(0x3388, 0x0022, 0);
67 if (riser) {
Myles Watson894a3472010-06-09 22:41:35 +0000[diff] [blame]68 riser_bus = riser->link_list->secondary;
Stefan Reinauer762a2302010-01-19 21:15:37 +0000[diff] [blame]69 }
Stefan Reinauer36a22682008-10-29 04:52:57 +0000[diff] [blame]70
Patrick Georgiab272662010-06-25 13:43:22 +0000[diff] [blame]71 mptable_write_buses(mc, NULL, &isa_bus);
Stefan Reinauer36a22682008-10-29 04:52:57 +0000[diff] [blame]72
73 /* I/O APICs: APIC ID Version State Address */
Stefan Reinauerde3206a2010-02-22 06:09:43 +0000[diff] [blame]74 ioapic_id = 2;
75 smp_write_ioapic(mc, ioapic_id, 0x20, 0xfec00000);
Stefan Reinauer36a22682008-10-29 04:52:57 +0000[diff] [blame]76
77 /* Legacy Interrupts */
Patrick Georgic5b87c82010-05-20 15:28:19 +0000[diff] [blame]78 mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0);
Stefan Reinauer36a22682008-10-29 04:52:57 +0000[diff] [blame]79
80 /* Builtin devices on Bus 0 */
Stefan Reinauerde3206a2010-02-22 06:09:43 +0000[diff] [blame]81 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x4, ioapic_id, 0x10);
82 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, ioapic_id, 0x10);
83 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, ioapic_id, 0x13);
84 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, ioapic_id, 0x17);
85 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, ioapic_id, 0x13);
86 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, ioapic_id, 0x12);
87 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, ioapic_id, 0x10);
88 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, ioapic_id, 0x10);
89 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, ioapic_id, 0x10);
90 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, ioapic_id, 0x11);
Stefan Reinauer36a22682008-10-29 04:52:57 +0000[diff] [blame]91
Stefan Reinauerde3206a2010-02-22 06:09:43 +0000[diff] [blame]92 /* Internal PCI bus (Firewire, PCI slot) */
Stefan Reinauer762a2302010-01-19 21:15:37 +0000[diff] [blame]93 if (firewire) {
Stefan Reinauerde3206a2010-02-22 06:09:43 +0000[diff] [blame]94 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, firewire_bus, 0x0, ioapic_id, 0x10);
95 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, firewire_bus, 0x4, ioapic_id, 0x14);
Stefan Reinauer762a2302010-01-19 21:15:37 +0000[diff] [blame]96 }
Stefan Reinauer36a22682008-10-29 04:52:57 +0000[diff] [blame]97
Stefan Reinauer762a2302010-01-19 21:15:37 +0000[diff] [blame]98 if (riser) {
99 /* Old riser card */
100 // riser slot top 5:8.0
Stefan Reinauerde3206a2010-02-22 06:09:43 +0000[diff] [blame]101 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x20, ioapic_id, 0x14);
Stefan Reinauer762a2302010-01-19 21:15:37 +0000[diff] [blame]102 // riser slot middle 5:9.0
Stefan Reinauerde3206a2010-02-22 06:09:43 +0000[diff] [blame]103 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x24, ioapic_id, 0x15);
Stefan Reinauer762a2302010-01-19 21:15:37 +0000[diff] [blame]104 // riser slot bottom 5:a.0
Stefan Reinauerde3206a2010-02-22 06:09:43 +0000[diff] [blame]105 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x28, ioapic_id, 0x16);
Stefan Reinauer36a22682008-10-29 04:52:57 +0000[diff] [blame]106
Stefan Reinauer762a2302010-01-19 21:15:37 +0000[diff] [blame]107 /* New Riser Card */
Stefan Reinauerde3206a2010-02-22 06:09:43 +0000[diff] [blame]108 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x30, ioapic_id, 0x14);
109 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x34, ioapic_id, 0x15);
110 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x38, ioapic_id, 0x16);
Stefan Reinauer762a2302010-01-19 21:15:37 +0000[diff] [blame]111 }
Stefan Reinauere1025d02009-03-11 15:20:36 +0000[diff] [blame]112
Stefan Reinauerde3206a2010-02-22 06:09:43 +0000[diff] [blame]113 /* PCIe slot */
114 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, ioapic_id, 0x10);
115 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1, ioapic_id, 0x11);
116
Stefan Reinauer36a22682008-10-29 04:52:57 +0000[diff] [blame]117 /* Onboard Ethernet */
Stefan Reinauerde3206a2010-02-22 06:09:43 +0000[diff] [blame]118 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x0, ioapic_id, 0x10);
Stefan Reinauer36a22682008-10-29 04:52:57 +0000[diff] [blame]119
120 /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
121 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0);
122 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1);
123
124 /* Compute the checksums */
125 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
126 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
127
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000[diff] [blame]128 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
Stefan Reinauer36a22682008-10-29 04:52:57 +0000[diff] [blame]129
130 return smp_next_mpe_entry(mc);
131}
132
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]133/* MP table generation in coreboot is not very well designed;
134 * One of the issues is that it knows nothing about Virtual
Stefan Reinauerde3206a2010-02-22 06:09:43 +0000[diff] [blame]135 * Wire mode, which everyone uses since a decade or so. This
136 * function fixes up our floating table. This spares us doing
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]137 * a half-baked fix of adding a new parameter to 200+ calls
Stefan Reinauerde3206a2010-02-22 06:09:43 +0000[diff] [blame]138 * to smp_write_floating_table()
139 */
140static void fixup_virtual_wire(void *v)
141{
142 struct intel_mp_floating *mf = v;
143
144 mf->mpf_checksum = 0;
145 mf->mpf_feature2 = MP_FEATURE_VIRTUALWIRE;
146 mf->mpf_checksum = smp_compute_checksum(mf, mf->mpf_length*16);
147}
148
Stefan Reinauer36a22682008-10-29 04:52:57 +0000[diff] [blame]149unsigned long write_smp_table(unsigned long addr)
150{
151 void *v;
152 v = smp_write_floating_table(addr);
Stefan Reinauerde3206a2010-02-22 06:09:43 +0000[diff] [blame]153 fixup_virtual_wire(v);
Stefan Reinauer36a22682008-10-29 04:52:57 +0000[diff] [blame]154 return (unsigned long)smp_write_config_table(v);
155}