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review.coreboot.org / coreboot / de3206a7bebce99f11e753164cc4d46357bba96a / . / src / mainboard / kontron / 986lcd-m / mptable.c
blob: 40cbd79f878b3d33284205e09fc52b5cc47f4372 [file] [log] [blame]
Stefan Reinauer36a22682008-10-29 04:52:57 +0000[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2008 coresystems GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
9 * the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
19 * MA 02110-1301 USA
20 */
21
22
23#include <device/device.h>
24#include <device/pci.h>
25#include <console/console.h>
26#include <arch/smp/mpspec.h>
27#include <string.h>
28#include <stdint.h>
29
Stefan Reinauerde3206a2010-02-22 06:09:43 +0000[diff] [blame^]30static void *smp_write_config_table(void *v)
Stefan Reinauer36a22682008-10-29 04:52:57 +0000[diff] [blame]31{
32 static const char sig[4] = "PCMP";
33 static const char oem[8] = "COREBOOT";
34 static const char productid[12] = "986LCD-M ";
35 struct mp_config_table *mc;
Stefan Reinauer762a2302010-01-19 21:15:37 +0000[diff] [blame]36 struct device *riser = NULL, *firewire = NULL;
Stefan Reinauer36a22682008-10-29 04:52:57 +0000[diff] [blame]37 int i;
Stefan Reinauer762a2302010-01-19 21:15:37 +0000[diff] [blame]38 int max_pci_bus, firewire_bus = 0, riser_bus = 0, isa_bus;
Stefan Reinauerde3206a2010-02-22 06:09:43 +0000[diff] [blame^]39 int ioapic_id;
Stefan Reinauer36a22682008-10-29 04:52:57 +0000[diff] [blame]40
41 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
42 memset(mc, 0, sizeof(*mc));
43
44 memcpy(mc->mpc_signature, sig, sizeof(sig));
45 mc->mpc_length = sizeof(*mc); /* initially just the header */
46 mc->mpc_spec = 0x04;
47 mc->mpc_checksum = 0; /* not yet computed */
48 memcpy(mc->mpc_oem, oem, sizeof(oem));
49 memcpy(mc->mpc_productid, productid, sizeof(productid));
50 mc->mpc_oemptr = 0;
51 mc->mpc_oemsize = 0;
52 mc->mpc_entry_count = 0; /* No entries yet... */
53 mc->mpc_lapic = LAPIC_ADDR;
54 mc->mpe_length = 0;
55 mc->mpe_checksum = 0;
56 mc->reserved = 0;
57
58 smp_write_processors(mc);
Stefan Reinauer762a2302010-01-19 21:15:37 +0000[diff] [blame]59 max_pci_bus=0;
Stefan Reinauer36a22682008-10-29 04:52:57 +0000[diff] [blame]60
Stefan Reinauer762a2302010-01-19 21:15:37 +0000[diff] [blame]61 firewire = dev_find_device(0x104c, 0x8023, 0);
62 if (firewire) {
63 firewire_bus = firewire->bus->secondary;
64 printk_spew("Firewire device is on bus %x\n",
65 firewire_bus);
66 max_pci_bus = firewire_bus;
67 }
68
69 // If a riser card is used, this riser is detected on bus 4, so its secondary bus is the
70 // highest bus number on the pci bus.
71 riser = dev_find_device(0x3388, 0x0021, 0);
72 if (!riser)
73 riser = dev_find_device(0x3388, 0x0022, 0);
74 if (riser) {
75 riser_bus = riser->link[0].secondary;
76 printk_spew("Riser bus is %x\n", riser_bus);
77 max_pci_bus = riser_bus;
78 }
Stefan Reinauer36a22682008-10-29 04:52:57 +0000[diff] [blame]79
80 /* ISA bus follows */
81 isa_bus = max_pci_bus + 1;
82
83 /* Bus: Bus ID Type */
84 for (i=0; i <= max_pci_bus; i++)
85 smp_write_bus(mc, i, "PCI ");
86
87 smp_write_bus(mc, isa_bus, "ISA ");
88
89 /* I/O APICs: APIC ID Version State Address */
Stefan Reinauerde3206a2010-02-22 06:09:43 +0000[diff] [blame^]90 ioapic_id = 2;
91 smp_write_ioapic(mc, ioapic_id, 0x20, 0xfec00000);
Stefan Reinauer36a22682008-10-29 04:52:57 +0000[diff] [blame]92
93 /* Legacy Interrupts */
94
95 /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
Stefan Reinauerde3206a2010-02-22 06:09:43 +0000[diff] [blame^]96 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, ioapic_id, 0x0);
97 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x1, ioapic_id, 0x1);
98 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, ioapic_id, 0x2);
99 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x3, ioapic_id, 0x3);
100 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x4, ioapic_id, 0x4);
101 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x8, ioapic_id, 0x8);
102 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x9, ioapic_id, 0x9);
103 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xa, ioapic_id, 0xa);
104 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xb, ioapic_id, 0xb);
105 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xc, ioapic_id, 0xc);
106 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xd, ioapic_id, 0xd);
107 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xe, ioapic_id, 0xe);
108 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xf, ioapic_id, 0xf);
Stefan Reinauer36a22682008-10-29 04:52:57 +0000[diff] [blame]109
110 /* Builtin devices on Bus 0 */
Stefan Reinauerde3206a2010-02-22 06:09:43 +0000[diff] [blame^]111 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x4, ioapic_id, 0x10);
112 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, ioapic_id, 0x10);
113 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, ioapic_id, 0x13);
114 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, ioapic_id, 0x17);
115 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, ioapic_id, 0x13);
116 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, ioapic_id, 0x12);
117 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, ioapic_id, 0x10);
118 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, ioapic_id, 0x10);
119 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, ioapic_id, 0x10);
120 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, ioapic_id, 0x11);
Stefan Reinauer36a22682008-10-29 04:52:57 +0000[diff] [blame]121
Stefan Reinauerde3206a2010-02-22 06:09:43 +0000[diff] [blame^]122 /* Internal PCI bus (Firewire, PCI slot) */
Stefan Reinauer762a2302010-01-19 21:15:37 +0000[diff] [blame]123 if (firewire) {
Stefan Reinauerde3206a2010-02-22 06:09:43 +0000[diff] [blame^]124 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, firewire_bus, 0x0, ioapic_id, 0x10);
125 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, firewire_bus, 0x4, ioapic_id, 0x14);
Stefan Reinauer762a2302010-01-19 21:15:37 +0000[diff] [blame]126 }
Stefan Reinauer36a22682008-10-29 04:52:57 +0000[diff] [blame]127
Stefan Reinauer762a2302010-01-19 21:15:37 +0000[diff] [blame]128 if (riser) {
129 /* Old riser card */
130 // riser slot top 5:8.0
Stefan Reinauerde3206a2010-02-22 06:09:43 +0000[diff] [blame^]131 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x20, ioapic_id, 0x14);
Stefan Reinauer762a2302010-01-19 21:15:37 +0000[diff] [blame]132 // riser slot middle 5:9.0
Stefan Reinauerde3206a2010-02-22 06:09:43 +0000[diff] [blame^]133 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x24, ioapic_id, 0x15);
Stefan Reinauer762a2302010-01-19 21:15:37 +0000[diff] [blame]134 // riser slot bottom 5:a.0
Stefan Reinauerde3206a2010-02-22 06:09:43 +0000[diff] [blame^]135 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x28, ioapic_id, 0x16);
Stefan Reinauer36a22682008-10-29 04:52:57 +0000[diff] [blame]136
Stefan Reinauer762a2302010-01-19 21:15:37 +0000[diff] [blame]137 /* New Riser Card */
Stefan Reinauerde3206a2010-02-22 06:09:43 +0000[diff] [blame^]138 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x30, ioapic_id, 0x14);
139 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x34, ioapic_id, 0x15);
140 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x38, ioapic_id, 0x16);
Stefan Reinauer762a2302010-01-19 21:15:37 +0000[diff] [blame]141 }
Stefan Reinauere1025d02009-03-11 15:20:36 +0000[diff] [blame]142
Stefan Reinauerde3206a2010-02-22 06:09:43 +0000[diff] [blame^]143 /* PCIe slot */
144 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, ioapic_id, 0x10);
145 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1, ioapic_id, 0x11);
146
Stefan Reinauer36a22682008-10-29 04:52:57 +0000[diff] [blame]147 /* Onboard Ethernet */
Stefan Reinauerde3206a2010-02-22 06:09:43 +0000[diff] [blame^]148 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x0, ioapic_id, 0x10);
Stefan Reinauer36a22682008-10-29 04:52:57 +0000[diff] [blame]149
150 /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
151 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0);
152 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1);
153
154 /* Compute the checksums */
155 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
156 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
157
158 printk_debug("Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
159
160 return smp_next_mpe_entry(mc);
161}
162
Stefan Reinauerde3206a2010-02-22 06:09:43 +0000[diff] [blame^]163/* MP table generation in coreboot is not very well designed;
164 * One of the issues is that it knows nothing about Virtual
165 * Wire mode, which everyone uses since a decade or so. This
166 * function fixes up our floating table. This spares us doing
167 * a half-baked fix of adding a new parameter to 200+ calls
168 * to smp_write_floating_table()
169 */
170static void fixup_virtual_wire(void *v)
171{
172 struct intel_mp_floating *mf = v;
173
174 mf->mpf_checksum = 0;
175 mf->mpf_feature2 = MP_FEATURE_VIRTUALWIRE;
176 mf->mpf_checksum = smp_compute_checksum(mf, mf->mpf_length*16);
177}
178
Stefan Reinauer36a22682008-10-29 04:52:57 +0000[diff] [blame]179unsigned long write_smp_table(unsigned long addr)
180{
181 void *v;
182 v = smp_write_floating_table(addr);
Stefan Reinauerde3206a2010-02-22 06:09:43 +0000[diff] [blame^]183 fixup_virtual_wire(v);
Stefan Reinauer36a22682008-10-29 04:52:57 +0000[diff] [blame]184 return (unsigned long)smp_write_config_table(v);
185}