| Elyes HAOUAS | 36787b0 | 2020-05-07 12:07:24 +0200 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
| Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 2 | |
| Kyösti Mälkki | e4c17ce | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 3 | config NORTHBRIDGE_AMD_PI |
| Martin Roth | 595e777 | 2015-04-26 18:53:26 -0600 | [diff] [blame] | 4 | bool |
| Marc Jones | 21cde8b | 2017-05-07 16:47:36 -0600 | [diff] [blame] | 5 | default y if CPU_AMD_PI |
| Marc Jones | 21cde8b | 2017-05-07 16:47:36 -0600 | [diff] [blame] | 6 | default n |
| Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 7 | |
| Kyösti Mälkki | e4c17ce | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 8 | if NORTHBRIDGE_AMD_PI |
| 9 | |
| Ricardo Ribalda Delgado | a132892 | 2016-12-28 15:16:22 +0100 | [diff] [blame] | 10 | config BOTTOMIO_POSITION |
| 11 | hex "Bottom of 32-bit IO space" |
| 12 | default 0xD0000000 |
| 13 | help |
| 14 | If PCI peripherals with big BARs are connected to the system |
| 15 | the bottom of the IO must be decreased to allocate such |
| 16 | devices. |
| 17 | |
| 18 | Declare the beginning of the 128MB-aligned MMIO region. This |
| 19 | option is useful when PCI peripherals requesting large address |
| 20 | ranges are present. |
| 21 | |
| Kyösti Mälkki | e4c17ce | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 22 | config S3_VGA_ROM_RUN |
| 23 | bool |
| 24 | default n |
| 25 | |
| Patrick Georgi | 0bb8346 | 2019-11-22 20:58:58 +0100 | [diff] [blame] | 26 | source "src/northbridge/amd/pi/00730F01/Kconfig" |
| Kyösti Mälkki | e4c17ce | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 27 | |
| Patrick Georgi | acbc491 | 2023-11-06 17:22:34 +0000 | [diff] [blame] | 28 | config HEAP_SIZE |
| 29 | hex |
| 30 | default 0xc0000 |
| 31 | |
| Kyösti Mälkki | e4c17ce | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 32 | endif # NORTHBRIDGE_AMD_PI |