Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1 | # |
| 2 | # This file is part of the coreboot project. |
| 3 | # |
Marc Jones | aa31f99 | 2016-09-20 20:30:17 -0600 | [diff] [blame] | 4 | # Copyright (C) 2011 - 2016 Advanced Micro Devices, Inc. |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 5 | # |
| 6 | # This program is free software; you can redistribute it and/or modify |
| 7 | # it under the terms of the GNU General Public License as published by |
| 8 | # the Free Software Foundation; version 2 of the License. |
| 9 | # |
| 10 | # This program is distributed in the hope that it will be useful, |
| 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | # GNU General Public License for more details. |
| 14 | # |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 15 | |
Kyösti Mälkki | e4c17ce | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 16 | config NORTHBRIDGE_AMD_PI |
Martin Roth | 595e777 | 2015-04-26 18:53:26 -0600 | [diff] [blame] | 17 | bool |
Marc Jones | 21cde8b | 2017-05-07 16:47:36 -0600 | [diff] [blame] | 18 | default y if CPU_AMD_PI |
Marc Jones | 21cde8b | 2017-05-07 16:47:36 -0600 | [diff] [blame] | 19 | default n |
Kyösti Mälkki | 6e37b0a | 2017-04-17 06:45:56 +0300 | [diff] [blame] | 20 | select CBMEM_TOP_BACKUP |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 21 | |
Kyösti Mälkki | e4c17ce | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 22 | if NORTHBRIDGE_AMD_PI |
| 23 | |
Ricardo Ribalda Delgado | a132892 | 2016-12-28 15:16:22 +0100 | [diff] [blame] | 24 | config BOTTOMIO_POSITION |
| 25 | hex "Bottom of 32-bit IO space" |
| 26 | default 0xD0000000 |
| 27 | help |
| 28 | If PCI peripherals with big BARs are connected to the system |
| 29 | the bottom of the IO must be decreased to allocate such |
| 30 | devices. |
| 31 | |
| 32 | Declare the beginning of the 128MB-aligned MMIO region. This |
| 33 | option is useful when PCI peripherals requesting large address |
| 34 | ranges are present. |
| 35 | |
Kyösti Mälkki | e4c17ce | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 36 | config CONSOLE_VGA_MULTI |
| 37 | bool |
| 38 | default n |
| 39 | |
| 40 | config S3_VGA_ROM_RUN |
| 41 | bool |
| 42 | default n |
| 43 | |
Patrick Georgi | 0bb8346 | 2019-11-22 20:58:58 +0100 | [diff] [blame^] | 44 | source "src/northbridge/amd/pi/00630F01/Kconfig" |
| 45 | source "src/northbridge/amd/pi/00730F01/Kconfig" |
| 46 | source "src/northbridge/amd/pi/00660F01/Kconfig" |
Kyösti Mälkki | e4c17ce | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 47 | |
WANG Siyuan | 2dcd0fc | 2015-06-02 16:25:58 +0800 | [diff] [blame] | 48 | config HW_MEM_HOLE_SIZEK |
| 49 | hex |
| 50 | default 0x200000 |
| 51 | |
WANG Siyuan | 2dcd0fc | 2015-06-02 16:25:58 +0800 | [diff] [blame] | 52 | config HEAP_SIZE |
| 53 | hex |
| 54 | default 0xc0000 |
| 55 | |
Kyösti Mälkki | e4c17ce | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 56 | endif # NORTHBRIDGE_AMD_PI |