Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2010 Google Inc. |
| 5 | ## |
| 6 | ## This program is free software; you can redistribute it and/or modify |
| 7 | ## it under the terms of the GNU General Public License as published by |
| 8 | ## the Free Software Foundation; version 2 of the License. |
| 9 | ## |
| 10 | ## This program is distributed in the hope that it will be useful, |
| 11 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | ## GNU General Public License for more details. |
| 14 | ## |
| 15 | ## You should have received a copy of the GNU General Public License |
| 16 | ## along with this program; if not, write to the Free Software |
Patrick Georgi | b890a12 | 2015-03-26 15:17:45 +0100 | [diff] [blame] | 17 | ## Foundation, Inc. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 18 | ## |
| 19 | |
| 20 | config NORTHBRIDGE_INTEL_HASWELL |
| 21 | bool |
| 22 | select CACHE_MRC_BIN |
| 23 | select CPU_INTEL_HASWELL |
| 24 | select REQUIRES_BLOB |
Kyösti Mälkki | 15c4ab7 | 2013-07-02 11:37:35 +0300 | [diff] [blame] | 25 | select MMCONF_SUPPORT |
Aaron Durbin | 6d04f0f | 2012-10-31 22:57:16 -0500 | [diff] [blame] | 26 | select MMCONF_SUPPORT_DEFAULT |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 27 | select INTEL_DDI |
| 28 | select INTEL_DP |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 29 | |
| 30 | if NORTHBRIDGE_INTEL_HASWELL |
| 31 | |
Aaron Durbin | 6d04f0f | 2012-10-31 22:57:16 -0500 | [diff] [blame] | 32 | config BOOTBLOCK_NORTHBRIDGE_INIT |
| 33 | string |
| 34 | default "northbridge/intel/haswell/bootblock.c" |
| 35 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 36 | config VGA_BIOS_ID |
| 37 | string |
| 38 | default "8086,0166" |
| 39 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 40 | config CACHE_MRC_SIZE_KB |
| 41 | int |
| 42 | default 512 |
| 43 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 44 | config MRC_CACHE_SIZE |
| 45 | hex |
| 46 | depends on !CHROMEOS |
| 47 | default 0x10000 |
| 48 | |
| 49 | config DCACHE_RAM_BASE |
| 50 | hex |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 51 | default 0xff7c0000 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 52 | |
| 53 | config DCACHE_RAM_SIZE |
| 54 | hex |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 55 | default 0x10000 |
| 56 | help |
| 57 | The size of the cache-as-ram region required during bootblock |
| 58 | and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE |
| 59 | must add up to a power of 2. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 60 | |
| 61 | config DCACHE_RAM_MRC_VAR_SIZE |
| 62 | hex |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 63 | default 0x30000 |
| 64 | help |
| 65 | The amount of cache-as-ram region required by the reference code. |
| 66 | |
| 67 | config DCACHE_RAM_ROMSTAGE_STACK_SIZE |
| 68 | hex |
| 69 | default 0x2000 |
| 70 | help |
| 71 | The amount of anticipated stack usage from the data cache |
| 72 | during pre-ram rom stage execution. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 73 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 74 | config HAVE_MRC |
| 75 | bool "Add a System Agent binary" |
| 76 | help |
| 77 | Select this option to add a System Agent binary to |
| 78 | the resulting coreboot image. |
| 79 | |
| 80 | Note: Without this binary coreboot will not work |
| 81 | |
| 82 | config MRC_FILE |
| 83 | string "Intel System Agent path and filename" |
| 84 | depends on HAVE_MRC |
| 85 | default "mrc.bin" |
| 86 | help |
| 87 | The path and filename of the file to use as System Agent |
| 88 | binary. |
| 89 | |
| 90 | config CBFS_SIZE |
| 91 | hex "Size of CBFS filesystem in ROM" |
| 92 | default 0x100000 |
| 93 | help |
| 94 | On Haswell systems the firmware image has to store a lot more |
| 95 | than just coreboot, including: |
| 96 | - a firmware descriptor |
| 97 | - Intel Management Engine firmware |
| 98 | - MRC cache information |
| 99 | This option allows to limit the size of the CBFS portion in the |
| 100 | firmware image. |
| 101 | |
Stefan Reinauer | f1aabec | 2014-01-22 15:16:30 -0800 | [diff] [blame] | 102 | config PRE_GRAPHICS_DELAY |
Stefan Reinauer | 7034b9e | 2014-02-11 16:18:07 -0800 | [diff] [blame] | 103 | int "Graphics initialization delay in ms" |
Stefan Reinauer | f1aabec | 2014-01-22 15:16:30 -0800 | [diff] [blame] | 104 | default 0 |
| 105 | help |
| 106 | On some systems, coreboot boots so fast that connected monitors |
| 107 | (mostly TVs) won't be able to wake up fast enough to talk to the |
| 108 | VBIOS. On those systems we need to wait for a bit before executing |
| 109 | the VBIOS. |
| 110 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 111 | endif |