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Aaron Durbin76c37002012-10-30 09:03:43 -05001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2010 Google Inc.
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
15## You should have received a copy of the GNU General Public License
16## along with this program; if not, write to the Free Software
Patrick Georgib890a122015-03-26 15:17:45 +010017## Foundation, Inc.
Aaron Durbin76c37002012-10-30 09:03:43 -050018##
19
20config NORTHBRIDGE_INTEL_HASWELL
21 bool
22 select CACHE_MRC_BIN
23 select CPU_INTEL_HASWELL
24 select REQUIRES_BLOB
Kyösti Mälkki15c4ab72013-07-02 11:37:35 +030025 select MMCONF_SUPPORT
Aaron Durbin6d04f0f2012-10-31 22:57:16 -050026 select MMCONF_SUPPORT_DEFAULT
Furquan Shaikh77f48cd2013-08-19 10:16:50 -070027 select INTEL_DDI
28 select INTEL_DP
Aaron Durbin76c37002012-10-30 09:03:43 -050029
30if NORTHBRIDGE_INTEL_HASWELL
31
Aaron Durbin6d04f0f2012-10-31 22:57:16 -050032config BOOTBLOCK_NORTHBRIDGE_INIT
33 string
34 default "northbridge/intel/haswell/bootblock.c"
35
Aaron Durbin76c37002012-10-30 09:03:43 -050036config VGA_BIOS_ID
37 string
38 default "8086,0166"
39
Aaron Durbin76c37002012-10-30 09:03:43 -050040config CACHE_MRC_SIZE_KB
41 int
42 default 512
43
Aaron Durbin76c37002012-10-30 09:03:43 -050044config MRC_CACHE_SIZE
45 hex
46 depends on !CHROMEOS
47 default 0x10000
48
49config DCACHE_RAM_BASE
50 hex
Aaron Durbin3d0071b2013-01-18 14:32:50 -060051 default 0xff7c0000
Aaron Durbin76c37002012-10-30 09:03:43 -050052
53config DCACHE_RAM_SIZE
54 hex
Aaron Durbin3d0071b2013-01-18 14:32:50 -060055 default 0x10000
56 help
57 The size of the cache-as-ram region required during bootblock
58 and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
59 must add up to a power of 2.
Aaron Durbin76c37002012-10-30 09:03:43 -050060
61config DCACHE_RAM_MRC_VAR_SIZE
62 hex
Aaron Durbin3d0071b2013-01-18 14:32:50 -060063 default 0x30000
64 help
65 The amount of cache-as-ram region required by the reference code.
66
67config DCACHE_RAM_ROMSTAGE_STACK_SIZE
68 hex
69 default 0x2000
70 help
71 The amount of anticipated stack usage from the data cache
72 during pre-ram rom stage execution.
Aaron Durbin76c37002012-10-30 09:03:43 -050073
Aaron Durbin76c37002012-10-30 09:03:43 -050074config HAVE_MRC
75 bool "Add a System Agent binary"
76 help
77 Select this option to add a System Agent binary to
78 the resulting coreboot image.
79
80 Note: Without this binary coreboot will not work
81
82config MRC_FILE
83 string "Intel System Agent path and filename"
84 depends on HAVE_MRC
85 default "mrc.bin"
86 help
87 The path and filename of the file to use as System Agent
88 binary.
89
90config CBFS_SIZE
91 hex "Size of CBFS filesystem in ROM"
92 default 0x100000
93 help
94 On Haswell systems the firmware image has to store a lot more
95 than just coreboot, including:
96 - a firmware descriptor
97 - Intel Management Engine firmware
98 - MRC cache information
99 This option allows to limit the size of the CBFS portion in the
100 firmware image.
101
Stefan Reinauerf1aabec2014-01-22 15:16:30 -0800102config PRE_GRAPHICS_DELAY
Stefan Reinauer7034b9e2014-02-11 16:18:07 -0800103 int "Graphics initialization delay in ms"
Stefan Reinauerf1aabec2014-01-22 15:16:30 -0800104 default 0
105 help
106 On some systems, coreboot boots so fast that connected monitors
107 (mostly TVs) won't be able to wake up fast enough to talk to the
108 VBIOS. On those systems we need to wait for a bit before executing
109 the VBIOS.
110
Aaron Durbin76c37002012-10-30 09:03:43 -0500111endif