Patrick Georgi | c49d7a3 | 2020-05-08 22:50:46 +0200 | [diff] [blame] | 1 | ## SPDX-License-Identifier: GPL-2.0-only |
Teo Boon Tiong | 4dee7b5 | 2017-09-07 00:48:55 +0800 | [diff] [blame] | 2 | |
| 3 | chip soc/intel/skylake |
| 4 | |
Teo Boon Tiong | 4dee7b5 | 2017-09-07 00:48:55 +0800 | [diff] [blame] | 5 | register "deep_s5_enable_ac" = "0" |
| 6 | register "deep_s5_enable_dc" = "0" |
| 7 | register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" |
| 8 | |
| 9 | # GPE configuration |
| 10 | # Note that GPE events called out in ASL code rely on this |
| 11 | # route. i.e. If this route changes then the affected GPE |
| 12 | # offset bits also need to be changed. |
| 13 | register "gpe0_dw0" = "GPP_B" |
| 14 | register "gpe0_dw1" = "GPP_D" |
| 15 | register "gpe0_dw2" = "GPP_E" |
| 16 | |
Teo Boon Tiong | 4dee7b5 | 2017-09-07 00:48:55 +0800 | [diff] [blame] | 17 | # FSP Configuration |
Teo Boon Tiong | 4dee7b5 | 2017-09-07 00:48:55 +0800 | [diff] [blame] | 18 | register "DspEnable" = "1" |
| 19 | register "IoBufferOwnership" = "3" |
Teo Boon Tiong | 4dee7b5 | 2017-09-07 00:48:55 +0800 | [diff] [blame] | 20 | register "SkipExtGfxScan" = "1" |
Teo Boon Tiong | 4dee7b5 | 2017-09-07 00:48:55 +0800 | [diff] [blame] | 21 | |
Teo Boon Tiong | 4dee7b5 | 2017-09-07 00:48:55 +0800 | [diff] [blame] | 22 | # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch |
| 23 | # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s |
| 24 | register "PmConfigSlpS3MinAssert" = "0x02" |
| 25 | |
| 26 | # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s |
| 27 | register "PmConfigSlpS4MinAssert" = "0x04" |
| 28 | |
| 29 | # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s |
| 30 | register "PmConfigSlpSusMinAssert" = "0x03" |
| 31 | |
| 32 | # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s |
| 33 | register "PmConfigSlpAMinAssert" = "0x03" |
| 34 | |
Nico Huber | 44e89af | 2019-02-23 19:24:51 +0100 | [diff] [blame] | 35 | register "serirq_mode" = "SERIRQ_CONTINUOUS" |
Teo Boon Tiong | 4dee7b5 | 2017-09-07 00:48:55 +0800 | [diff] [blame] | 36 | |
Michael Niewöhner | 5e779f9 | 2019-10-09 21:02:36 +0200 | [diff] [blame] | 37 | # VR Settings Configuration for 4 Domains |
| 38 | #+----------------+-----------+-----------+-------------+----------+ |
| 39 | #| Domain/Setting | SA | IA | GT Unsliced | GT | |
| 40 | #+----------------+-----------+-----------+-------------+----------+ |
| 41 | #| Psi1Threshold | 20A | 20A | 20A | 20A | |
| 42 | #| Psi2Threshold | 4A | 5A | 5A | 5A | |
| 43 | #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| 44 | #| Psi3Enable | 1 | 1 | 1 | 1 | |
| 45 | #| Psi4Enable | 1 | 1 | 1 | 1 | |
| 46 | #| ImonSlope | 0 | 0 | 0 | 0 | |
| 47 | #| ImonOffset | 0 | 0 | 0 | 0 | |
| 48 | #| IccMax | 7A | 34A | 35A | 35A | |
| 49 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
| 50 | #+----------------+-----------+-----------+-------------+----------+ |
Teo Boon Tiong | 4dee7b5 | 2017-09-07 00:48:55 +0800 | [diff] [blame] | 51 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
Michael Niewöhner | 5e779f9 | 2019-10-09 21:02:36 +0200 | [diff] [blame] | 52 | .vr_config_enable = 1, |
| 53 | .psi1threshold = VR_CFG_AMP(20), |
| 54 | .psi2threshold = VR_CFG_AMP(4), |
| 55 | .psi3threshold = VR_CFG_AMP(1), |
| 56 | .psi3enable = 1, |
| 57 | .psi4enable = 1, |
| 58 | .imon_slope = 0x0, |
| 59 | .imon_offset = 0x0, |
| 60 | .icc_max = VR_CFG_AMP(7), |
| 61 | .voltage_limit = 1520, |
Teo Boon Tiong | 4dee7b5 | 2017-09-07 00:48:55 +0800 | [diff] [blame] | 62 | }" |
| 63 | |
| 64 | register "domain_vr_config[VR_IA_CORE]" = "{ |
Michael Niewöhner | 5e779f9 | 2019-10-09 21:02:36 +0200 | [diff] [blame] | 65 | .vr_config_enable = 1, |
| 66 | .psi1threshold = VR_CFG_AMP(20), |
| 67 | .psi2threshold = VR_CFG_AMP(5), |
| 68 | .psi3threshold = VR_CFG_AMP(1), |
| 69 | .psi3enable = 1, |
| 70 | .psi4enable = 1, |
| 71 | .imon_slope = 0x0, |
| 72 | .imon_offset = 0x0, |
| 73 | .icc_max = VR_CFG_AMP(34), |
| 74 | .voltage_limit = 1520, |
Teo Boon Tiong | 4dee7b5 | 2017-09-07 00:48:55 +0800 | [diff] [blame] | 75 | }" |
| 76 | |
| 77 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
Michael Niewöhner | 5e779f9 | 2019-10-09 21:02:36 +0200 | [diff] [blame] | 78 | .vr_config_enable = 1, |
| 79 | .psi1threshold = VR_CFG_AMP(20), |
| 80 | .psi2threshold = VR_CFG_AMP(5), |
| 81 | .psi3threshold = VR_CFG_AMP(1), |
| 82 | .psi3enable = 1, |
| 83 | .psi4enable = 1, |
| 84 | .imon_slope = 0x0, |
| 85 | .imon_offset = 0x0, |
| 86 | .icc_max = VR_CFG_AMP(35), |
| 87 | .voltage_limit = 1520, |
Teo Boon Tiong | 4dee7b5 | 2017-09-07 00:48:55 +0800 | [diff] [blame] | 88 | }" |
| 89 | |
| 90 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
Michael Niewöhner | 5e779f9 | 2019-10-09 21:02:36 +0200 | [diff] [blame] | 91 | .vr_config_enable = 1, |
| 92 | .psi1threshold = VR_CFG_AMP(20), |
| 93 | .psi2threshold = VR_CFG_AMP(5), |
| 94 | .psi3threshold = VR_CFG_AMP(1), |
| 95 | .psi3enable = 1, |
| 96 | .psi4enable = 1, |
| 97 | .imon_slope = 0x0, |
| 98 | .imon_offset = 0x0, |
| 99 | .icc_max = VR_CFG_AMP(35), |
| 100 | .voltage_limit = 1520, |
Teo Boon Tiong | 4dee7b5 | 2017-09-07 00:48:55 +0800 | [diff] [blame] | 101 | }" |
| 102 | |
Teo Boon Tiong | 4dee7b5 | 2017-09-07 00:48:55 +0800 | [diff] [blame] | 103 | # Enable x1 slot |
| 104 | register "PcieRpEnable[7]" = "1" |
| 105 | register "PcieRpClkReqSupport[7]" = "1" |
| 106 | register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3 |
| 107 | |
| 108 | # Enable x4 slot |
| 109 | register "PcieRpEnable[8]" = "1" |
| 110 | register "PcieRpClkReqSupport[8]" = "1" |
| 111 | register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4 |
| 112 | |
| 113 | # Enable Root port 6 and 13. |
| 114 | register "PcieRpEnable[5]" = "1" |
| 115 | register "PcieRpEnable[12]" = "1" |
| 116 | |
| 117 | # Enable CLKREQ# |
| 118 | register "PcieRpClkReqSupport[5]" = "1" |
| 119 | register "PcieRpClkReqSupport[12]" = "1" |
| 120 | |
| 121 | # RP 6 uses SRCCLKREQ1# while RP `3 uses SRCCLKREQ2# |
| 122 | register "PcieRpClkReqNumber[5]" = "0" |
| 123 | register "PcieRpClkReqNumber[12]" = "1" |
| 124 | |
Teo Boon Tiong | 4dee7b5 | 2017-09-07 00:48:55 +0800 | [diff] [blame] | 125 | # USB related |
| 126 | register "SsicPortEnable" = "1" |
Teo Boon Tiong | 4dee7b5 | 2017-09-07 00:48:55 +0800 | [diff] [blame] | 127 | |
Teo Boon Tiong | 4dee7b5 | 2017-09-07 00:48:55 +0800 | [diff] [blame] | 128 | |
| 129 | register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V |
| 130 | |
| 131 | # Must leave UART0 enabled or SD/eMMC will not work as PCI |
| 132 | |
Teo Boon Tiong | 4dee7b5 | 2017-09-07 00:48:55 +0800 | [diff] [blame] | 133 | register "SataSalpSupport" = "1" |
Felix Singer | 21b5a9a | 2023-10-23 07:26:28 +0200 | [diff] [blame] | 134 | register "SataPortsEnable" = "{ |
| 135 | [0] = 1, |
| 136 | [1] = 1, |
| 137 | [2] = 1, |
| 138 | [3] = 1, |
| 139 | [4] = 1, |
| 140 | [5] = 1, |
| 141 | [6] = 1, |
| 142 | [7] = 1, |
Teo Boon Tiong | 4dee7b5 | 2017-09-07 00:48:55 +0800 | [diff] [blame] | 143 | }" |
Felix Singer | 21b5a9a | 2023-10-23 07:26:28 +0200 | [diff] [blame] | 144 | register "SerialIoDevMode" = "{ |
| 145 | [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| 146 | [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| 147 | [PchSerialIoIndexI2C2] = PchSerialIoPci, |
| 148 | [PchSerialIoIndexI2C3] = PchSerialIoPci, |
| 149 | [PchSerialIoIndexI2C4] = PchSerialIoPci, |
| 150 | [PchSerialIoIndexI2C5] = PchSerialIoPci, |
| 151 | [PchSerialIoIndexSpi0] = PchSerialIoPci, |
| 152 | [PchSerialIoIndexSpi1] = PchSerialIoPci, |
| 153 | [PchSerialIoIndexUart0] = PchSerialIoPci, |
| 154 | [PchSerialIoIndexUart1] = PchSerialIoPci, |
| 155 | [PchSerialIoIndexUart2] = PchSerialIoSkipInit, |
Teo Boon Tiong | 4dee7b5 | 2017-09-07 00:48:55 +0800 | [diff] [blame] | 156 | }" |
| 157 | |
| 158 | # PL2 override 25W |
Sumeet R Pawnikar | 97c5464 | 2020-05-10 01:24:11 +0530 | [diff] [blame] | 159 | register "power_limits_config" = "{ |
| 160 | .tdp_pl2_override = 25, |
| 161 | }" |
Teo Boon Tiong | 4dee7b5 | 2017-09-07 00:48:55 +0800 | [diff] [blame] | 162 | |
| 163 | # Send an extra VR mailbox command for the PS4 exit issue |
| 164 | register "SendVrMbxCmd" = "2" |
| 165 | |
Teo Boon Tiong | 4dee7b5 | 2017-09-07 00:48:55 +0800 | [diff] [blame] | 166 | # Use default SD card detect GPIO configuration |
Angel Pons | 6bd99f9 | 2021-02-20 00:16:47 +0100 | [diff] [blame] | 167 | #register "sdcard_cd_gpio" = "GPP_A7" |
Teo Boon Tiong | 4dee7b5 | 2017-09-07 00:48:55 +0800 | [diff] [blame] | 168 | |
Teo Boon Tiong | 4dee7b5 | 2017-09-07 00:48:55 +0800 | [diff] [blame] | 169 | device domain 0 on |
Felix Singer | dada017 | 2023-11-12 18:10:12 +0000 | [diff] [blame] | 170 | device ref igpu on end |
Felix Singer | 6c83a71 | 2024-06-23 00:25:18 +0200 | [diff] [blame] | 171 | device ref south_xhci on |
| 172 | register "usb2_ports" = "{ |
| 173 | [0] = USB2_PORT_MID(OC_SKIP), /* OTG */ |
| 174 | [1] = USB2_PORT_MID(OC3), /* Touch Pad */ |
| 175 | [2] = USB2_PORT_MID(OC_SKIP), /* M.2 BT */ |
| 176 | [3] = USB2_PORT_MID(OC_SKIP), /* Touch Panel */ |
| 177 | [4] = USB2_PORT_MID(OC_SKIP), /* M.2 WWAN */ |
| 178 | [5] = USB2_PORT_MID(OC0), /* Front Panel */ |
| 179 | [6] = USB2_PORT_MID(OC0), /* Front Panel */ |
| 180 | [7] = USB2_PORT_MID(OC2), /* Stacked conn (lan + usb) */ |
| 181 | [8] = USB2_PORT_MID(OC2), /* Stacked conn (lan + usb) */ |
| 182 | [9] = USB2_PORT_MID(OC1), /* LAN MAGJACK */ |
| 183 | [10] = USB2_PORT_MID(OC1), /* LAN MAGJACK */ |
| 184 | [11] = USB2_PORT_MID(OC_SKIP), /* Finger print sensor */ |
| 185 | [12] = USB2_PORT_MID(OC4), /* USB 2 stack conn */ |
| 186 | [13] = USB2_PORT_MID(OC4), /* USB 2 stack conn */ |
| 187 | }" |
| 188 | |
| 189 | register "usb3_ports" = "{ |
| 190 | [0] = USB3_PORT_DEFAULT(OC5), /* OTG */ |
| 191 | [1] = USB3_PORT_DEFAULT(OC_SKIP), /* M.2 WWAN */ |
| 192 | [2] = USB3_PORT_DEFAULT(OC3), /* Flex */ |
| 193 | [3] = USB3_PORT_DEFAULT(OC_SKIP), /* IVCAM */ |
| 194 | [4] = USB3_PORT_DEFAULT(OC1), /* LAN MAGJACK */ |
| 195 | [5] = USB3_PORT_DEFAULT(OC0), /* Front Panel */ |
| 196 | [6] = USB3_PORT_DEFAULT(OC0), /* Front Panel */ |
| 197 | [7] = USB3_PORT_DEFAULT(OC2), /* Stack Conn */ |
| 198 | [8] = USB3_PORT_DEFAULT(OC2), /* Stack Conn */ |
| 199 | [9] = USB3_PORT_DEFAULT(OC1), /* LAN MAGJACK */ |
| 200 | }" |
| 201 | end |
Felix Singer | dada017 | 2023-11-12 18:10:12 +0000 | [diff] [blame] | 202 | device ref thermal on end |
| 203 | device ref i2c0 on end |
| 204 | device ref i2c1 on end |
| 205 | device ref i2c2 on end |
| 206 | device ref i2c3 on end |
| 207 | device ref heci1 on end |
| 208 | device ref sata on end |
| 209 | device ref uart2 on end |
| 210 | device ref i2c5 on end |
| 211 | device ref i2c4 on end |
| 212 | device ref pcie_rp1 on end |
| 213 | device ref uart0 on end |
| 214 | device ref uart1 on end |
| 215 | device ref gspi0 on end |
| 216 | device ref gspi1 on end |
| 217 | device ref hda on end |
| 218 | device ref smbus on end |
| 219 | device ref fast_spi on end |
| 220 | device ref gbe on end |
Teo Boon Tiong | 4dee7b5 | 2017-09-07 00:48:55 +0800 | [diff] [blame] | 221 | end |
| 222 | end |