skylake: update processor power limits configuration
Update processor power limit configuration parameters based on
common code base support for Intel Skylake SoC based platforms.
BRANCH=None
BUG=None
TEST=Built and tested on nami system
Change-Id: Idc82f3d2f805b92fb3005d2f49098e55cb142e45
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb
index f4ccb1b..4811a41 100644
--- a/src/mainboard/intel/saddlebrook/devicetree.cb
+++ b/src/mainboard/intel/saddlebrook/devicetree.cb
@@ -213,7 +213,9 @@
}"
# PL2 override 25W
- register "tdp_pl2_override" = "25"
+ register "power_limits_config" = "{
+ .tdp_pl2_override = 25,
+ }"
# Send an extra VR mailbox command for the PS4 exit issue
register "SendVrMbxCmd" = "2"