Teo Boon Tiong | 4dee7b5 | 2017-09-07 00:48:55 +0800 | [diff] [blame^] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2017 Intel Corporation. |
| 5 | ## |
| 6 | ## This program is free software; you can redistribute it and/or modify |
| 7 | ## it under the terms of the GNU General Public License as published by |
| 8 | ## the Free Software Foundation; version 2 of the License. |
| 9 | ## |
| 10 | ## This program is distributed in the hope that it will be useful, |
| 11 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | ## GNU General Public License for more details. |
| 14 | ## |
| 15 | |
| 16 | chip soc/intel/skylake |
| 17 | |
| 18 | # Enable deep Sx states |
| 19 | register "deep_s5_enable_ac" = "0" |
| 20 | register "deep_s5_enable_dc" = "0" |
| 21 | register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" |
| 22 | |
| 23 | # GPE configuration |
| 24 | # Note that GPE events called out in ASL code rely on this |
| 25 | # route. i.e. If this route changes then the affected GPE |
| 26 | # offset bits also need to be changed. |
| 27 | register "gpe0_dw0" = "GPP_B" |
| 28 | register "gpe0_dw1" = "GPP_D" |
| 29 | register "gpe0_dw2" = "GPP_E" |
| 30 | |
| 31 | # Enable "Intel Speed Shift Technology" |
| 32 | register "speed_shift_enable" = "1" |
| 33 | |
| 34 | # FSP Configuration |
| 35 | register "EnableAzalia" = "1" |
| 36 | register "DspEnable" = "1" |
| 37 | register "IoBufferOwnership" = "3" |
| 38 | register "SmbusEnable" = "1" |
| 39 | register "ScsEmmcEnabled" = "0" |
| 40 | register "ScsEmmcHs400Enabled" = "0" |
| 41 | register "ScsSdCardEnabled" = "0" |
| 42 | register "InternalGfx" = "1" |
| 43 | register "SkipExtGfxScan" = "1" |
| 44 | register "Device4Enable" = "0" |
| 45 | register "Heci3Enabled" = "0" |
| 46 | |
| 47 | register "SaGv" = "3" |
| 48 | register "PmTimerDisabled" = "0" |
| 49 | |
| 50 | # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch |
| 51 | # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s |
| 52 | register "PmConfigSlpS3MinAssert" = "0x02" |
| 53 | |
| 54 | # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s |
| 55 | register "PmConfigSlpS4MinAssert" = "0x04" |
| 56 | |
| 57 | # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s |
| 58 | register "PmConfigSlpSusMinAssert" = "0x03" |
| 59 | |
| 60 | # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s |
| 61 | register "PmConfigSlpAMinAssert" = "0x03" |
| 62 | |
| 63 | # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled |
| 64 | register "SerialIrqConfigSirqEnable" = "0x01" |
| 65 | register "SerialIrqConfigSirqMode" = "0x01" |
| 66 | |
| 67 | # VR Settings Configuration for 5 Domains |
| 68 | #+----------------+-------+-------+-------------+-------------+-------+ |
| 69 | #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | |
| 70 | #+----------------+-------+-------+-------------+-------------+-------+ |
| 71 | #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | |
| 72 | #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | |
| 73 | #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | |
| 74 | #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | |
| 75 | #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | |
| 76 | #| ImonSlope | 0 | 0 | 0 | 0 | 0 | |
| 77 | #| ImonOffset | 0 | 0 | 0 | 0 | 0 | |
| 78 | #| IccMax | 7A | 34A | 34A | 35A | 35A | |
| 79 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | |
| 80 | #+----------------+-------+-------+-------------+-------------+-------+ |
| 81 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| 82 | .vr_config_enable = 1, \ |
| 83 | .psi1threshold = 0x50, \ |
| 84 | .psi2threshold = 0x10, \ |
| 85 | .psi3threshold = 0x4, \ |
| 86 | .psi3enable = 1, \ |
| 87 | .psi4enable = 1, \ |
| 88 | .imon_slope = 0x0, \ |
| 89 | .imon_offset = 0x0, \ |
| 90 | .icc_max = 0x1C, \ |
| 91 | .voltage_limit = 0x5F0 \ |
| 92 | }" |
| 93 | |
| 94 | register "domain_vr_config[VR_IA_CORE]" = "{ |
| 95 | .vr_config_enable = 1, \ |
| 96 | .psi1threshold = 0x50, \ |
| 97 | .psi2threshold = 0x14, \ |
| 98 | .psi3threshold = 0x4, \ |
| 99 | .psi3enable = 1, \ |
| 100 | .psi4enable = 1, \ |
| 101 | .imon_slope = 0x0, \ |
| 102 | .imon_offset = 0x0, \ |
| 103 | .icc_max = 0x88, \ |
| 104 | .voltage_limit = 0x5F0 \ |
| 105 | }" |
| 106 | register "domain_vr_config[VR_RING]" = "{ |
| 107 | .vr_config_enable = 1, \ |
| 108 | .psi1threshold = 0x50, \ |
| 109 | .psi2threshold = 0x14, \ |
| 110 | .psi3threshold = 0x4, \ |
| 111 | .psi3enable = 1, \ |
| 112 | .psi4enable = 1, \ |
| 113 | .imon_slope = 0x0, \ |
| 114 | .imon_offset = 0x0, \ |
| 115 | .icc_max = 0x88, \ |
| 116 | .voltage_limit = 0x5F0, \ |
| 117 | }" |
| 118 | |
| 119 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| 120 | .vr_config_enable = 1, \ |
| 121 | .psi1threshold = 0x50, \ |
| 122 | .psi2threshold = 0x14, \ |
| 123 | .psi3threshold = 0x4, \ |
| 124 | .psi3enable = 1, \ |
| 125 | .psi4enable = 1, \ |
| 126 | .imon_slope = 0x0, \ |
| 127 | .imon_offset = 0x0, \ |
| 128 | .icc_max = 0x8C ,\ |
| 129 | .voltage_limit = 0x5F0 \ |
| 130 | }" |
| 131 | |
| 132 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
| 133 | .vr_config_enable = 1, \ |
| 134 | .psi1threshold = 0x50, \ |
| 135 | .psi2threshold = 0x14, \ |
| 136 | .psi3threshold = 0x4, \ |
| 137 | .psi3enable = 1, \ |
| 138 | .psi4enable = 1, \ |
| 139 | .imon_slope = 0x0, \ |
| 140 | .imon_offset = 0x0, \ |
| 141 | .icc_max = 0x8C, \ |
| 142 | .voltage_limit = 0x5F0 \ |
| 143 | }" |
| 144 | |
| 145 | register "FspSkipMpInit" = "0" |
| 146 | |
| 147 | # Enable x1 slot |
| 148 | register "PcieRpEnable[7]" = "1" |
| 149 | register "PcieRpClkReqSupport[7]" = "1" |
| 150 | register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3 |
| 151 | |
| 152 | # Enable x4 slot |
| 153 | register "PcieRpEnable[8]" = "1" |
| 154 | register "PcieRpClkReqSupport[8]" = "1" |
| 155 | register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4 |
| 156 | |
| 157 | # Enable Root port 6 and 13. |
| 158 | register "PcieRpEnable[5]" = "1" |
| 159 | register "PcieRpEnable[12]" = "1" |
| 160 | |
| 161 | # Enable CLKREQ# |
| 162 | register "PcieRpClkReqSupport[5]" = "1" |
| 163 | register "PcieRpClkReqSupport[12]" = "1" |
| 164 | |
| 165 | # RP 6 uses SRCCLKREQ1# while RP `3 uses SRCCLKREQ2# |
| 166 | register "PcieRpClkReqNumber[5]" = "0" |
| 167 | register "PcieRpClkReqNumber[12]" = "1" |
| 168 | |
| 169 | register "EnableLan" = "1" |
| 170 | |
| 171 | # USB related |
| 172 | register "SsicPortEnable" = "1" |
| 173 | register "XdciEnable" = "0" |
| 174 | |
| 175 | register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # OTG |
| 176 | register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Touch Pad |
| 177 | register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 BT |
| 178 | register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Touch Panel |
| 179 | register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN |
| 180 | register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Front Panel |
| 181 | register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # Front Panel |
| 182 | register "usb2_ports[7]" = "USB2_PORT_MID(OC2)" # Stacked conn (lan + usb) |
| 183 | register "usb2_ports[8]" = "USB2_PORT_MID(OC2)" # Stacked conn (lan + usb) |
| 184 | register "usb2_ports[9]" = "USB2_PORT_MID(OC1)" # LAN MAGJACK |
| 185 | register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" # LAN MAGJACK |
| 186 | register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)" # Finger print sensor |
| 187 | register "usb2_ports[12]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn |
| 188 | register "usb2_ports[13]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn |
| 189 | |
| 190 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" # OTG |
| 191 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN |
| 192 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Flex |
| 193 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # IVCAM |
| 194 | register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK |
| 195 | register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel |
| 196 | register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel |
| 197 | register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn |
| 198 | register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn |
| 199 | register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK |
| 200 | |
| 201 | register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V |
| 202 | |
| 203 | # Must leave UART0 enabled or SD/eMMC will not work as PCI |
| 204 | |
| 205 | register "pirqa_routing" = "0x0b" |
| 206 | register "pirqb_routing" = "0x0a" |
| 207 | register "pirqc_routing" = "0x0b" |
| 208 | register "pirqd_routing" = "0x0b" |
| 209 | register "pirqe_routing" = "0x0b" |
| 210 | register "pirqf_routing" = "0x0b" |
| 211 | register "pirqg_routing" = "0x0b" |
| 212 | register "pirqh_routing" = "0x0b" |
| 213 | |
| 214 | register "PmTimerDisabled" = "0" |
| 215 | |
| 216 | register "EnableSata" = "1" |
| 217 | register "SataSalpSupport" = "1" |
| 218 | register "SataPortsEnable" = "{ \ |
| 219 | [0] = 1, \ |
| 220 | [1] = 1, \ |
| 221 | [2] = 1, \ |
| 222 | [3] = 1, \ |
| 223 | [4] = 1, \ |
| 224 | [5] = 1, \ |
| 225 | [6] = 1, \ |
| 226 | [7] = 1, \ |
| 227 | }" |
| 228 | register "SerialIoDevMode" = "{ \ |
| 229 | [PchSerialIoIndexI2C0] = PchSerialIoPci, \ |
| 230 | [PchSerialIoIndexI2C1] = PchSerialIoPci, \ |
| 231 | [PchSerialIoIndexI2C2] = PchSerialIoPci, \ |
| 232 | [PchSerialIoIndexI2C3] = PchSerialIoPci, \ |
| 233 | [PchSerialIoIndexI2C4] = PchSerialIoPci, \ |
| 234 | [PchSerialIoIndexI2C5] = PchSerialIoPci, \ |
| 235 | [PchSerialIoIndexSpi0] = PchSerialIoPci, \ |
| 236 | [PchSerialIoIndexSpi1] = PchSerialIoPci, \ |
| 237 | [PchSerialIoIndexUart0] = PchSerialIoPci, \ |
| 238 | [PchSerialIoIndexUart1] = PchSerialIoPci, \ |
| 239 | [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ |
| 240 | }" |
| 241 | |
| 242 | # PL2 override 25W |
| 243 | register "tdp_pl2_override" = "25" |
| 244 | |
| 245 | # Send an extra VR mailbox command for the PS4 exit issue |
| 246 | register "SendVrMbxCmd" = "2" |
| 247 | |
| 248 | # Enable/Disable VMX feature |
| 249 | register "VmxEnable" = "0" |
| 250 | # Use default SD card detect GPIO configuration |
| 251 | #register "sdcard_cd_gpio_default" = "GPP_A7" |
| 252 | |
| 253 | device cpu_cluster 0 on |
| 254 | device lapic 0 on end |
| 255 | end |
| 256 | device domain 0 on |
| 257 | device pci 00.0 on end # Host Bridge |
| 258 | device pci 02.0 on end # Integrated Graphics Device |
| 259 | device pci 14.0 on end # USB xHCI |
| 260 | device pci 14.1 off end # USB xDCI (OTG) |
| 261 | device pci 14.2 on end # Thermal Subsystem |
| 262 | device pci 15.0 on end # I2C #0 |
| 263 | device pci 15.1 on end # I2C #1 |
| 264 | device pci 15.2 on end # I2C #2 |
| 265 | device pci 15.3 on end # I2C #3 |
| 266 | device pci 16.0 on end # Management Engine Interface 1 |
| 267 | device pci 16.1 off end # Management Engine Interface 2 |
| 268 | device pci 16.2 off end # Management Engine IDE-R |
| 269 | device pci 16.3 off end # Management Engine KT Redirection |
| 270 | device pci 16.4 off end # Management Engine Interface 3 |
| 271 | device pci 17.0 on end # SATA |
| 272 | device pci 19.0 on end # UART #2 |
| 273 | device pci 19.1 on end # I2C #5 |
| 274 | device pci 19.2 on end # I2C #4 |
| 275 | device pci 1c.0 on end # PCI Express Port 1 |
| 276 | device pci 1c.1 off end # PCI Express Port 2 |
| 277 | device pci 1c.2 off end # PCI Express Port 3 |
| 278 | device pci 1c.3 off end # PCI Express Port 4 |
| 279 | device pci 1c.4 off end # PCI Express Port 5 |
| 280 | device pci 1c.5 off end # PCI Express Port 6 |
| 281 | device pci 1c.6 off end # PCI Express Port 7 |
| 282 | device pci 1c.7 off end # PCI Express Port 8 |
| 283 | device pci 1d.0 off end # PCI Express Port 9 |
| 284 | device pci 1d.1 off end # PCI Express Port 10 |
| 285 | device pci 1d.2 off end # PCI Express Port 11 |
| 286 | device pci 1d.3 off end # PCI Express Port 12 |
| 287 | device pci 1e.0 on end # UART #0 |
| 288 | device pci 1e.1 on end # UART #1 |
| 289 | device pci 1e.2 on end # GSPI #0 |
| 290 | device pci 1e.3 on end # GSPI #1 |
| 291 | device pci 1e.4 off end # eMMC |
| 292 | device pci 1e.5 off end # SDIO |
| 293 | device pci 1e.6 off end # SDCard |
| 294 | device pci 1f.0 on |
| 295 | end # LPC Interface |
| 296 | device pci 1f.1 on end # P2SB |
| 297 | device pci 1f.2 on end # Power Management Controller |
| 298 | device pci 1f.3 on end # Intel HDA |
| 299 | device pci 1f.4 on end # SMBus |
| 300 | device pci 1f.5 on end # PCH SPI |
| 301 | device pci 1f.6 on end # GbE |
| 302 | end |
| 303 | end |