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Patrick Georgiac959032020-05-05 22:49:26 +02001/* SPDX-License-Identifier: GPL-2.0-or-later */
Jonathan Zhang8f895492020-01-16 11:16:45 -08002
3#include <assert.h>
Jonathan Zhang8f895492020-01-16 11:16:45 -08004#include <console/console.h>
Jonathan Zhang8f895492020-01-16 11:16:45 -08005#include <device/pci.h>
Patrick Rudolph106d7b32024-01-18 09:14:03 +01006#include <device/pci_ids.h>
Jonathan Zhang8f895492020-01-16 11:16:45 -08007#include <hob_iiouds.h>
8#include <intelblocks/cpulib.h>
9#include <intelblocks/pcr.h>
10#include <soc/iomap.h>
Jonathan Zhang8f895492020-01-16 11:16:45 -080011#include <soc/msr.h>
12#include <soc/pci_devs.h>
13#include <soc/pcr_ids.h>
14#include <soc/soc_util.h>
Andrey Petrov662da6c2020-03-16 22:46:57 -070015#include <soc/util.h>
Jonathan Zhang8f895492020-01-16 11:16:45 -080016
Jonathan Zhang8f895492020-01-16 11:16:45 -080017
18/*
19 * +-------------------------+ TOLM
20 * | System Management Mode |
21 * | code and data |
22 * | (TSEG) |
23 * +-------------------------+ SMM base (aligned)
24 * | |
25 * | Chipset Reserved Memory |
26 * | |
27 * +-------------------------+ top_of_ram (aligned)
28 * | |
29 * | CBMEM Root |
30 * | |
31 * +-------------------------+
32 * | |
33 * | FSP Reserved Memory |
34 * | |
35 * +-------------------------+
36 * | |
37 * | Various CBMEM Entries |
38 * | |
39 * +-------------------------+ top_of_stack (8 byte aligned)
40 * | |
41 * | stack (CBMEM Entry) |
42 * | |
43 * +-------------------------+
44 */
45
Marc Jones645bca42020-11-02 14:29:46 -070046const struct SystemMemoryMapHob *get_system_memory_map(void)
Jonathan Zhang8f895492020-01-16 11:16:45 -080047{
48 size_t hob_size;
Marc Jones645bca42020-11-02 14:29:46 -070049 const uint8_t mem_hob_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID;
50 const struct SystemMemoryMapHob *memmap_addr;
51
52 memmap_addr = fsp_find_extension_hob_by_guid(mem_hob_guid, &hob_size);
Elyes Haouasf1ba7d62022-09-13 10:03:44 +020053 assert(memmap_addr && hob_size != 0);
Marc Jones645bca42020-11-02 14:29:46 -070054
55 return memmap_addr;
56}
57
Arthur Heymans550f55e2022-08-24 14:44:26 +020058bool is_pcie_iio_stack_res(const STACK_RES *res)
59{
Arthur Heymans470f1d32023-08-31 18:19:09 +020060 return res->BusBase < res->BusLimit;
Arthur Heymans550f55e2022-08-24 14:44:26 +020061}
62
Patrick Rudolph15672592024-01-18 07:57:07 +010063bool is_ubox_stack_res(const STACK_RES *res)
64{
65 /*
66 * Unlike on later platforms there's no separate "UBOX" stack.
67 *
68 * The UBOX devices can always be found on the first bus on the stack IIO0 (CSTACK).
69 * This bus is also referred to as uncore bus 0 or B(30).
70 * It has at a fixed address the UBOX:
71 * B(30):8.0 8086:2014
72 * B(30):8.1 8086:2015
73 * B(30):8.2 8086:2016
74 *
75 * The PCU devices can always be on the first bus of the stack IIO1 (PSTACK).
76 * This bus is also referred to as uncore bus 1 or B(31).
77 * It has at a fixed address the PCU:
78 * B(31):30.0 8086:2080
79 * B(31):30.1 8086:2081
80 * B(31):30.2 8086:2082
81 */
82
83 return false;
84}
85
Patrick Rudolph47e68822024-01-19 16:05:56 +010086/* Returns the UBOX(stack) bus number when called from socket0 */
87uint8_t socket0_get_ubox_busno(const uint8_t stack)
Jonathan Zhangca520a72023-01-23 18:14:53 -080088{
89 if (stack >= MAX_IIO_STACK) {
90 printk(BIOS_ERR, "%s: Stack %u does not exist!\n", __func__, stack);
91 return 0;
92 }
93 const pci_devfn_t dev = PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC);
94 const uint16_t offset = stack / 4 ? UBOX_DECS_CPUBUSNO1_CSR : UBOX_DECS_CPUBUSNO_CSR;
95 return pci_io_read_config32(dev, offset) >> (8 * (stack % 4)) & 0xff;
96}
97
Patrick Rudolph106d7b32024-01-18 09:14:03 +010098#if ENV_RAMSTAGE
Marc Jones645bca42020-11-02 14:29:46 -070099void config_reset_cpl3_csrs(void)
Jonathan Zhang8f895492020-01-16 11:16:45 -0800100{
Marc Jones645bca42020-11-02 14:29:46 -0700101 uint32_t data, plat_info, max_min_turbo_limit_ratio;
Patrick Rudolph106d7b32024-01-18 09:14:03 +0100102 struct device *dev;
Jonathan Zhang8f895492020-01-16 11:16:45 -0800103
Patrick Rudolph106d7b32024-01-18 09:14:03 +0100104 dev = NULL;
105 while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR0_DEVID, dev))) {
106 data = pci_read_config32(dev, PCU_CR0_P_STATE_LIMITS);
Marc Jones645bca42020-11-02 14:29:46 -0700107 data |= P_STATE_LIMITS_LOCK;
Patrick Rudolph106d7b32024-01-18 09:14:03 +0100108 pci_write_config32(dev, PCU_CR0_P_STATE_LIMITS, data);
Marc Jones645bca42020-11-02 14:29:46 -0700109
Patrick Rudolph106d7b32024-01-18 09:14:03 +0100110 plat_info = pci_read_config32(dev, PCU_CR0_PLATFORM_INFO);
111 dump_csr64(dev, PCU_CR0_PLATFORM_INFO);
Marc Jones645bca42020-11-02 14:29:46 -0700112 max_min_turbo_limit_ratio =
113 (plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >>
114 MAX_NON_TURBO_LIM_RATIO_SHIFT;
115 printk(BIOS_SPEW, "plat_info: 0x%x, max_min_turbo_limit_ratio: 0x%x\n",
116 plat_info, max_min_turbo_limit_ratio);
Patrick Rudolph106d7b32024-01-18 09:14:03 +0100117 }
Marc Jones645bca42020-11-02 14:29:46 -0700118
Patrick Rudolph106d7b32024-01-18 09:14:03 +0100119 dev = NULL;
120 while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR1_DEVID, dev))) {
121 data = pci_read_config32(dev, PCU_CR1_SAPMCTL);
Marc Jones645bca42020-11-02 14:29:46 -0700122 /* clear bits 27:31 - FSP sets this with 0x7 which needs to be cleared */
123 data &= 0x0fffffff;
124 data |= SAPMCTL_LOCK_MASK;
Patrick Rudolph106d7b32024-01-18 09:14:03 +0100125 pci_write_config32(dev, PCU_CR1_SAPMCTL, data);
126 }
Marc Jones645bca42020-11-02 14:29:46 -0700127
Patrick Rudolph106d7b32024-01-18 09:14:03 +0100128 dev = NULL;
129 while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR2_DEVID, dev))) {
Marc Jones645bca42020-11-02 14:29:46 -0700130 data = PCIE_IN_PKGCSTATE_L1_MASK;
Patrick Rudolph106d7b32024-01-18 09:14:03 +0100131 pci_write_config32(dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK, data);
Marc Jones645bca42020-11-02 14:29:46 -0700132
133 data = KTI_IN_PKGCSTATE_L1_MASK;
Patrick Rudolph106d7b32024-01-18 09:14:03 +0100134 pci_write_config32(dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2, data);
Marc Jones645bca42020-11-02 14:29:46 -0700135
136 data = PROCHOT_RATIO;
137 printk(BIOS_SPEW, "PCU_CR2_PROCHOT_RESPONSE_RATIO_REG data: 0x%x\n", data);
Patrick Rudolph106d7b32024-01-18 09:14:03 +0100138 pci_write_config32(dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG, data);
139 dump_csr(dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG);
Marc Jones645bca42020-11-02 14:29:46 -0700140
Patrick Rudolph106d7b32024-01-18 09:14:03 +0100141 data = pci_read_config32(dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL);
Marc Jones645bca42020-11-02 14:29:46 -0700142 data |= UNOCRE_PLIMIT_OVERRIDE_SHIFT;
Patrick Rudolph106d7b32024-01-18 09:14:03 +0100143 pci_write_config32(dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL, data);
Jonathan Zhang8f895492020-01-16 11:16:45 -0800144 }
Marc Jonese1db55b2020-09-28 16:53:19 -0600145}
Patrick Rudolph106d7b32024-01-18 09:14:03 +0100146#endif
Jonathan Zhang8f895492020-01-16 11:16:45 -0800147
Marc Jones995a7e22020-10-28 17:08:54 -0600148/*
149 * EX: SKX-SP
150 * Ports Stack Stack(HOB) IioConfigIou
151 * ==========================================
152 * 0 CSTACK stack 0 IOU0
153 * 1A..1D PSTACKZ stack 1 IOU1
154 * 2A..2D PSTACK1 stack 2 IOU2
155 * 3A..3D PSTACK2 stack 3 IOU3
156 * 5A..4D PSTACK3 stack 4 IOU4
157 * 5A..5D PSTACK4 stack 5 IOU5
158 */
159int soc_get_stack_for_port(int port)
160{
161 if (port == PORT_0)
162 return CSTACK;
163 else if (port >= PORT_1A && port <= PORT_1D)
164 return PSTACK0;
165 else if (port >= PORT_2A && port <= PORT_2D)
166 return PSTACK1;
167 else if (port >= PORT_3A && port <= PORT_3D)
168 return PSTACK2;
169 else if (port >= PORT_4A && port <= PORT_4D)
170 return PSTACK3; // MCP0
171 else if (port >= PORT_5A && port <= PORT_5D)
172 return PSTACK4; // MCP1
173 else
174 return -1;
175}
Arthur Heymansa1cc5572020-11-06 12:53:33 +0100176
177uint8_t soc_get_iio_ioapicid(int socket, int stack)
178{
179 uint8_t ioapic_id = socket ? 0xf : 0x9;
180 switch (stack) {
181 case CSTACK:
182 break;
183 case PSTACK0:
184 ioapic_id += 1;
185 break;
186 case PSTACK1:
187 ioapic_id += 2;
188 break;
189 case PSTACK2:
190 ioapic_id += 3;
191 break;
192 default:
193 return 0xff;
194 }
195 return ioapic_id;
196}
Shuo Liua5bdf8e2024-02-20 01:06:10 +0800197
198bool is_memtype_reserved(uint16_t mem_type)
199{
200 return !!(mem_type & MEM_TYPE_RESERVED);
201}
202
203bool is_memtype_non_volatile(uint16_t mem_type)
204{
205 return !(mem_type & MEMTYPE_VOLATILE_MASK);
206}
207
208bool is_memtype_processor_attached(uint16_t mem_type)
209{
210 return true;
211}