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review.coreboot.org / coreboot / db2e11841ad69d52a610577abb0aab288eb094b7 / . / src / vendorcode / amd / agesa / f14 / Config / PlatformInstall.h
blob: 31472b2c2eb21eb6118a8dde679873c4287359c6 [file] [log] [blame]
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * Install of build options for a combination of package type, processor, and features.
6 *
7 * This file generates the defaults tables for the all platform solution
8 * combinations. The documented build options are imported from a user
9 * controlled file for processing.
10 *
11 * @xrefitem bom "File Content Label" "Release Content"
12 * @e project: AGESA
13 * @e sub-project: Core
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]14 * @e \$Revision: 47417 $ @e \$Date: 2011-02-18 12:48:20 -0700 (Fri, 18 Feb 2011) $
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]15 */
16/*
17 *****************************************************************************
18 *
19 * Copyright (c) 2011, Advanced Micro Devices, Inc.
20 * All rights reserved.
Edward O'Callaghane963b382014-07-06 19:27:14 +1000[diff] [blame]21 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions are met:
24 * * Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * * Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in the
28 * documentation and/or other materials provided with the distribution.
Edward O'Callaghane963b382014-07-06 19:27:14 +1000[diff] [blame]29 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
30 * its contributors may be used to endorse or promote products derived
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]31 * from this software without specific prior written permission.
Edward O'Callaghane963b382014-07-06 19:27:14 +1000[diff] [blame]32 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
35 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
36 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
37 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
38 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
40 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
41 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
42 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Edward O'Callaghane963b382014-07-06 19:27:14 +1000[diff] [blame]43 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]44 * ***************************************************************************
45 *
46 */
47
48/*****************************************************************************
49 *
50 * Start processing the user options: First, set default settings
51 *
52 ****************************************************************************/
53
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]54VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
55 //ModuleHeaderSignature
56 // Remove 'DOM$' as temp solution before update BinUtil.exe ,
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]57 Int32FromChar ('0', '0', '0', '0'),
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]58 //ModuleIdentifier[8]
59 AGESA_ID,
60 //ModuleVersion[12]
61 AGESA_VERSION_STRING,
62 //ModuleDispatcher
63 NULL,//(VOID *)(UINT64)((MODULE_ENTRY)AmdAgesaDispatcher),
64 //NextBlock
65 NULL
66};
67
Angel Pons41b820c2020-05-21 00:58:33 +0200[diff] [blame]68/* The default fixed MTRR values to be set after memory initialization */
69static const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
70{
71 { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
72 { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
73 { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
74 { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
75 { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
76 { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
77 { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
78 { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
79 { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
80 { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
81 { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
82 { CPU_LIST_TERMINAL },
83};
84
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]85/* Process solution defined socket / family installations
86 *
87 * As part of the release package for each image, define the options below to select the
88 * AGESA processor support included in that image.
89 */
90
91/* Default sockets to off */
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]92#define OPTION_FT1_SOCKET_SUPPORT FALSE
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]93
94/* Default families to off */
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]95#define OPTION_FAMILY14H FALSE
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]96
97/* Enable the appropriate socket support */
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]98#ifdef INSTALL_FT1_SOCKET_SUPPORT
99 #if INSTALL_FT1_SOCKET_SUPPORT == TRUE
100 #undef OPTION_FT1_SOCKET_SUPPORT
101 #define OPTION_FT1_SOCKET_SUPPORT TRUE
102 #endif
103#endif
104
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]105// F14 is supported in FT1
106#ifdef INSTALL_FAMILY_14_SUPPORT
107 #if INSTALL_FAMILY_14_SUPPORT == TRUE
108 #undef OPTION_FAMILY14H
109 #define OPTION_FAMILY14H TRUE
110 #endif
111#endif
112
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]113#if (OPTION_FAMILY14H == TRUE)
114 #if (OPTION_FT1_SOCKET_SUPPORT == FALSE)
115 #undef OPTION_FAMILY14H
116 #define OPTION_FAMILY14H FALSE
117 #endif
118#endif
119
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]120
121/* Check for invalid combinations of socket/family */
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]122
123#if (OPTION_FT1_SOCKET_SUPPORT == TRUE)
124 #if (OPTION_FAMILY14H == FALSE)
125 #error No FT1 supported families included in the build
126 #endif
127#endif
128
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]129/* Process AGESA private data
130 *
131 * Turn on appropriate CPU models and memory controllers,
132 * as well as some other memory controls.
133 */
134
135/* Default all models to off */
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]136#define OPTION_FAMILY14H_ON FALSE
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]137
138/* Default all memory controllers to off */
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]139#define OPTION_MEMCTLR_ON FALSE
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]140
141/* Default all memory controls to off */
142#define OPTION_HW_WRITE_LEV_TRAINING FALSE
143#define OPTION_SW_WRITE_LEV_TRAINING FALSE
144#define OPTION_CONTINOUS_PATTERN_GENERATION FALSE
145#define OPTION_HW_DQS_REC_EN_TRAINING FALSE
146#define OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING FALSE
147#define OPTION_OPT_SW_DQS_REC_EN_TRAINING FALSE
148#define OPTION_NON_OPT_SW_RD_WR_POS_TRAINING FALSE
149#define OPTION_OPT_SW_RD_WR_POS_TRAINING FALSE
150#define OPTION_MAX_RD_LAT_TRAINING FALSE
151#define OPTION_HW_DRAM_INIT FALSE
152#define OPTION_SW_DRAM_INIT FALSE
153#define OPTION_S3_MEM_SUPPORT FALSE
154#define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
155
156/* Defaults for public user options */
157#define OPTION_UDIMMS FALSE
158#define OPTION_RDIMMS FALSE
159#define OPTION_SODIMMS FALSE
160#define OPTION_LRDIMMS FALSE
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]161#define OPTION_DDR3 FALSE
162#define OPTION_ECC FALSE
163#define OPTION_BANK_INTERLEAVE FALSE
164#define OPTION_DCT_INTERLEAVE FALSE
165#define OPTION_NODE_INTERLEAVE FALSE
166#define OPTION_PARALLEL_TRAINING FALSE
167#define OPTION_ONLINE_SPARE FALSE
168#define OPTION_MEM_RESTORE FALSE
169#define OPTION_DIMM_EXCLUDE FALSE
170
171/* Default all CPU controls to off */
172#define OPTION_MULTISOCKET FALSE
173#define OPTION_SRAT FALSE
174#define OPTION_SLIT FALSE
175#define OPTION_HT_ASSIST FALSE
176#define OPTION_ATM_MODE FALSE
177#define OPTION_CPU_CORELEVLING FALSE
178#define OPTION_MSG_BASED_C1E FALSE
179#define OPTION_CPU_CFOH FALSE
180#define OPTION_C6_STATE FALSE
181#define OPTION_IO_CSTATE FALSE
182#define OPTION_CPB FALSE
183#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT FALSE
184#define OPTION_S3SCRIPT FALSE
185#define OPTION_GFX_RECOVERY FALSE
186
187/* Enable all private controls based on socket/family enables */
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]188
189#if (OPTION_FT1_SOCKET_SUPPORT == TRUE)
190 #if (OPTION_FAMILY14H == TRUE)
191 #undef OPTION_FAMILY14H_ON
192 #define OPTION_FAMILY14H_ON TRUE
193 #undef OPTION_MEMCTLR_ON
194 #define OPTION_MEMCTLR_ON TRUE
195 #undef OPTION_HW_WRITE_LEV_TRAINING
196 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
197 #undef OPTION_CONTINOUS_PATTERN_GENERATION
198 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
199 #undef OPTION_MAX_RD_LAT_TRAINING
200 #define OPTION_MAX_RD_LAT_TRAINING TRUE
201 #undef OPTION_HW_DQS_REC_EN_TRAINING
202 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
203 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
204 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
205 #undef OPTION_SW_DRAM_INIT
206 #define OPTION_SW_DRAM_INIT TRUE
207 #undef OPTION_S3_MEM_SUPPORT
208 #define OPTION_S3_MEM_SUPPORT TRUE
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]209 #undef OPTION_C6_STATE
210 #define OPTION_C6_STATE TRUE
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]211 #undef OPTION_CPB
212 #define OPTION_CPB TRUE
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]213 #undef OPTION_IO_CSTATE
214 #define OPTION_IO_CSTATE TRUE
215 #undef OPTION_S3SCRIPT
216 #define OPTION_S3SCRIPT TRUE
217 #undef OPTION_UDIMMS
218 #define OPTION_UDIMMS TRUE
219 #undef OPTION_SODIMMS
220 #define OPTION_SODIMMS TRUE
221 #undef OPTION_DDR3
222 #define OPTION_DDR3 TRUE
223 #undef OPTION_BANK_INTERLEAVE
224 #define OPTION_BANK_INTERLEAVE TRUE
225 #undef OPTION_MEM_RESTORE
226 #define OPTION_MEM_RESTORE TRUE
227 #undef OPTION_DIMM_EXCLUDE
228 #define OPTION_DIMM_EXCLUDE TRUE
229 #endif
230#endif
231
Kyösti Mälkkiba4e6952017-08-31 15:17:36 +0300[diff] [blame]232#if (OPTION_FAMILY14H == TRUE)
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]233 #undef GNB_SUPPORT
234 #define GNB_SUPPORT TRUE
235#endif
236
237#define OPTION_ACPI_PSTATES TRUE
238#define OPTION_WHEA TRUE
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]239#define OPTION_DMI FALSE
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]240#define OPTION_EARLY_SAMPLES FALSE
241#define CFG_ACPI_PSTATES_PPC TRUE
242#define CFG_ACPI_PSTATES_PCT TRUE
243#define CFG_ACPI_PSTATES_PSD TRUE
244#define CFG_ACPI_PSTATES_PSS TRUE
245#define CFG_ACPI_PSTATES_XPSS TRUE
246#define CFG_ACPI_PSTATE_PSD_INDPX FALSE
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]247#define CFG_VRM_HIGH_SPEED_ENABLE TRUE
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]248#define CFG_VRM_NB_HIGH_SPEED_ENABLE FALSE
249#define OPTION_ALIB TRUE
250/*---------------------------------------------------------------------------
251 * Processing the options: Second, process the user's selections
252 *--------------------------------------------------------------------------*/
253#ifdef BLDOPT_REMOVE_MULTISOCKET_SUPPORT
254 #if BLDOPT_REMOVE_MULTISOCKET_SUPPORT == TRUE
255 #undef OPTION_MULTISOCKET
256 #define OPTION_MULTISOCKET FALSE
257 #endif
258#endif
259#ifdef BLDOPT_REMOVE_ECC_SUPPORT
260 #if BLDOPT_REMOVE_ECC_SUPPORT == TRUE
261 #undef OPTION_ECC
262 #define OPTION_ECC FALSE
263 #endif
264#endif
265#ifdef BLDOPT_REMOVE_UDIMMS_SUPPORT
266 #if BLDOPT_REMOVE_UDIMMS_SUPPORT == TRUE
267 #undef OPTION_UDIMMS
268 #define OPTION_UDIMMS FALSE
269 #endif
270#endif
271#ifdef BLDOPT_REMOVE_RDIMMS_SUPPORT
272 #if BLDOPT_REMOVE_RDIMMS_SUPPORT == TRUE
273 #undef OPTION_RDIMMS
274 #define OPTION_RDIMMS FALSE
275 #endif
276#endif
277#ifdef BLDOPT_REMOVE_SODIMMS_SUPPORT
278 #if BLDOPT_REMOVE_SODIMMS_SUPPORT == TRUE
279 #undef OPTION_SODIMMS
280 #define OPTION_SODIMMS FALSE
281 #endif
282#endif
283#ifdef BLDOPT_REMOVE_LRDIMMS_SUPPORT
284 #if BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE
285 #undef OPTION_LRDIMMS
286 #define OPTION_LRDIMMS FALSE
287 #endif
288#endif
289#ifdef BLDOPT_REMOVE_BANK_INTERLEAVE
290 #if BLDOPT_REMOVE_BANK_INTERLEAVE == TRUE
291 #undef OPTION_BANK_INTERLEAVE
292 #define OPTION_BANK_INTERLEAVE FALSE
293 #endif
294#endif
295#ifdef BLDOPT_REMOVE_DCT_INTERLEAVE
296 #if BLDOPT_REMOVE_DCT_INTERLEAVE == TRUE
297 #undef OPTION_DCT_INTERLEAVE
298 #define OPTION_DCT_INTERLEAVE FALSE
299 #endif
300#endif
301#ifdef BLDOPT_REMOVE_NODE_INTERLEAVE
302 #if BLDOPT_REMOVE_NODE_INTERLEAVE == TRUE
303 #undef OPTION_NODE_INTERLEAVE
304 #define OPTION_NODE_INTERLEAVE FALSE
305 #endif
306#endif
307#ifdef BLDOPT_REMOVE_PARALLEL_TRAINING
308 #if BLDOPT_REMOVE_PARALLEL_TRAINING == TRUE
309 #undef OPTION_PARALLEL_TRAINING
310 #define OPTION_PARALLEL_TRAINING FALSE
311 #endif
312#endif
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]313/* Originally BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT, but inverted alongside the default value */
314#ifdef BLDOPT_ENABLE_ONLINE_SPARE_SUPPORT
315 #if BLDOPT_ENABLE_ONLINE_SPARE_SUPPORT == TRUE
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]316 #undef OPTION_ONLINE_SPARE
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]317 #define OPTION_ONLINE_SPARE TRUE
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]318 #endif
319#endif
320#ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
321 #if BLDOPT_REMOVE_MEM_RESTORE_SUPPORT == TRUE
322 #undef OPTION_MEM_RESTORE
323 #define OPTION_MEM_RESTORE FALSE
324 #endif
325#endif
326#ifdef BLDOPT_REMOVE_ACPI_PSTATES
327 #if BLDOPT_REMOVE_ACPI_PSTATES == TRUE
328 #undef OPTION_ACPI_PSTATES
329 #define OPTION_ACPI_PSTATES FALSE
330 #endif
331#endif
332#ifdef BLDOPT_REMOVE_SRAT
333 #if BLDOPT_REMOVE_SRAT == TRUE
334 #undef OPTION_SRAT
335 #define OPTION_SRAT FALSE
336 #endif
337#endif
338#ifdef BLDOPT_REMOVE_SLIT
339 #if BLDOPT_REMOVE_SLIT == TRUE
340 #undef OPTION_SLIT
341 #define OPTION_SLIT FALSE
342 #endif
343#endif
344#ifdef BLDOPT_REMOVE_WHEA
345 #if BLDOPT_REMOVE_WHEA == TRUE
346 #undef OPTION_WHEA
347 #define OPTION_WHEA FALSE
348 #endif
349#endif
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]350/* Originally BLDOPT_REMOVE_DMI, but inverted alongside the default value */
351#ifdef BLDOPT_ENABLE_DMI
352 #if BLDOPT_ENABLE_DMI == TRUE
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]353 #undef OPTION_DMI
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]354 #define OPTION_DMI TRUE
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]355 #endif
356#endif
357#ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR
358 #if BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR == TRUE
359 #undef OPTION_ADDR_TO_CS_TRANSLATOR
360 #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
361 #endif
362#endif
363
364#ifdef BLDOPT_REMOVE_HT_ASSIST
365 #if BLDOPT_REMOVE_HT_ASSIST == TRUE
366 #undef OPTION_HT_ASSIST
367 #define OPTION_HT_ASSIST FALSE
368 #endif
369#endif
370
371#ifdef BLDOPT_REMOVE_ATM_MODE
372 #if BLDOPT_REMOVE_ATM_MODE == TRUE
373 #undef OPTION_ATM_MODE
374 #define OPTION_ATM_MODE FALSE
375 #endif
376#endif
377
378#ifdef BLDOPT_REMOVE_MSG_BASED_C1E
379 #if BLDOPT_REMOVE_MSG_BASED_C1E == TRUE
380 #undef OPTION_MSG_BASED_C1E
381 #define OPTION_MSG_BASED_C1E FALSE
382 #endif
383#endif
384
385#ifdef BLDOPT_REMOVE_C6_STATE
386 #if BLDOPT_REMOVE_C6_STATE == TRUE
387 #undef OPTION_C6_STATE
388 #define OPTION_C6_STATE FALSE
389 #endif
390#endif
391
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]392/* Originally BLDOPT_REMOVE_GFX_RECOVERY, but inverted alongside the default value */
393#ifdef BLDOPT_ENABLE_GFX_RECOVERY
394 #if BLDOPT_ENABLE_GFX_RECOVERY == TRUE
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]395 #undef OPTION_GFX_RECOVERY
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]396 #define OPTION_GFX_RECOVERY TRUE
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]397 #endif
398#endif
399
400#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PPC
401 #if BLDCFG_REMOVE_ACPI_PSTATES_PPC == TRUE
402 #undef CFG_ACPI_PSTATES_PPC
403 #define CFG_ACPI_PSTATES_PPC FALSE
404 #endif
405#endif
406
407#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PCT
408 #if BLDCFG_REMOVE_ACPI_PSTATES_PCT == TRUE
409 #undef CFG_ACPI_PSTATES_PCT
410 #define CFG_ACPI_PSTATES_PCT FALSE
411 #endif
412#endif
413
414#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSD
415 #if BLDCFG_REMOVE_ACPI_PSTATES_PSD == TRUE
416 #undef CFG_ACPI_PSTATES_PSD
417 #define CFG_ACPI_PSTATES_PSD FALSE
418 #endif
419#endif
420
421#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSS
422 #if BLDCFG_REMOVE_ACPI_PSTATES_PSS == TRUE
423 #undef CFG_ACPI_PSTATES_PSS
424 #define CFG_ACPI_PSTATES_PSS FALSE
425 #endif
426#endif
427
428#ifdef BLDCFG_REMOVE_ACPI_PSTATES_XPSS
429 #if BLDCFG_REMOVE_ACPI_PSTATES_XPSS == TRUE
430 #undef CFG_ACPI_PSTATES_XPSS
431 #define CFG_ACPI_PSTATES_XPSS FALSE
432 #endif
433#endif
434
435#ifdef BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT
436 #if BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT == TRUE
437 #undef CFG_ACPI_PSTATE_PSD_INDPX
438 #define CFG_ACPI_PSTATE_PSD_INDPX TRUE
439 #endif
440#endif
441
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]442/* Originally BLDCFG_VRM_HIGH_SPEED_ENABLE, but inverted alongside the default value */
443#ifdef BLDCFG_VRM_HIGH_SPEED_DISABLE
444 #if BLDCFG_VRM_HIGH_SPEED_DISABLE == TRUE
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]445 #undef CFG_VRM_HIGH_SPEED_ENABLE
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]446 #define CFG_VRM_HIGH_SPEED_ENABLE FALSE
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]447 #endif
448#endif
449
450#ifdef BLDCFG_VRM_NB_HIGH_SPEED_ENABLE
451 #if BLDCFG_VRM_NB_HIGH_SPEED_ENABLE == TRUE
452 #undef CFG_VRM_NB_HIGH_SPEED_ENABLE
453 #define CFG_VRM_NB_HIGH_SPEED_ENABLE TRUE
454 #endif
455#endif
456
457#ifdef BLDCFG_STARTING_BUSNUM
458 #define CFG_STARTING_BUSNUM (BLDCFG_STARTING_BUSNUM)
459#else
460 #define CFG_STARTING_BUSNUM (0)
461#endif
462
463#ifdef BLDCFG_AMD_PLATFORM_TYPE
464 #define CFG_AMD_PLATFORM_TYPE BLDCFG_AMD_PLATFORM_TYPE
465#else
466 #define CFG_AMD_PLATFORM_TYPE 0
467#endif
468
469CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
470
471#ifdef BLDCFG_MAXIMUM_BUSNUM
472 #define CFG_MAXIMUM_BUSNUM (BLDCFG_MAXIMUM_BUSNUM)
473#else
474 #define CFG_MAXIMUM_BUSNUM (0xF8)
475#endif
476
477#ifdef BLDCFG_ALLOCATED_BUSNUM
478 #define CFG_ALLOCATED_BUSNUM (BLDCFG_ALLOCATED_BUSNUM)
479#else
480 #define CFG_ALLOCATED_BUSNUM (0x20)
481#endif
482
483#ifdef BLDCFG_BUID_SWAP_LIST
484 #define CFG_BUID_SWAP_LIST (BLDCFG_BUID_SWAP_LIST)
485#else
486 #define CFG_BUID_SWAP_LIST (NULL)
487#endif
488
489#ifdef BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST
490 #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST)
491#else
492 #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (NULL)
493#endif
494
495#ifdef BLDCFG_HTFABRIC_LIMITS_LIST
496 #define CFG_HTFABRIC_LIMITS_LIST (BLDCFG_HTFABRIC_LIMITS_LIST)
497#else
498 #define CFG_HTFABRIC_LIMITS_LIST (NULL)
499#endif
500
501#ifdef BLDCFG_HTCHAIN_LIMITS_LIST
502 #define CFG_HTCHAIN_LIMITS_LIST (BLDCFG_HTCHAIN_LIMITS_LIST)
503#else
504 #define CFG_HTCHAIN_LIMITS_LIST (NULL)
505#endif
506
507#ifdef BLDCFG_BUS_NUMBERS_LIST
508 #define CFG_BUS_NUMBERS_LIST (BLDCFG_BUS_NUMBERS_LIST)
509#else
510 #define CFG_BUS_NUMBERS_LIST (NULL)
511#endif
512
513#ifdef BLDCFG_IGNORE_LINK_LIST
514 #define CFG_IGNORE_LINK_LIST (BLDCFG_IGNORE_LINK_LIST)
515#else
516 #define CFG_IGNORE_LINK_LIST (NULL)
517#endif
518
519#ifdef BLDCFG_LINK_SKIP_REGANG_LIST
520 #define CFG_LINK_SKIP_REGANG_LIST (BLDCFG_LINK_SKIP_REGANG_LIST)
521#else
522 #define CFG_LINK_SKIP_REGANG_LIST (NULL)
523#endif
524
525#ifdef BLDCFG_SET_HTCRC_SYNC_FLOOD
526 #define CFG_SET_HTCRC_SYNC_FLOOD (BLDCFG_SET_HTCRC_SYNC_FLOOD)
527#else
528 #define CFG_SET_HTCRC_SYNC_FLOOD (FALSE)
529#endif
530
531#ifdef BLDCFG_USE_UNIT_ID_CLUMPING
532 #define CFG_USE_UNIT_ID_CLUMPING (BLDCFG_USE_UNIT_ID_CLUMPING)
533#else
534 #define CFG_USE_UNIT_ID_CLUMPING (FALSE)
535#endif
536
537#ifdef BLDCFG_ADDITIONAL_TOPOLOGIES_LIST
538 #define CFG_ADDITIONAL_TOPOLOGIES_LIST (BLDCFG_ADDITIONAL_TOPOLOGIES_LIST)
539#else
540 #define CFG_ADDITIONAL_TOPOLOGIES_LIST (NULL)
541#endif
542
543#ifdef BLDCFG_USE_HT_ASSIST
544 #define CFG_USE_HT_ASSIST (BLDCFG_USE_HT_ASSIST)
545#else
546 #define CFG_USE_HT_ASSIST (TRUE)
547#endif
548
549#ifdef BLDCFG_USE_ATM_MODE
550 #define CFG_USE_ATM_MODE (BLDCFG_USE_ATM_MODE)
551#else
552 #define CFG_USE_ATM_MODE (TRUE)
553#endif
554
555#ifdef BLDCFG_PLATFORM_CONTROL_FLOW_MODE
556 #define CFG_PLATFORM_CONTROL_FLOW_MODE (BLDCFG_PLATFORM_CONTROL_FLOW_MODE)
557#else
558 #define CFG_PLATFORM_CONTROL_FLOW_MODE (Nfcm)
559#endif
560
561#ifdef BLDCFG_PLATFORM_DEEMPHASIS_LIST
562 #define CFG_PLATFORM_DEEMPHASIS_LIST (BLDCFG_PLATFORM_DEEMPHASIS_LIST)
563#else
564 #define CFG_PLATFORM_DEEMPHASIS_LIST (NULL)
565#endif
566
567#ifdef BLDCFG_VRM_ADDITIONAL_DELAY
568 #define CFG_VRM_ADDITIONAL_DELAY (BLDCFG_VRM_ADDITIONAL_DELAY)
569#else
570 #define CFG_VRM_ADDITIONAL_DELAY (0)
571#endif
572
573#ifdef BLDCFG_VRM_CURRENT_LIMIT
574 #define CFG_VRM_CURRENT_LIMIT BLDCFG_VRM_CURRENT_LIMIT
575#else
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]576 #define CFG_VRM_CURRENT_LIMIT 24000
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]577#endif
578
579#ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD
580 #define CFG_VRM_LOW_POWER_THRESHOLD BLDCFG_VRM_LOW_POWER_THRESHOLD
581#else
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]582 #define CFG_VRM_LOW_POWER_THRESHOLD 24000
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]583#endif
584
585#ifdef BLDCFG_VRM_SLEW_RATE
586 #define CFG_VRM_SLEW_RATE BLDCFG_VRM_SLEW_RATE
587#else
Angel Pons7e577ad2020-05-21 15:14:07 +0200[diff] [blame]588 #define CFG_VRM_SLEW_RATE (5000)
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]589#endif
590
591#ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT
592 #define CFG_VRM_INRUSH_CURRENT_LIMIT BLDCFG_VRM_INRUSH_CURRENT_LIMIT
593#else
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]594 #define CFG_VRM_INRUSH_CURRENT_LIMIT (6000)
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]595#endif
596
597#ifdef BLDCFG_VRM_NB_ADDITIONAL_DELAY
598 #define CFG_VRM_NB_ADDITIONAL_DELAY (BLDCFG_VRM_NB_ADDITIONAL_DELAY)
599#else
600 #define CFG_VRM_NB_ADDITIONAL_DELAY (0)
601#endif
602
603#ifdef BLDCFG_VRM_NB_CURRENT_LIMIT
604 #define CFG_VRM_NB_CURRENT_LIMIT BLDCFG_VRM_NB_CURRENT_LIMIT
605#else
606 #define CFG_VRM_NB_CURRENT_LIMIT (0)
607#endif
608
609#ifdef BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
610 #define CFG_VRM_NB_LOW_POWER_THRESHOLD BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
611#else
612 #define CFG_VRM_NB_LOW_POWER_THRESHOLD (0)
613#endif
614
615#ifdef BLDCFG_VRM_NB_SLEW_RATE
616 #define CFG_VRM_NB_SLEW_RATE BLDCFG_VRM_NB_SLEW_RATE
617#else
Angel Pons7e577ad2020-05-21 15:14:07 +0200[diff] [blame]618 #define CFG_VRM_NB_SLEW_RATE (5000)
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]619#endif
620
621#ifdef BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT
622 #define CFG_VRM_NB_INRUSH_CURRENT_LIMIT BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT
623#else
624 #define CFG_VRM_NB_INRUSH_CURRENT_LIMIT (0)
625#endif
626
627
628#ifdef BLDCFG_PLAT_NUM_IO_APICS
629 #define CFG_PLAT_NUM_IO_APICS BLDCFG_PLAT_NUM_IO_APICS
630#else
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]631 #define CFG_PLAT_NUM_IO_APICS 3
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]632#endif
633
634#ifdef BLDCFG_MEM_INIT_PSTATE
635 #define CFG_MEM_INIT_PSTATE BLDCFG_MEM_INIT_PSTATE
636#else
637 #define CFG_MEM_INIT_PSTATE 0
638#endif
639
640#ifdef BLDCFG_PLATFORM_C1E_MODE
641 #define CFG_C1E_MODE BLDCFG_PLATFORM_C1E_MODE
642#else
643 #define CFG_C1E_MODE C1eModeDisabled
644#endif
645
646#ifdef BLDCFG_PLATFORM_C1E_OPDATA
647 #define CFG_C1E_OPDATA BLDCFG_PLATFORM_C1E_OPDATA
648#else
649 #define CFG_C1E_OPDATA 0
650#endif
651
652#ifdef BLDCFG_PLATFORM_C1E_OPDATA1
653 #define CFG_C1E_OPDATA1 BLDCFG_PLATFORM_C1E_OPDATA1
654#else
655 #define CFG_C1E_OPDATA1 0
656#endif
657
658#ifdef BLDCFG_PLATFORM_C1E_OPDATA2
659 #define CFG_C1E_OPDATA2 BLDCFG_PLATFORM_C1E_OPDATA2
660#else
661 #define CFG_C1E_OPDATA2 0
662#endif
663
664#ifdef BLDCFG_PLATFORM_CSTATE_MODE
665 #define CFG_CSTATE_MODE BLDCFG_PLATFORM_CSTATE_MODE
666#else
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]667 #define CFG_CSTATE_MODE CStateModeC6
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]668#endif
669
670#ifdef BLDCFG_PLATFORM_CSTATE_OPDATA
671 #define CFG_CSTATE_OPDATA BLDCFG_PLATFORM_CSTATE_OPDATA
672#else
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]673 #define CFG_CSTATE_OPDATA 0x840
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]674#endif
675
676#ifdef BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
677 #define CFG_CSTATE_IO_BASE_ADDRESS BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
678#else
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]679 #define CFG_CSTATE_IO_BASE_ADDRESS 0x840
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]680#endif
681
682#ifdef BLDCFG_PLATFORM_CPB_MODE
683 #define CFG_CPB_MODE BLDCFG_PLATFORM_CPB_MODE
684#else
685 #define CFG_CPB_MODE CpbModeAuto
686#endif
687
688#ifdef BLDCFG_CORE_LEVELING_MODE
689 #define CFG_CORE_LEVELING_MODE BLDCFG_CORE_LEVELING_MODE
690#else
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]691 #define CFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]692#endif
693
694#ifdef BLDCFG_AMD_PSTATE_CAP_VALUE
695 #define CFG_AMD_PSTATE_CAP_VALUE BLDCFG_AMD_PSTATE_CAP_VALUE
696#else
697 #define CFG_AMD_PSTATE_CAP_VALUE 0
698#endif
699
700#ifdef BLDCFG_HEAP_DRAM_ADDRESS
701 #define CFG_HEAP_DRAM_ADDRESS BLDCFG_HEAP_DRAM_ADDRESS
702#else
703 #define CFG_HEAP_DRAM_ADDRESS AMD_HEAP_RAM_ADDRESS
704#endif
705
706#ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
707 #define CFG_MEMORY_BUS_FREQUENCY_LIMIT BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
708#else
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]709 #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]710#endif
711
712#ifdef BLDCFG_MEMORY_MODE_UNGANGED
713 #define CFG_MEMORY_MODE_UNGANGED BLDCFG_MEMORY_MODE_UNGANGED
714#else
715 #define CFG_MEMORY_MODE_UNGANGED TRUE
716#endif
717
718#ifdef BLDCFG_MEMORY_QUAD_RANK_CAPABLE
719 #define CFG_MEMORY_QUAD_RANK_CAPABLE BLDCFG_MEMORY_QUAD_RANK_CAPABLE
720#else
721 #define CFG_MEMORY_QUAD_RANK_CAPABLE TRUE
722#endif
723
724#ifdef BLDCFG_MEMORY_QUADRANK_TYPE
725 #define CFG_MEMORY_QUADRANK_TYPE BLDCFG_MEMORY_QUADRANK_TYPE
726#else
Angel Pons7e577ad2020-05-21 15:14:07 +0200[diff] [blame]727 #define CFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]728#endif
729
730#ifdef BLDCFG_MEMORY_RDIMM_CAPABLE
731 #define CFG_MEMORY_RDIMM_CAPABLE BLDCFG_MEMORY_RDIMM_CAPABLE
732#else
733 #define CFG_MEMORY_RDIMM_CAPABLE TRUE
734#endif
735
736#ifdef BLDCFG_MEMORY_LRDIMM_CAPABLE
737 #define CFG_MEMORY_LRDIMM_CAPABLE BLDCFG_MEMORY_LRDIMM_CAPABLE
738#else
739 #define CFG_MEMORY_LRDIMM_CAPABLE TRUE
740#endif
741
742#ifdef BLDCFG_MEMORY_UDIMM_CAPABLE
743 #define CFG_MEMORY_UDIMM_CAPABLE BLDCFG_MEMORY_UDIMM_CAPABLE
744#else
745 #define CFG_MEMORY_UDIMM_CAPABLE TRUE
746#endif
747
748#ifdef BLDCFG_MEMORY_SODIMM_CAPABLE
749 #define CFG_MEMORY_SODIMM_CAPABLE BLDCFG_MEMORY_SODIMM_CAPABLE
750#else
751 #define CFG_MEMORY_SODIMM_CAPABLE FALSE
752#endif
753
754#ifdef BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
755 #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
756#else
757 #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
758#endif
759
760#ifdef BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
761 #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
762#else
763 #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
764#endif
765
766#ifdef BLDCFG_MEMORY_CHANNEL_INTERLEAVING
767 #define CFG_MEMORY_CHANNEL_INTERLEAVING BLDCFG_MEMORY_CHANNEL_INTERLEAVING
768#else
769 #define CFG_MEMORY_CHANNEL_INTERLEAVING TRUE
770#endif
771
772#ifdef BLDCFG_MEMORY_POWER_DOWN
773 #define CFG_MEMORY_POWER_DOWN BLDCFG_MEMORY_POWER_DOWN
774#else
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]775 #define CFG_MEMORY_POWER_DOWN TRUE
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]776#endif
777
778#ifdef BLDCFG_POWER_DOWN_MODE
779 #define CFG_POWER_DOWN_MODE BLDCFG_POWER_DOWN_MODE
780#else
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]781 #define CFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]782#endif
783
784#ifdef BLDCFG_ONLINE_SPARE
785 #define CFG_ONLINE_SPARE BLDCFG_ONLINE_SPARE
786#else
787 #define CFG_ONLINE_SPARE FALSE
788#endif
789
790#ifdef BLDCFG_MEMORY_PARITY_ENABLE
791 #define CFG_MEMORY_PARITY_ENABLE BLDCFG_MEMORY_PARITY_ENABLE
792#else
793 #define CFG_MEMORY_PARITY_ENABLE FALSE
794#endif
795
796#ifdef BLDCFG_BANK_SWIZZLE
797 #define CFG_BANK_SWIZZLE BLDCFG_BANK_SWIZZLE
798#else
799 #define CFG_BANK_SWIZZLE TRUE
800#endif
801
802#ifdef BLDCFG_TIMING_MODE_SELECT
803 #define CFG_TIMING_MODE_SELECT BLDCFG_TIMING_MODE_SELECT
804#else
805 #define CFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
806#endif
807
808#ifdef BLDCFG_MEMORY_CLOCK_SELECT
809 #define CFG_MEMORY_CLOCK_SELECT BLDCFG_MEMORY_CLOCK_SELECT
810#else
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]811 #define CFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]812#endif
813
814#ifdef BLDCFG_DQS_TRAINING_CONTROL
815 #define CFG_DQS_TRAINING_CONTROL BLDCFG_DQS_TRAINING_CONTROL
816#else
817 #define CFG_DQS_TRAINING_CONTROL TRUE
818#endif
819
820#ifdef BLDCFG_IGNORE_SPD_CHECKSUM
821 #define CFG_IGNORE_SPD_CHECKSUM BLDCFG_IGNORE_SPD_CHECKSUM
822#else
823 #define CFG_IGNORE_SPD_CHECKSUM FALSE
824#endif
825
826#ifdef BLDCFG_USE_BURST_MODE
827 #define CFG_USE_BURST_MODE BLDCFG_USE_BURST_MODE
828#else
829 #define CFG_USE_BURST_MODE FALSE
830#endif
831
832#ifdef BLDCFG_MEMORY_ALL_CLOCKS_ON
833 #define CFG_MEMORY_ALL_CLOCKS_ON BLDCFG_MEMORY_ALL_CLOCKS_ON
834#else
835 #define CFG_MEMORY_ALL_CLOCKS_ON FALSE
836#endif
837
838#ifdef BLDCFG_ENABLE_ECC_FEATURE
839 #define CFG_ENABLE_ECC_FEATURE BLDCFG_ENABLE_ECC_FEATURE
840#else
841 #define CFG_ENABLE_ECC_FEATURE TRUE
842#endif
843
844#ifdef BLDCFG_ECC_REDIRECTION
845 #define CFG_ECC_REDIRECTION BLDCFG_ECC_REDIRECTION
846#else
847 #define CFG_ECC_REDIRECTION FALSE
848#endif
849
850#ifdef BLDCFG_SCRUB_DRAM_RATE
851 #define CFG_SCRUB_DRAM_RATE BLDCFG_SCRUB_DRAM_RATE
852#else
Angel Pons7e577ad2020-05-21 15:14:07 +0200[diff] [blame]853 #define CFG_SCRUB_DRAM_RATE (0)
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]854#endif
855
856#ifdef BLDCFG_SCRUB_L2_RATE
857 #define CFG_SCRUB_L2_RATE BLDCFG_SCRUB_L2_RATE
858#else
Angel Pons7e577ad2020-05-21 15:14:07 +0200[diff] [blame]859 #define CFG_SCRUB_L2_RATE (0)
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]860#endif
861
862#ifdef BLDCFG_SCRUB_L3_RATE
863 #define CFG_SCRUB_L3_RATE BLDCFG_SCRUB_L3_RATE
864#else
Angel Pons7e577ad2020-05-21 15:14:07 +0200[diff] [blame]865 #define CFG_SCRUB_L3_RATE (0)
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]866#endif
867
868#ifdef BLDCFG_SCRUB_IC_RATE
869 #define CFG_SCRUB_IC_RATE BLDCFG_SCRUB_IC_RATE
870#else
Angel Pons7e577ad2020-05-21 15:14:07 +0200[diff] [blame]871 #define CFG_SCRUB_IC_RATE (0)
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]872#endif
873
874#ifdef BLDCFG_SCRUB_DC_RATE
875 #define CFG_SCRUB_DC_RATE BLDCFG_SCRUB_DC_RATE
876#else
Angel Pons7e577ad2020-05-21 15:14:07 +0200[diff] [blame]877 #define CFG_SCRUB_DC_RATE (0)
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]878#endif
879
880#ifdef BLDCFG_ECC_SYNC_FLOOD
881 #define CFG_ECC_SYNC_FLOOD BLDCFG_ECC_SYNC_FLOOD
882#else
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame^]883 #define CFG_ECC_SYNC_FLOOD FALSE
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]884#endif
885
886#ifdef BLDCFG_ECC_SYMBOL_SIZE
887 #define CFG_ECC_SYMBOL_SIZE BLDCFG_ECC_SYMBOL_SIZE
888#else
889 #define CFG_ECC_SYMBOL_SIZE 0
890#endif
891
892#ifdef BLDCFG_1GB_ALIGN
893 #define CFG_1GB_ALIGN BLDCFG_1GB_ALIGN
894#else
895 #define CFG_1GB_ALIGN FALSE
896#endif
897
898#ifdef BLDCFG_UMA_ALLOCATION_MODE
899 #define CFG_UMA_MODE BLDCFG_UMA_ALLOCATION_MODE
900#else
901 #define CFG_UMA_MODE UMA_AUTO
902#endif
903
904#ifdef BLDCFG_UMA_ALLOCATION_SIZE
905 #define CFG_UMA_SIZE BLDCFG_UMA_ALLOCATION_SIZE
906#else
907 #define CFG_UMA_SIZE 0
908#endif
909
910#ifdef BLDCFG_UMA_ABOVE4G_SUPPORT
911 #define CFG_UMA_ABOVE4G BLDCFG_UMA_ABOVE4G_SUPPORT
912#else
913 #define CFG_UMA_ABOVE4G FALSE
914#endif
915
916#ifdef BLDCFG_UMA_ALIGNMENT
917 #define CFG_UMA_ALIGNMENT BLDCFG_UMA_ALIGNMENT
918#else
919 #define CFG_UMA_ALIGNMENT NO_UMA_ALIGNED
920#endif
921
922#ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB
923 #define CFG_PROCESSOR_SCOPE_IN_SB BLDCFG_PROCESSOR_SCOPE_IN_SB
924#else
925 #define CFG_PROCESSOR_SCOPE_IN_SB FALSE
926#endif
927
928#ifdef BLDCFG_S3_LATE_RESTORE
929 #define CFG_S3_LATE_RESTORE BLDCFG_S3_LATE_RESTORE
930#else
931 #define CFG_S3_LATE_RESTORE TRUE
932#endif
933
934#ifdef BLDCFG_USE_32_BYTE_REFRESH
935 #define CFG_USE_32_BYTE_REFRESH (BLDCFG_USE_32_BYTE_REFRESH)
936#else
937 #define CFG_USE_32_BYTE_REFRESH (FALSE)
938#endif
939
940#ifdef BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY
941 #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
942#else
943 #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (FALSE)
944#endif
945
946#ifdef BLDCFG_PROCESSOR_SCOPE_NAME0
947 #define CFG_PROCESSOR_SCOPE_NAME0 BLDCFG_PROCESSOR_SCOPE_NAME0
948#else
949 #define CFG_PROCESSOR_SCOPE_NAME0 SCOPE_NAME_VALUE
950#endif
951
952#ifdef BLDCFG_PROCESSOR_SCOPE_NAME1
953 #define CFG_PROCESSOR_SCOPE_NAME1 BLDCFG_PROCESSOR_SCOPE_NAME1
954#else
955 #define CFG_PROCESSOR_SCOPE_NAME1 SCOPE_NAME_VALUE1
956#endif
957
958#ifdef BLDCFG_CFG_GNB_HD_AUDIO
959 #define CFG_GNB_HD_AUDIO BLDCFG_CFG_GNB_HD_AUDIO
960#else
961 #define CFG_GNB_HD_AUDIO TRUE
962#endif
963
964#ifdef BLDCFG_CFG_ABM_SUPPORT
965 #define CFG_ABM_SUPPORT BLDCFG_CFG_ABM_SUPPORT
966#else
967 #define CFG_ABM_SUPPORT FALSE
968#endif
969
970#ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE
971 #define CFG_DINAMIC_REFRESH_RATE BLDCFG_CFG_DYNAMIC_REFRESH_RATE
972#else
973 #define CFG_DYNAMIC_REFRESH_RATE 0
974#endif
975
976#ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
977 #define CFG_LCD_BACK_LIGHT_CONTROL BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
978#else
979 #define CFG_LCD_BACK_LIGHT_CONTROL 0
980#endif
981
982#ifdef BLDCFG_STEREO_3D_PINOUT
983 #define CFG_GNB_STEREO_3D_PINOUT BLDCFG_STEREO_3D_PINOUT
984#else
985 #define CFG_GNB_STEREO_3D_PINOUT 0
986#endif
987
988#ifdef BLDCFG_IGPU_SUBSYSTEM_ID
989 #define CFG_GNB_IGPU_SSID BLDCFG_IGPU_SUBSYSTEM_ID
990#else
991 #define CFG_GNB_IGPU_SSID 0
992#endif
993
994#ifdef BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
995 #define CFG_GNB_HDAUDIO_SSID BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
996#else
997 #define CFG_GNB_HDAUDIO_SSID 0
998#endif
999
1000#ifdef BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
1001 #define CFG_GNB_PCIE_SSID BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
1002#else
1003 #define CFG_GNB_PCIE_SSID 0x12341022
1004#endif
1005
1006#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
1007 #define CFG_GFX_LVDS_SPREAD_SPECTRUM BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
1008#else
1009 #define CFG_GFX_LVDS_SPREAD_SPECTRUM 0
1010#endif
1011
1012#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
1013 #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
1014#else
1015 #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE 0
1016#endif
1017
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]1018#ifdef BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
1019 #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
1020#else
1021 #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM 0
1022#endif
1023
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1024#ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
1025 #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
1026#else
1027 #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000
1028#endif
1029
1030#ifdef BLDOPT_REMOVE_EARLY_SAMPLES
1031 #if BLDOPT_REMOVE_EARLY_SAMPLES == TRUE
1032 #undef OPTION_EARLY_SAMPLES
1033 #define OPTION_EARLY_SAMPLES FALSE
1034 #else
1035 #undef OPTION_EARLY_SAMPLES
1036 #define OPTION_EARLY_SAMPLES TRUE
1037 #endif
1038#endif
1039
1040#ifdef BLDOPT_REMOVE_ALIB
1041 #if BLDOPT_REMOVE_ALIB == TRUE
1042 #undef OPTION_ALIB
1043 #define OPTION_ALIB FALSE
1044 #else
1045 #undef OPTION_ALIB
1046 #define OPTION_ALIB TRUE
1047 #endif
1048#endif
1049
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]1050#ifdef BLDCFG_LVDS_MISC_888_FPDI_MODE
1051 #define CFG_LVDS_MISC_888_FPDI_MODE BLDCFG_LVDS_MISC_888_FPDI_MODE
1052#else
1053 #define CFG_LVDS_MISC_888_FPDI_MODE FALSE
1054#endif
1055
1056#ifdef BLDCFG_LVDS_MISC_DL_CH_SWAP
1057 #define CFG_LVDS_MISC_DL_CH_SWAP BLDCFG_LVDS_MISC_DL_CH_SWAP
1058#else
1059 #define CFG_LVDS_MISC_DL_CH_SWAP FALSE
1060#endif
1061
1062#ifdef BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
1063 #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
1064#else
1065 #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW FALSE
1066#endif
1067
1068#ifdef BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
1069 #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
1070#else
1071 #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW FALSE
1072#endif
1073
1074#ifdef BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
1075 #define CFG_LVDS_MISC_BLON_ACTIVE_LOW BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
1076#else
1077 #define CFG_LVDS_MISC_BLON_ACTIVE_LOW FALSE
1078#endif
Kyösti Mälkki206e1572016-05-18 14:04:45 +0300[diff] [blame]1079
1080#ifdef BLDCFG_PLATFORM_POWER_POLICY_MODE
1081 #define CFG_PLATFORM_POWER_POLICY_MODE (BLDCFG_PLATFORM_POWER_POLICY_MODE)
1082#else
1083 #define CFG_PLATFORM_POWER_POLICY_MODE (Performance)
1084#endif
1085
Angel Pons5f823702020-05-21 01:06:28 +0200[diff] [blame]1086#define CFG_PCI_MMIO_BASE (CONFIG_MMCONF_BASE_ADDRESS)
Kyösti Mälkki206e1572016-05-18 14:04:45 +0300[diff] [blame]1087
Angel Pons5f823702020-05-21 01:06:28 +0200[diff] [blame]1088#define CFG_PCI_MMIO_SIZE (CONFIG_MMCONF_BUS_NUMBER)
Kyösti Mälkki206e1572016-05-18 14:04:45 +0300[diff] [blame]1089
1090#ifdef BLDCFG_AP_MTRR_SETTINGS_LIST
1091 #define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST)
1092#else
Angel Pons41b820c2020-05-21 00:58:33 +0200[diff] [blame]1093 #define CFG_AP_MTRR_SETTINGS_LIST (&OntarioApMtrrSettingsList)
Kyösti Mälkki206e1572016-05-18 14:04:45 +0300[diff] [blame]1094#endif
1095
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1096/*---------------------------------------------------------------------------
1097 * Processing the options: Third, perform the option cross checks
1098 *--------------------------------------------------------------------------*/
Angel Pons5f823702020-05-21 01:06:28 +0200[diff] [blame]1099// Check that deprecated options are not used
1100#ifdef BLDCFG_PCI_MMIO_BASE
1101 #error BLDOPT: BLDCFG_PCI_MMIO_BASE has been deprecated in coreboot. Do not use!
1102#endif
1103#ifdef BLDCFG_PCI_MMIO_SIZE
1104 #error BLDOPT: BLDCFG_PCI_MMIO_SIZE has been deprecated in coreboot. Do not use!
1105#endif
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1106// Assure that at least one type of memory support is included
1107#if OPTION_UDIMMS == FALSE
1108 #if OPTION_RDIMMS == FALSE
1109 #if OPTION_SODIMMS == FALSE
1110 #if OPTION_LRDIMMS == FALSE
1111 #error BLDOPT: No DIMM support selected. Either BLDOPT_REMOVE_UDIMMS_SUPPORT or BLDOPT_REMOVE_RDIMMS_SUPPORT or BLDOPT_REMOVE_SODIMMS_SUPPORT or BLDOPT_REMOVE_LRDIMMS_SUPPORT must be FALSE.
1112 #endif
1113 #endif
1114 #endif
1115#endif
1116// Ensure at least one dimm type is capable
1117#if CFG_MEMORY_RDIMM_CAPABLE == FALSE
1118 #if CFG_MEMORY_UDIMM_CAPABLE == FALSE
1119 #if CFG_MEMORY_SODIMM_CAPABLE == FALSE
1120 #if CFG_MEMORY_LRDIMM_CAPABLE == FALSE
1121 #error BLDCFG: No dimm type is capable
1122 #endif
1123 #endif
1124 #endif
1125#endif
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1126// Turn off multi-socket based features if only one node...
1127#if OPTION_MULTISOCKET == FALSE
1128 #undef OPTION_PARALLEL_TRAINING
1129 #define OPTION_PARALLEL_TRAINING FALSE
1130 #undef OPTION_NODE_INTERLEAVE
1131 #define OPTION_NODE_INTERLEAVE FALSE
1132#endif
1133// Ensure that at least one write leveling option is selected
1134#if OPTION_DDR3 == TRUE
1135 #if OPTION_HW_WRITE_LEV_TRAINING == FALSE
1136 #if OPTION_SW_WRITE_LEV_TRAINING == FALSE
1137 #error No Write leveling option selected for DDR3
1138 #endif
1139 #endif
1140 #if OPTION_SW_DRAM_INIT == FALSE
1141 #error Software dram init must be enabled for DDR3 dimms
1142 #endif
1143#endif
1144// Ensure at least one DQS receiver training option is selected
1145#if OPTION_HW_DQS_REC_EN_TRAINING == FALSE
1146 #if OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == FALSE
1147 #if OPTION_OPT_SW_DQS_REC_EN_TRAINING == FALSE
1148 #error No DQS receiver training option has been slected
1149 #endif
1150 #endif
1151#endif
1152// Ensure at least one Rd Wr position training option has been selected
1153#if OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == FALSE
1154 #if OPTION_OPT_SW_RD_WR_POS_TRAINING == FALSE
1155 #error No Rd Wr position training option has been selected
1156 #endif
1157#endif
1158// Ensure at least one dram init option has been selected
1159#if OPTION_HW_DRAM_INIT == FALSE
1160 #if OPTION_SW_DRAM_INIT == FALSE
1161 #error No Dram init option has been selected
1162 #endif
1163#endif
1164// Ensure the frequency limit is valid
1165#if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1866_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 933)
1166 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 800)
1167 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1333_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 667)
1168 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1066_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 533)
1169 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR800_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 400)
1170 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR667_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 333)
1171 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR533_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 266)
1172 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR400_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 200)
1173 #error BLDCFG: Unsupported memory bus frequency
1174 #endif
1175 #endif
1176 #endif
1177 #endif
1178 #endif
1179 #endif
1180 #endif
1181#endif
1182// Ensure timing mode is valid
1183#if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC
1184 #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED
1185 #if CFG_TIMING_MODE_SELECT != TIMING_MODE_AUTO
1186 #error BLDCFG: Invalid timing mode is set
1187 #endif
1188 #endif
1189#endif
1190// Ensure the scrub rate is valid
1191#if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF))
1192 #error BLDCFG: Unsupported dram scrub rate set
1193#endif
1194#if CFG_SCRUB_L2_RATE > 0x16
1195 #error BLDCFG: Unsupported L2 scrubber rate set
1196#endif
1197#if CFG_SCRUB_L3_RATE > 0x16
1198 #error BLDCFG: unsupported L3 scrubber rate set
1199#endif
1200#if CFG_SCRUB_IC_RATE > 0x16
1201 #error BLDCFG: Unsupported Instruction cache scrub rate set
1202#endif
1203#if CFG_SCRUB_DC_RATE > 0x16
1204 #error BLDCFG: Unsupported Dcache scrub rate set
1205#endif
1206// Ensure Quad rank dimm type is valid
1207#if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED
1208 #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED
1209 #error BLDCFG: Invalid quad rank dimm type set
1210 #endif
1211#endif
1212// Ensure ECC symbol size is valid
1213#if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG
1214 #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4
1215 #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X8
1216 #error BLDCFG: Invalid Ecc symbol size set
1217 #endif
1218 #endif
1219#endif
1220// Ensure power down mode is valid
1221#if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT
1222 #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL
1223 #error BLDCFG: Invalid power down mode set
1224 #endif
1225#endif
1226
1227/*****************************************************************************
1228 *
1229 * Process the option logic, setting local control variables
1230 *
1231 ****************************************************************************/
1232#if OPTION_ACPI_PSTATES == TRUE
1233 #define OPTFCN_ACPI_TABLES CreateAcpiTablesMain
1234 #define OPTFCN_GATHER_DATA PStateGatherData
1235 #if OPTION_MULTISOCKET == TRUE
1236 #define OPTFCN_PSTATE_LEVELING PStateLeveling
1237 #else
1238 #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess
1239 #endif
1240#else
1241 #define OPTFCN_ACPI_TABLES CommonReturnAgesaSuccess
1242 #define OPTFCN_GATHER_DATA CommonReturnAgesaSuccess
1243 #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess
1244#endif
1245
1246
1247/*****************************************************************************
1248 *
1249 * Include the structure definitions for the defaults table structures
1250 *
1251 ****************************************************************************/
Kyösti Mälkki062ef1c2016-04-19 15:18:02 +0300[diff] [blame]1252#include <CommonReturns.h>
1253#include <agesa-entry-cfg.h>
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1254#include "Options.h"
1255#include "OptionCpuFamiliesInstall.h"
1256#include "OptionsHt.h"
1257#include "OptionHtInstall.h"
1258#include "OptionMemory.h"
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1259#include "OptionMemoryInstall.h"
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1260#include "OptionCpuFeaturesInstall.h"
1261#include "OptionDmi.h"
1262#include "OptionDmiInstall.h"
1263#include "OptionPstate.h"
1264#include "OptionPstateInstall.h"
1265#include "OptionWhea.h"
1266#include "OptionWheaInstall.h"
1267#include "OptionSrat.h"
1268#include "OptionSratInstall.h"
1269#include "OptionSlit.h"
1270#include "OptionSlitInstall.h"
1271#include "OptionMultiSocket.h"
1272#include "OptionMultiSocketInstall.h"
1273#include "OptionIdsInstall.h"
1274#include "OptionGfxRecovery.h"
1275#include "OptionGfxRecoveryInstall.h"
1276#include "OptionGnb.h"
1277#include "OptionGnbInstall.h"
1278#include "OptionS3ScriptInstall.h"
1279
1280
1281/*****************************************************************************
1282 *
1283 * Generate the output structures (defaults tables)
1284 *
1285 ****************************************************************************/
1286BUILD_OPT_CFG UserOptions = {
1287 { // AGESA version string
1288 AGESA_CODE_SIGNATURE, // code header Signature
1289 AGESA_PACKAGE_STRING, // 8 character ID
1290 AGESA_VERSION_STRING, // 12 character version string
1291 0 // null string terminator
1292 },
1293 //Build Option Area
1294 OPTION_UDIMMS, //UDIMMS
1295 OPTION_RDIMMS, //RDIMMS
1296 OPTION_LRDIMMS, //LRDIMMS
1297 OPTION_ECC, //ECC
1298 OPTION_BANK_INTERLEAVE, //BANK_INTERLEAVE
1299 OPTION_DCT_INTERLEAVE, //DCT_INTERLEAVE
1300 OPTION_NODE_INTERLEAVE, //NODE_INTERLEAVE
1301 OPTION_PARALLEL_TRAINING, //PARALLEL_TRAINING
1302 OPTION_ONLINE_SPARE, //ONLINE_SPARE
1303 OPTION_MEM_RESTORE, //MEM CONTEXT RESTORE
1304 OPTION_MULTISOCKET, //MULTISOCKET
1305 OPTION_ACPI_PSTATES, //ACPI_PSTATES
1306 OPTION_SRAT, //SRAT
1307 OPTION_SLIT, //SLIT
1308 OPTION_WHEA, //WHEA
1309 OPTION_DMI, //DMI
1310 OPTION_EARLY_SAMPLES, //EARLY_SAMPLES
1311 OPTION_ADDR_TO_CS_TRANSLATOR, //ADDR_TO_CS_TRANSLATOR
1312
1313 //Build Configuration Area
1314 CFG_PCI_MMIO_BASE,
1315 CFG_PCI_MMIO_SIZE,
1316 {
1317 // CoreVrm
1318 {
1319 CFG_VRM_CURRENT_LIMIT, // VrmCurrentLimit
1320 CFG_VRM_LOW_POWER_THRESHOLD, // VrmLowPowerThershold
1321 CFG_VRM_SLEW_RATE, // VrmSlewRate
1322 CFG_VRM_ADDITIONAL_DELAY, // VrmAdditionalDelay
1323 CFG_VRM_HIGH_SPEED_ENABLE, // VrmHiSpeedEnable
1324 CFG_VRM_INRUSH_CURRENT_LIMIT // VrmInrushCurrentLimit
1325 },
1326 // NbVrm
1327 {
1328 CFG_VRM_NB_CURRENT_LIMIT, // VrmNbCurrentLimit
1329 CFG_VRM_NB_LOW_POWER_THRESHOLD, // VrmNbLowPowerThershold
1330 CFG_VRM_NB_SLEW_RATE, // VrmNbSlewRate
1331 CFG_VRM_NB_ADDITIONAL_DELAY, // VrmNbAdditionalDelay
1332 CFG_VRM_NB_HIGH_SPEED_ENABLE, // VrmNbHiSpeedEnable
1333 CFG_VRM_NB_INRUSH_CURRENT_LIMIT // VrmNbInrushCurrentLimit
1334 }
1335 },
1336 CFG_PLAT_NUM_IO_APICS, //PlatformApicIoNumber
1337 CFG_MEM_INIT_PSTATE, //MemoryInitPstate
1338 CFG_C1E_MODE, //C1eMode
1339 CFG_C1E_OPDATA, //C1ePlatformData
1340 CFG_C1E_OPDATA1, //C1ePlatformData1
1341 CFG_C1E_OPDATA2, //C1ePlatformData2
1342 CFG_CSTATE_MODE, //CStateMode
1343 CFG_CSTATE_OPDATA, //CStatePlatformData
1344 CFG_CSTATE_IO_BASE_ADDRESS, //CStateIoBaseAddress
1345 CFG_CPB_MODE, //CpbMode
1346 CFG_CORE_LEVELING_MODE, //CoreLevelingCofig
1347 {
1348 CFG_PLATFORM_CONTROL_FLOW_MODE, // The platform's control flow mode.
1349 CFG_USE_HT_ASSIST, // CfgUseHtAssist
1350 CFG_USE_ATM_MODE, // CfgUseAtmMode
1351 CFG_USE_32_BYTE_REFRESH, // Display Refresh uses 32 byte packets.
1352 CFG_USE_VARIABLE_MCT_ISOC_PRIORITY, // The Memory controller will be set to Variable Isoc Priority.
1353 CFG_PLATFORM_POWER_POLICY_MODE // The platform's power policy mode.
1354 },
1355 (CPU_HT_DEEMPHASIS_LEVEL *)CFG_PLATFORM_DEEMPHASIS_LIST, // Deemphasis settings
1356 CFG_AMD_PLATFORM_TYPE, //AmdPlatformType
1357 CFG_AMD_PSTATE_CAP_VALUE, // Amd pstate ceiling enabling deck
1358
1359 CFG_MEMORY_BUS_FREQUENCY_LIMIT, // CfgMemoryBusFrequencyLimit
1360 CFG_MEMORY_MODE_UNGANGED, // CfgMemoryModeUnganged
1361 CFG_MEMORY_QUAD_RANK_CAPABLE, // CfgMemoryQuadRankCapable
1362 CFG_MEMORY_QUADRANK_TYPE, // CfgMemoryQuadrankType
1363 CFG_MEMORY_RDIMM_CAPABLE, // CfgMemoryRDimmCapable
1364 CFG_MEMORY_LRDIMM_CAPABLE, // CfgMemoryLRDimmCapable
1365 CFG_MEMORY_UDIMM_CAPABLE, // CfgMemoryUDimmCapable
1366 CFG_MEMORY_SODIMM_CAPABLE, // CfgMemorySodimmCapable
1367 CFG_MEMORY_ENABLE_BANK_INTERLEAVING, // CfgMemoryEnableBankInterleaving
1368 CFG_MEMORY_ENABLE_NODE_INTERLEAVING, // CfgMemoryEnableNodeInterleaving
1369 CFG_MEMORY_CHANNEL_INTERLEAVING, // CfgMemoryChannelInterleaving
1370 CFG_MEMORY_POWER_DOWN, // CfgMemoryPowerDown
1371 CFG_POWER_DOWN_MODE, // CfgPowerDownMode
1372 CFG_ONLINE_SPARE, // CfgOnlineSpare
1373 CFG_MEMORY_PARITY_ENABLE, // CfgMemoryParityEnable
1374 CFG_BANK_SWIZZLE, // CfgBankSwizzle
1375 CFG_TIMING_MODE_SELECT, // CfgTimingModeSelect
1376 CFG_MEMORY_CLOCK_SELECT, // CfgMemoryClockSelect
1377 CFG_DQS_TRAINING_CONTROL, // CfgDqsTrainingControl
1378 CFG_IGNORE_SPD_CHECKSUM, // CfgIgnoreSpdChecksum
1379 CFG_USE_BURST_MODE, // CfgUseBurstMode
1380 CFG_MEMORY_ALL_CLOCKS_ON, // CfgMemoryAllClocksOn
1381 CFG_ENABLE_ECC_FEATURE, // CfgEnableEccFeature
1382 CFG_ECC_REDIRECTION, // CfgEccRedirection
1383 CFG_SCRUB_DRAM_RATE, // CfgScrubDramRate
1384 CFG_SCRUB_L2_RATE, // CfgScrubL2Rate
1385 CFG_SCRUB_L3_RATE, // CfgScrubL3Rate
1386 CFG_SCRUB_IC_RATE, // CfgScrubIcRate
1387 CFG_SCRUB_DC_RATE, // CfgScrubDcRate
1388 CFG_ECC_SYNC_FLOOD, // CfgEccSyncFlood
1389 CFG_ECC_SYMBOL_SIZE, // CfgEccSymbolSize
1390 CFG_HEAP_DRAM_ADDRESS, // CfgHeapDramAddress
1391 CFG_1GB_ALIGN, // CfgNodeMem1GBAlign
1392 CFG_S3_LATE_RESTORE, // CfgS3LateRestore
1393 CFG_ACPI_PSTATE_PSD_INDPX, // CfgAcpiPstateIndependent
1394 (AP_MTRR_SETTINGS *) CFG_AP_MTRR_SETTINGS_LIST, // CfgApMtrrSettingsList
1395 CFG_UMA_MODE, // CfgUmaMode
1396 CFG_UMA_SIZE, // CfgUmaSize
1397 CFG_UMA_ABOVE4G, // CfgUmaAbove4G
1398 CFG_UMA_ALIGNMENT, // CfgUmaAlignment
1399 CFG_PROCESSOR_SCOPE_IN_SB, // CfgProcessorScopeInSb
1400 CFG_PROCESSOR_SCOPE_NAME0, // CfgProcessorScopeName0
1401 CFG_PROCESSOR_SCOPE_NAME1, // CfgProcessorScopeName1
1402 CFG_GNB_HD_AUDIO, // CfgGnbHdAudio
1403 CFG_ABM_SUPPORT, // CfgAbmSupport
1404 CFG_DYNAMIC_REFRESH_RATE, // CfgDynamicRefreshRate
1405 CFG_LCD_BACK_LIGHT_CONTROL, // CfgLcdBackLightControl
1406 CFG_GNB_STEREO_3D_PINOUT, // CfgGnb3dStereoPinIndex
1407 CFG_TEMP_PCIE_MMIO_BASE_ADDRESS, // CfgTempPcieMmioBaseAddress
1408 CFG_GNB_IGPU_SSID, // CfgGnbIGPUSSID
1409 CFG_GNB_HDAUDIO_SSID, // CfgGnbHDAudioSSID
1410 CFG_GNB_PCIE_SSID, // CfgGnbPcieSSID
1411 CFG_GFX_LVDS_SPREAD_SPECTRUM, // CfgLvdsSpreadSpectrum
1412 CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE, // CfgLvdsSpreadSpectrumRate
1413
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]1414 {{
1415 CFG_LVDS_MISC_888_FPDI_MODE, // CfgLvdsMiscControl
1416 CFG_LVDS_MISC_DL_CH_SWAP, // CfgLvdsMiscControl
1417 CFG_LVDS_MISC_VSYNC_ACTIVE_LOW, // CfgLvdsMiscControl
1418 CFG_LVDS_MISC_HSYNC_ACTIVE_LOW, // CfgLvdsMiscControl
1419 CFG_LVDS_MISC_BLON_ACTIVE_LOW, // CfgLvdsMiscControl
1420 }},
1421 CFG_PCIE_REFCLK_SPREAD_SPECTRUM, // CfgPcieRefClkSpreadSpectrum
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1422 0, //reserved...
1423};
1424
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1425
1426CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] =
1427{
1428 IDS_LATE_RUN_AP_TASK
1429 // Get DMI info
1430 CPU_DMI_AP_GET_TYPE4_TYPE7
1431 // Probe filter enable
1432 HT_ASSIST_AP_DISABLE_CACHE
1433 HT_ASSIST_AP_ENABLE_CACHE
1434
1435 { 0, NULL }
1436};
1437
1438#if AGESA_ENTRY_INIT_RESET == TRUE
1439 #if IDSOPT_IDS_ENABLED == TRUE
1440 #if IDSOPT_TRACING_ENABLED == TRUE
1441 #define MAKE_DBG_STR(x, y) MAKE_AS_A_STRING(x : y)
1442 CONST CHAR8 *BldOptDebugOutput[] = {
1443 #if IDS_TRACE_SHOW_BLD_OPT_CFG == TRUE
1444 //Build Option Area
1445 MAKE_DBG_STR (\nOptUDIMM, OPTION_UDIMMS)
1446 MAKE_DBG_STR (\nOptRDIMM, OPTION_RDIMMS)
1447 MAKE_DBG_STR (\nOptLRDIMM, OPTION_LRDIMMS)
1448 MAKE_DBG_STR (\nOptECC, OPTION_ECC)
1449 MAKE_DBG_STR (\nOptCsIntlv, OPTION_BANK_INTERLEAVE)
1450 MAKE_DBG_STR (\nOptDctIntlv, OPTION_DCT_INTERLEAVE)
1451 MAKE_DBG_STR (\nOptNodeIntlv, OPTION_NODE_INTERLEAVE)
1452 //MAKE_DBG_STR (\nOptParallelTraining, OPTION_PARALLEL_TRAINING)
1453 MAKE_DBG_STR (\nOptOnlineSpare, OPTION_ONLINE_SPARE)
1454 MAKE_DBG_STR (\nOptAddr2CsTranslator, OPTION_ADDR_TO_CS_TRANSLATOR)
1455 MAKE_DBG_STR (\nOptMemRestore, OPTION_MEM_RESTORE)
1456 MAKE_DBG_STR (\nOptMultiSocket, OPTION_MULTISOCKET)
1457 MAKE_DBG_STR (\nOptPstates, OPTION_ACPI_PSTATES)
1458 MAKE_DBG_STR (\nOptSRAT, OPTION_SRAT)
1459 MAKE_DBG_STR (\nOptSLIT, OPTION_SLIT)
1460 MAKE_DBG_STR (\nOptWHEA, OPTION_WHEA)
1461 MAKE_DBG_STR (\nOptDMI, OPTION_DMI)
1462 MAKE_DBG_STR (\nOptEarlySamples, OPTION_EARLY_SAMPLES),
1463
1464 //Build Configuration Area
1465 // CoreVrm
1466 MAKE_DBG_STR (\nVrmCurrentLimit , CFG_VRM_CURRENT_LIMIT)
1467 MAKE_DBG_STR (\nVrmLowPowerThreshold , CFG_VRM_LOW_POWER_THRESHOLD)
1468 MAKE_DBG_STR (\nVrmSlewRate , CFG_VRM_SLEW_RATE)
1469 MAKE_DBG_STR (\nVrmAdditionalDelay , CFG_VRM_ADDITIONAL_DELAY)
1470 MAKE_DBG_STR (\nVrmHiSpeedEnable , CFG_VRM_HIGH_SPEED_ENABLE)
1471 MAKE_DBG_STR (\nVrmInrushCurrentLimit, CFG_VRM_INRUSH_CURRENT_LIMIT)
1472 // NbVrm
1473 MAKE_DBG_STR (\nNbVrmCurrentLimit , CFG_VRM_NB_CURRENT_LIMIT)
1474 MAKE_DBG_STR (\nNbVrmLowPowerThreshold , CFG_VRM_NB_LOW_POWER_THRESHOLD)
1475 MAKE_DBG_STR (\nNbVrmSlewRate , CFG_VRM_NB_SLEW_RATE)
1476 MAKE_DBG_STR (\nNbVrmAdditionalDelay , CFG_VRM_NB_ADDITIONAL_DELAY)
1477 MAKE_DBG_STR (\nNbVrmHiSpeedEnable , CFG_VRM_NB_HIGH_SPEED_ENABLE)
1478 MAKE_DBG_STR (\nNbVrmInrushCurrentLimit, CFG_VRM_NB_INRUSH_CURRENT_LIMIT),
1479
1480 MAKE_DBG_STR (\nNumIoApics , CFG_PLAT_NUM_IO_APICS)
1481 MAKE_DBG_STR (\nMemInitPstate , CFG_MEM_INIT_PSTATE)
1482 MAKE_DBG_STR (\nC1eMode , CFG_C1E_MODE)
1483 MAKE_DBG_STR (\nC1eOpData , CFG_C1E_OPDATA)
1484 MAKE_DBG_STR (\nC1eOpdata1 , CFG_C1E_OPDATA1)
1485 MAKE_DBG_STR (\nC1eOpdata2 , CFG_C1E_OPDATA2)
1486 MAKE_DBG_STR (\nCStateMode , CFG_CSTATE_MODE)
1487 MAKE_DBG_STR (\nCStateOpData , CFG_CSTATE_OPDATA)
1488 MAKE_DBG_STR (\nCStateIoBaseAddr , CFG_CSTATE_IO_BASE_ADDRESS)
1489 MAKE_DBG_STR (\nCpbMode , CFG_CPB_MODE)
1490 MAKE_DBG_STR (\nCoreLevelingMode , CFG_CORE_LEVELING_MODE),
1491
1492 MAKE_DBG_STR (\nControlFlowMode , CFG_PLATFORM_CONTROL_FLOW_MODE)
1493 MAKE_DBG_STR (\nUseHtAssist , CFG_USE_HT_ASSIST)
1494 MAKE_DBG_STR (\nUseAtmMode , CFG_USE_ATM_MODE)
1495 MAKE_DBG_STR (\nUse32ByteRefresh , CFG_USE_32_BYTE_REFRESH)
1496 MAKE_DBG_STR (\nUseVarMctIsocPriority , CFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
1497 MAKE_DBG_STR (\nPowerPolicy , CFG_PLATFORM_POWER_POLICY_MOD)
1498
1499 MAKE_DBG_STR (\nDeemphasisList , CFG_PLATFORM_DEEMPHASIS_LIST)
1500
1501 MAKE_DBG_STR (\nPciMmioAddr , CFG_PCI_MMIO_BASE)
1502 MAKE_DBG_STR (\nPciMmioSize , CFG_PCI_MMIO_SIZE)
1503 MAKE_DBG_STR (\nPlatformType , CFG_AMD_PLATFORM_TYPE)
1504 MAKE_DBG_STR (\nPstateCapValue , CFG_AMD_PSTATE_CAP_VALUE),
1505
1506 MAKE_DBG_STR (\nMemBusFreqLimit , CFG_MEMORY_BUS_FREQUENCY_LIMIT)
1507 MAKE_DBG_STR (\nTimingModeSelect , CFG_TIMING_MODE_SELECT)
1508 MAKE_DBG_STR (\nMemoryClockSelect , CFG_MEMORY_CLOCK_SELECT)
1509
1510 MAKE_DBG_STR (\nMemUnganged , CFG_MEMORY_MODE_UNGANGED)
1511 MAKE_DBG_STR (\nQRCap , CFG_MEMORY_QUAD_RANK_CAPABLE)
1512 MAKE_DBG_STR (\nQRType , CFG_MEMORY_QUADRANK_TYPE)
1513 MAKE_DBG_STR (\nRDimmCap , CFG_MEMORY_RDIMM_CAPABLE)
1514 MAKE_DBG_STR (\nLRDimmCap , CFG_MEMORY_LRDIMM_CAPABLE)
1515 MAKE_DBG_STR (\nUDimmCap , CFG_MEMORY_UDIMM_CAPABLE)
1516 MAKE_DBG_STR (\nSODimmCap , CFG_MEMORY_SODIMM_CAPABLE)
1517 MAKE_DBG_STR (\nDqsTrainingControl , CFG_DQS_TRAINING_CONTROL)
1518 MAKE_DBG_STR (\nIgnoreSpdChecksum , CFG_IGNORE_SPD_CHECKSUM)
1519 MAKE_DBG_STR (\nUseBurstMode , CFG_USE_BURST_MODE)
1520 MAKE_DBG_STR (\nAllMemClkOn , CFG_MEMORY_ALL_CLOCKS_ON),
1521
1522 MAKE_DBG_STR (\nPowerDownEn , CFG_MEMORY_POWER_DOWN)
1523 MAKE_DBG_STR (\nPowerDownMode , CFG_POWER_DOWN_MODE)
1524 MAKE_DBG_STR (\nOnlineSpare , CFG_ONLINE_SPARE)
1525 MAKE_DBG_STR (\nAddrParityEn , CFG_MEMORY_PARITY_ENABLE)
1526 MAKE_DBG_STR (\nBankSwizzle , CFG_BANK_SWIZZLE)
1527 MAKE_DBG_STR (\nCsIntlvEn , CFG_MEMORY_ENABLE_BANK_INTERLEAVING)
1528 MAKE_DBG_STR (\nNodeIntlvEn , CFG_MEMORY_ENABLE_NODE_INTERLEAVING)
1529 MAKE_DBG_STR (\nDctIntlvEn , CFG_MEMORY_CHANNEL_INTERLEAVING),
1530
1531 MAKE_DBG_STR (\nUmaMode , CFG_UMA_MODE)
1532 MAKE_DBG_STR (\nUmaSize , CFG_UMA_SIZE)
1533 MAKE_DBG_STR (\nUmaAbove4G , CFG_UMA_ABOVE4G)
1534 MAKE_DBG_STR (\nUmaAlignment , CFG_UMA_ALIGNMENT)
1535
1536 MAKE_DBG_STR (\nEccEn , CFG_ENABLE_ECC_FEATURE)
1537 MAKE_DBG_STR (\nEccRedirect , CFG_ECC_REDIRECTION)
1538 MAKE_DBG_STR (\nScrubDramRate , CFG_SCRUB_DRAM_RATE)
1539 MAKE_DBG_STR (\nScrubL2Rate , CFG_SCRUB_L2_RATE)
1540 MAKE_DBG_STR (\nScrubL3Rate , CFG_SCRUB_L3_RATE)
1541 MAKE_DBG_STR (\nScrubIcRate , CFG_SCRUB_IC_RATE)
1542 MAKE_DBG_STR (\nScrubDcRate , CFG_SCRUB_DC_RATE)
1543 MAKE_DBG_STR (\nEccSyncFlood , CFG_ECC_SYNC_FLOOD)
1544 MAKE_DBG_STR (\nEccSymbolSize , CFG_ECC_SYMBOL_SIZE)
1545 MAKE_DBG_STR (\nHeapDramAddress , CFG_HEAP_DRAM_ADDRESS)
1546 MAKE_DBG_STR (\nNodeMem1GBAlign , CFG_1GB_ALIGN),
1547
1548 MAKE_DBG_STR (\nS3LateRestore , CFG_S3_LATE_RESTORE)
1549 MAKE_DBG_STR (\nAcpiPstateIndependent , CFG_ACPI_PSTATE_PSD_INDPX)
1550
1551 MAKE_DBG_STR (\nApMtrrSettingsList , CFG_AP_MTRR_SETTINGS_LIST)
1552
1553 MAKE_DBG_STR (\nProcessorScopeInSb , CFG_PROCESSOR_SCOPE_IN_SB)
1554 MAKE_DBG_STR (\nProcessorScopeName0 , CFG_PROCESSOR_SCOPE_NAME0)
1555 MAKE_DBG_STR (\nProcessorScopeName1 , CFG_PROCESSOR_SCOPE_NAME1)
1556 MAKE_DBG_STR (\nGnbHdAudio , CFG_GNB_HD_AUDIO)
1557 MAKE_DBG_STR (\nAbmSupport , CFG_ABM_SUPPORT)
1558 MAKE_DBG_STR (\nDynamicRefreshRate , CFG_DYNAMIC_REFRESH_RATE)
1559 MAKE_DBG_STR (\nLcdBackLightControl , CFG_LCD_BACK_LIGHT_CONTROL)
1560 MAKE_DBG_STR (\nGnb3dStereoPinIndex , CFG_GNB_STEREO_3D_PINOUT)
1561 MAKE_DBG_STR (\nTempPcieMmioBaseAddress, CFG_TEMP_PCIE_MMIO_BASE_ADDRESS),
1562 MAKE_DBG_STR (\nCfgGnbIGPUSSID , CFG_GNB_IGPU_SSID),
1563 MAKE_DBG_STR (\nCfgGnbHDAudioSSID , CFG_GNB_HDAUDIO_SSID),
1564 MAKE_DBG_STR (\nCfgGnbPcieSSID , CFG_GNB_PCIE_SSID),
1565
1566 MAKE_DBG_STR (\nCfgLvdsSpreadSpectrum , CFG_GFX_LVDS_SPREAD_SPECTRUM),
1567 MAKE_DBG_STR (\nCfgLvdsSpreadSpectrumRate , CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE),
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]1568 MAKE_DBG_STR (\nCfgLvdsMiscControl.FpdiMode , CFG_LVDS_MISC_888_FPDI_MODE),
1569 MAKE_DBG_STR (\nCfgLvdsMiscControl.DlChSwap , CFG_LVDS_MISC_DL_CH_SWAP),
1570 MAKE_DBG_STR (\nCfgLvdsMiscControl.VsyncActiveLow , CFG_LVDS_MISC_VSYNC_ACTIVE_LOW),
1571 MAKE_DBG_STR (\nCfgLvdsMiscControl.HsyncActiveLow , CFG_LVDS_MISC_HSYNC_ACTIVE_LOW),
1572 MAKE_DBG_STR (\nCfgLvdsMiscControl.BLONActiveLow , CFG_LVDS_MISC_BLON_ACTIVE_LOW),
1573 MAKE_DBG_STR (\nCfgPcieRefClkSpreadSpectrum , CFG_PCIE_REFCLK_SPREAD_SPECTRUM),
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1574 #endif
1575 NULL
1576 };
1577 #endif
1578 #endif
1579#endif