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review.coreboot.org / coreboot / 41b820cbd66da001b02a426a7b5cf1b7f011702a / . / src / vendorcode / amd / agesa / f14 / Config / PlatformInstall.h
blob: 9aa9cbd16a07dd8093e6c570e4bd55bf3cf7c7c9 [file] [log] [blame]
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * Install of build options for a combination of package type, processor, and features.
6 *
7 * This file generates the defaults tables for the all platform solution
8 * combinations. The documented build options are imported from a user
9 * controlled file for processing.
10 *
11 * @xrefitem bom "File Content Label" "Release Content"
12 * @e project: AGESA
13 * @e sub-project: Core
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]14 * @e \$Revision: 47417 $ @e \$Date: 2011-02-18 12:48:20 -0700 (Fri, 18 Feb 2011) $
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]15 */
16/*
17 *****************************************************************************
18 *
19 * Copyright (c) 2011, Advanced Micro Devices, Inc.
20 * All rights reserved.
Edward O'Callaghane963b382014-07-06 19:27:14 +1000[diff] [blame]21 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions are met:
24 * * Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * * Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in the
28 * documentation and/or other materials provided with the distribution.
Edward O'Callaghane963b382014-07-06 19:27:14 +1000[diff] [blame]29 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
30 * its contributors may be used to endorse or promote products derived
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]31 * from this software without specific prior written permission.
Edward O'Callaghane963b382014-07-06 19:27:14 +1000[diff] [blame]32 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
35 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
36 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
37 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
38 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
40 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
41 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
42 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Edward O'Callaghane963b382014-07-06 19:27:14 +1000[diff] [blame]43 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]44 * ***************************************************************************
45 *
46 */
47
48/*****************************************************************************
49 *
50 * Start processing the user options: First, set default settings
51 *
52 ****************************************************************************/
53
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]54VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
55 //ModuleHeaderSignature
56 // Remove 'DOM$' as temp solution before update BinUtil.exe ,
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]57 Int32FromChar ('0', '0', '0', '0'),
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]58 //ModuleIdentifier[8]
59 AGESA_ID,
60 //ModuleVersion[12]
61 AGESA_VERSION_STRING,
62 //ModuleDispatcher
63 NULL,//(VOID *)(UINT64)((MODULE_ENTRY)AmdAgesaDispatcher),
64 //NextBlock
65 NULL
66};
67
Angel Pons41b820c2020-05-21 00:58:33 +0200[diff] [blame^]68/* The default fixed MTRR values to be set after memory initialization */
69static const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
70{
71 { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
72 { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
73 { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
74 { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
75 { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
76 { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
77 { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
78 { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
79 { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
80 { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
81 { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
82 { CPU_LIST_TERMINAL },
83};
84
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]85/* Process solution defined socket / family installations
86 *
87 * As part of the release package for each image, define the options below to select the
88 * AGESA processor support included in that image.
89 */
90
91/* Default sockets to off */
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]92#define OPTION_FT1_SOCKET_SUPPORT FALSE
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]93
94/* Default families to off */
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]95#define OPTION_FAMILY14H FALSE
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]96
97/* Enable the appropriate socket support */
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]98#ifdef INSTALL_FT1_SOCKET_SUPPORT
99 #if INSTALL_FT1_SOCKET_SUPPORT == TRUE
100 #undef OPTION_FT1_SOCKET_SUPPORT
101 #define OPTION_FT1_SOCKET_SUPPORT TRUE
102 #endif
103#endif
104
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]105// F14 is supported in FT1
106#ifdef INSTALL_FAMILY_14_SUPPORT
107 #if INSTALL_FAMILY_14_SUPPORT == TRUE
108 #undef OPTION_FAMILY14H
109 #define OPTION_FAMILY14H TRUE
110 #endif
111#endif
112
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]113#if (OPTION_FAMILY14H == TRUE)
114 #if (OPTION_FT1_SOCKET_SUPPORT == FALSE)
115 #undef OPTION_FAMILY14H
116 #define OPTION_FAMILY14H FALSE
117 #endif
118#endif
119
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]120
121/* Check for invalid combinations of socket/family */
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]122
123#if (OPTION_FT1_SOCKET_SUPPORT == TRUE)
124 #if (OPTION_FAMILY14H == FALSE)
125 #error No FT1 supported families included in the build
126 #endif
127#endif
128
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]129/* Process AGESA private data
130 *
131 * Turn on appropriate CPU models and memory controllers,
132 * as well as some other memory controls.
133 */
134
135/* Default all models to off */
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]136#define OPTION_FAMILY14H_ON FALSE
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]137
138/* Default all memory controllers to off */
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]139#define OPTION_MEMCTLR_ON FALSE
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]140
141/* Default all memory controls to off */
142#define OPTION_HW_WRITE_LEV_TRAINING FALSE
143#define OPTION_SW_WRITE_LEV_TRAINING FALSE
144#define OPTION_CONTINOUS_PATTERN_GENERATION FALSE
145#define OPTION_HW_DQS_REC_EN_TRAINING FALSE
146#define OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING FALSE
147#define OPTION_OPT_SW_DQS_REC_EN_TRAINING FALSE
148#define OPTION_NON_OPT_SW_RD_WR_POS_TRAINING FALSE
149#define OPTION_OPT_SW_RD_WR_POS_TRAINING FALSE
150#define OPTION_MAX_RD_LAT_TRAINING FALSE
151#define OPTION_HW_DRAM_INIT FALSE
152#define OPTION_SW_DRAM_INIT FALSE
153#define OPTION_S3_MEM_SUPPORT FALSE
154#define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
155
156/* Defaults for public user options */
157#define OPTION_UDIMMS FALSE
158#define OPTION_RDIMMS FALSE
159#define OPTION_SODIMMS FALSE
160#define OPTION_LRDIMMS FALSE
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]161#define OPTION_DDR3 FALSE
162#define OPTION_ECC FALSE
163#define OPTION_BANK_INTERLEAVE FALSE
164#define OPTION_DCT_INTERLEAVE FALSE
165#define OPTION_NODE_INTERLEAVE FALSE
166#define OPTION_PARALLEL_TRAINING FALSE
167#define OPTION_ONLINE_SPARE FALSE
168#define OPTION_MEM_RESTORE FALSE
169#define OPTION_DIMM_EXCLUDE FALSE
170
171/* Default all CPU controls to off */
172#define OPTION_MULTISOCKET FALSE
173#define OPTION_SRAT FALSE
174#define OPTION_SLIT FALSE
175#define OPTION_HT_ASSIST FALSE
176#define OPTION_ATM_MODE FALSE
177#define OPTION_CPU_CORELEVLING FALSE
178#define OPTION_MSG_BASED_C1E FALSE
179#define OPTION_CPU_CFOH FALSE
180#define OPTION_C6_STATE FALSE
181#define OPTION_IO_CSTATE FALSE
182#define OPTION_CPB FALSE
183#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT FALSE
184#define OPTION_S3SCRIPT FALSE
185#define OPTION_GFX_RECOVERY FALSE
186
187/* Enable all private controls based on socket/family enables */
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]188
189#if (OPTION_FT1_SOCKET_SUPPORT == TRUE)
190 #if (OPTION_FAMILY14H == TRUE)
191 #undef OPTION_FAMILY14H_ON
192 #define OPTION_FAMILY14H_ON TRUE
193 #undef OPTION_MEMCTLR_ON
194 #define OPTION_MEMCTLR_ON TRUE
195 #undef OPTION_HW_WRITE_LEV_TRAINING
196 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
197 #undef OPTION_CONTINOUS_PATTERN_GENERATION
198 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
199 #undef OPTION_MAX_RD_LAT_TRAINING
200 #define OPTION_MAX_RD_LAT_TRAINING TRUE
201 #undef OPTION_HW_DQS_REC_EN_TRAINING
202 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
203 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
204 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
205 #undef OPTION_SW_DRAM_INIT
206 #define OPTION_SW_DRAM_INIT TRUE
207 #undef OPTION_S3_MEM_SUPPORT
208 #define OPTION_S3_MEM_SUPPORT TRUE
209 #undef OPTION_GFX_RECOVERY
210 #define OPTION_GFX_RECOVERY TRUE
211 #undef OPTION_C6_STATE
212 #define OPTION_C6_STATE TRUE
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]213 #undef OPTION_CPB
214 #define OPTION_CPB TRUE
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]215 #undef OPTION_IO_CSTATE
216 #define OPTION_IO_CSTATE TRUE
217 #undef OPTION_S3SCRIPT
218 #define OPTION_S3SCRIPT TRUE
219 #undef OPTION_UDIMMS
220 #define OPTION_UDIMMS TRUE
221 #undef OPTION_SODIMMS
222 #define OPTION_SODIMMS TRUE
223 #undef OPTION_DDR3
224 #define OPTION_DDR3 TRUE
225 #undef OPTION_BANK_INTERLEAVE
226 #define OPTION_BANK_INTERLEAVE TRUE
227 #undef OPTION_MEM_RESTORE
228 #define OPTION_MEM_RESTORE TRUE
229 #undef OPTION_DIMM_EXCLUDE
230 #define OPTION_DIMM_EXCLUDE TRUE
231 #endif
232#endif
233
Kyösti Mälkkiba4e6952017-08-31 15:17:36 +0300[diff] [blame]234#if (OPTION_FAMILY14H == TRUE)
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]235 #undef GNB_SUPPORT
236 #define GNB_SUPPORT TRUE
237#endif
238
239#define OPTION_ACPI_PSTATES TRUE
240#define OPTION_WHEA TRUE
241#define OPTION_DMI TRUE
242#define OPTION_EARLY_SAMPLES FALSE
243#define CFG_ACPI_PSTATES_PPC TRUE
244#define CFG_ACPI_PSTATES_PCT TRUE
245#define CFG_ACPI_PSTATES_PSD TRUE
246#define CFG_ACPI_PSTATES_PSS TRUE
247#define CFG_ACPI_PSTATES_XPSS TRUE
248#define CFG_ACPI_PSTATE_PSD_INDPX FALSE
249#define CFG_VRM_HIGH_SPEED_ENABLE FALSE
250#define CFG_VRM_NB_HIGH_SPEED_ENABLE FALSE
251#define OPTION_ALIB TRUE
252/*---------------------------------------------------------------------------
253 * Processing the options: Second, process the user's selections
254 *--------------------------------------------------------------------------*/
255#ifdef BLDOPT_REMOVE_MULTISOCKET_SUPPORT
256 #if BLDOPT_REMOVE_MULTISOCKET_SUPPORT == TRUE
257 #undef OPTION_MULTISOCKET
258 #define OPTION_MULTISOCKET FALSE
259 #endif
260#endif
261#ifdef BLDOPT_REMOVE_ECC_SUPPORT
262 #if BLDOPT_REMOVE_ECC_SUPPORT == TRUE
263 #undef OPTION_ECC
264 #define OPTION_ECC FALSE
265 #endif
266#endif
267#ifdef BLDOPT_REMOVE_UDIMMS_SUPPORT
268 #if BLDOPT_REMOVE_UDIMMS_SUPPORT == TRUE
269 #undef OPTION_UDIMMS
270 #define OPTION_UDIMMS FALSE
271 #endif
272#endif
273#ifdef BLDOPT_REMOVE_RDIMMS_SUPPORT
274 #if BLDOPT_REMOVE_RDIMMS_SUPPORT == TRUE
275 #undef OPTION_RDIMMS
276 #define OPTION_RDIMMS FALSE
277 #endif
278#endif
279#ifdef BLDOPT_REMOVE_SODIMMS_SUPPORT
280 #if BLDOPT_REMOVE_SODIMMS_SUPPORT == TRUE
281 #undef OPTION_SODIMMS
282 #define OPTION_SODIMMS FALSE
283 #endif
284#endif
285#ifdef BLDOPT_REMOVE_LRDIMMS_SUPPORT
286 #if BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE
287 #undef OPTION_LRDIMMS
288 #define OPTION_LRDIMMS FALSE
289 #endif
290#endif
291#ifdef BLDOPT_REMOVE_BANK_INTERLEAVE
292 #if BLDOPT_REMOVE_BANK_INTERLEAVE == TRUE
293 #undef OPTION_BANK_INTERLEAVE
294 #define OPTION_BANK_INTERLEAVE FALSE
295 #endif
296#endif
297#ifdef BLDOPT_REMOVE_DCT_INTERLEAVE
298 #if BLDOPT_REMOVE_DCT_INTERLEAVE == TRUE
299 #undef OPTION_DCT_INTERLEAVE
300 #define OPTION_DCT_INTERLEAVE FALSE
301 #endif
302#endif
303#ifdef BLDOPT_REMOVE_NODE_INTERLEAVE
304 #if BLDOPT_REMOVE_NODE_INTERLEAVE == TRUE
305 #undef OPTION_NODE_INTERLEAVE
306 #define OPTION_NODE_INTERLEAVE FALSE
307 #endif
308#endif
309#ifdef BLDOPT_REMOVE_PARALLEL_TRAINING
310 #if BLDOPT_REMOVE_PARALLEL_TRAINING == TRUE
311 #undef OPTION_PARALLEL_TRAINING
312 #define OPTION_PARALLEL_TRAINING FALSE
313 #endif
314#endif
315#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
316 #if BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE
317 #undef OPTION_ONLINE_SPARE
318 #define OPTION_ONLINE_SPARE FALSE
319 #endif
320#endif
321#ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
322 #if BLDOPT_REMOVE_MEM_RESTORE_SUPPORT == TRUE
323 #undef OPTION_MEM_RESTORE
324 #define OPTION_MEM_RESTORE FALSE
325 #endif
326#endif
327#ifdef BLDOPT_REMOVE_ACPI_PSTATES
328 #if BLDOPT_REMOVE_ACPI_PSTATES == TRUE
329 #undef OPTION_ACPI_PSTATES
330 #define OPTION_ACPI_PSTATES FALSE
331 #endif
332#endif
333#ifdef BLDOPT_REMOVE_SRAT
334 #if BLDOPT_REMOVE_SRAT == TRUE
335 #undef OPTION_SRAT
336 #define OPTION_SRAT FALSE
337 #endif
338#endif
339#ifdef BLDOPT_REMOVE_SLIT
340 #if BLDOPT_REMOVE_SLIT == TRUE
341 #undef OPTION_SLIT
342 #define OPTION_SLIT FALSE
343 #endif
344#endif
345#ifdef BLDOPT_REMOVE_WHEA
346 #if BLDOPT_REMOVE_WHEA == TRUE
347 #undef OPTION_WHEA
348 #define OPTION_WHEA FALSE
349 #endif
350#endif
351#ifdef BLDOPT_REMOVE_DMI
352 #if BLDOPT_REMOVE_DMI == TRUE
353 #undef OPTION_DMI
354 #define OPTION_DMI FALSE
355 #endif
356#endif
357#ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR
358 #if BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR == TRUE
359 #undef OPTION_ADDR_TO_CS_TRANSLATOR
360 #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
361 #endif
362#endif
363
364#ifdef BLDOPT_REMOVE_HT_ASSIST
365 #if BLDOPT_REMOVE_HT_ASSIST == TRUE
366 #undef OPTION_HT_ASSIST
367 #define OPTION_HT_ASSIST FALSE
368 #endif
369#endif
370
371#ifdef BLDOPT_REMOVE_ATM_MODE
372 #if BLDOPT_REMOVE_ATM_MODE == TRUE
373 #undef OPTION_ATM_MODE
374 #define OPTION_ATM_MODE FALSE
375 #endif
376#endif
377
378#ifdef BLDOPT_REMOVE_MSG_BASED_C1E
379 #if BLDOPT_REMOVE_MSG_BASED_C1E == TRUE
380 #undef OPTION_MSG_BASED_C1E
381 #define OPTION_MSG_BASED_C1E FALSE
382 #endif
383#endif
384
385#ifdef BLDOPT_REMOVE_C6_STATE
386 #if BLDOPT_REMOVE_C6_STATE == TRUE
387 #undef OPTION_C6_STATE
388 #define OPTION_C6_STATE FALSE
389 #endif
390#endif
391
392#ifdef BLDOPT_REMOVE_GFX_RECOVERY
393 #if BLDOPT_REMOVE_GFX_RECOVERY == TRUE
394 #undef OPTION_GFX_RECOVERY
395 #define OPTION_GFX_RECOVERY FALSE
396 #endif
397#endif
398
399#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PPC
400 #if BLDCFG_REMOVE_ACPI_PSTATES_PPC == TRUE
401 #undef CFG_ACPI_PSTATES_PPC
402 #define CFG_ACPI_PSTATES_PPC FALSE
403 #endif
404#endif
405
406#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PCT
407 #if BLDCFG_REMOVE_ACPI_PSTATES_PCT == TRUE
408 #undef CFG_ACPI_PSTATES_PCT
409 #define CFG_ACPI_PSTATES_PCT FALSE
410 #endif
411#endif
412
413#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSD
414 #if BLDCFG_REMOVE_ACPI_PSTATES_PSD == TRUE
415 #undef CFG_ACPI_PSTATES_PSD
416 #define CFG_ACPI_PSTATES_PSD FALSE
417 #endif
418#endif
419
420#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSS
421 #if BLDCFG_REMOVE_ACPI_PSTATES_PSS == TRUE
422 #undef CFG_ACPI_PSTATES_PSS
423 #define CFG_ACPI_PSTATES_PSS FALSE
424 #endif
425#endif
426
427#ifdef BLDCFG_REMOVE_ACPI_PSTATES_XPSS
428 #if BLDCFG_REMOVE_ACPI_PSTATES_XPSS == TRUE
429 #undef CFG_ACPI_PSTATES_XPSS
430 #define CFG_ACPI_PSTATES_XPSS FALSE
431 #endif
432#endif
433
434#ifdef BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT
435 #if BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT == TRUE
436 #undef CFG_ACPI_PSTATE_PSD_INDPX
437 #define CFG_ACPI_PSTATE_PSD_INDPX TRUE
438 #endif
439#endif
440
441#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE
442 #if BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE
443 #undef CFG_VRM_HIGH_SPEED_ENABLE
444 #define CFG_VRM_HIGH_SPEED_ENABLE TRUE
445 #endif
446#endif
447
448#ifdef BLDCFG_VRM_NB_HIGH_SPEED_ENABLE
449 #if BLDCFG_VRM_NB_HIGH_SPEED_ENABLE == TRUE
450 #undef CFG_VRM_NB_HIGH_SPEED_ENABLE
451 #define CFG_VRM_NB_HIGH_SPEED_ENABLE TRUE
452 #endif
453#endif
454
455#ifdef BLDCFG_STARTING_BUSNUM
456 #define CFG_STARTING_BUSNUM (BLDCFG_STARTING_BUSNUM)
457#else
458 #define CFG_STARTING_BUSNUM (0)
459#endif
460
461#ifdef BLDCFG_AMD_PLATFORM_TYPE
462 #define CFG_AMD_PLATFORM_TYPE BLDCFG_AMD_PLATFORM_TYPE
463#else
464 #define CFG_AMD_PLATFORM_TYPE 0
465#endif
466
467CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
468
469#ifdef BLDCFG_MAXIMUM_BUSNUM
470 #define CFG_MAXIMUM_BUSNUM (BLDCFG_MAXIMUM_BUSNUM)
471#else
472 #define CFG_MAXIMUM_BUSNUM (0xF8)
473#endif
474
475#ifdef BLDCFG_ALLOCATED_BUSNUM
476 #define CFG_ALLOCATED_BUSNUM (BLDCFG_ALLOCATED_BUSNUM)
477#else
478 #define CFG_ALLOCATED_BUSNUM (0x20)
479#endif
480
481#ifdef BLDCFG_BUID_SWAP_LIST
482 #define CFG_BUID_SWAP_LIST (BLDCFG_BUID_SWAP_LIST)
483#else
484 #define CFG_BUID_SWAP_LIST (NULL)
485#endif
486
487#ifdef BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST
488 #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST)
489#else
490 #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (NULL)
491#endif
492
493#ifdef BLDCFG_HTFABRIC_LIMITS_LIST
494 #define CFG_HTFABRIC_LIMITS_LIST (BLDCFG_HTFABRIC_LIMITS_LIST)
495#else
496 #define CFG_HTFABRIC_LIMITS_LIST (NULL)
497#endif
498
499#ifdef BLDCFG_HTCHAIN_LIMITS_LIST
500 #define CFG_HTCHAIN_LIMITS_LIST (BLDCFG_HTCHAIN_LIMITS_LIST)
501#else
502 #define CFG_HTCHAIN_LIMITS_LIST (NULL)
503#endif
504
505#ifdef BLDCFG_BUS_NUMBERS_LIST
506 #define CFG_BUS_NUMBERS_LIST (BLDCFG_BUS_NUMBERS_LIST)
507#else
508 #define CFG_BUS_NUMBERS_LIST (NULL)
509#endif
510
511#ifdef BLDCFG_IGNORE_LINK_LIST
512 #define CFG_IGNORE_LINK_LIST (BLDCFG_IGNORE_LINK_LIST)
513#else
514 #define CFG_IGNORE_LINK_LIST (NULL)
515#endif
516
517#ifdef BLDCFG_LINK_SKIP_REGANG_LIST
518 #define CFG_LINK_SKIP_REGANG_LIST (BLDCFG_LINK_SKIP_REGANG_LIST)
519#else
520 #define CFG_LINK_SKIP_REGANG_LIST (NULL)
521#endif
522
523#ifdef BLDCFG_SET_HTCRC_SYNC_FLOOD
524 #define CFG_SET_HTCRC_SYNC_FLOOD (BLDCFG_SET_HTCRC_SYNC_FLOOD)
525#else
526 #define CFG_SET_HTCRC_SYNC_FLOOD (FALSE)
527#endif
528
529#ifdef BLDCFG_USE_UNIT_ID_CLUMPING
530 #define CFG_USE_UNIT_ID_CLUMPING (BLDCFG_USE_UNIT_ID_CLUMPING)
531#else
532 #define CFG_USE_UNIT_ID_CLUMPING (FALSE)
533#endif
534
535#ifdef BLDCFG_ADDITIONAL_TOPOLOGIES_LIST
536 #define CFG_ADDITIONAL_TOPOLOGIES_LIST (BLDCFG_ADDITIONAL_TOPOLOGIES_LIST)
537#else
538 #define CFG_ADDITIONAL_TOPOLOGIES_LIST (NULL)
539#endif
540
541#ifdef BLDCFG_USE_HT_ASSIST
542 #define CFG_USE_HT_ASSIST (BLDCFG_USE_HT_ASSIST)
543#else
544 #define CFG_USE_HT_ASSIST (TRUE)
545#endif
546
547#ifdef BLDCFG_USE_ATM_MODE
548 #define CFG_USE_ATM_MODE (BLDCFG_USE_ATM_MODE)
549#else
550 #define CFG_USE_ATM_MODE (TRUE)
551#endif
552
553#ifdef BLDCFG_PLATFORM_CONTROL_FLOW_MODE
554 #define CFG_PLATFORM_CONTROL_FLOW_MODE (BLDCFG_PLATFORM_CONTROL_FLOW_MODE)
555#else
556 #define CFG_PLATFORM_CONTROL_FLOW_MODE (Nfcm)
557#endif
558
559#ifdef BLDCFG_PLATFORM_DEEMPHASIS_LIST
560 #define CFG_PLATFORM_DEEMPHASIS_LIST (BLDCFG_PLATFORM_DEEMPHASIS_LIST)
561#else
562 #define CFG_PLATFORM_DEEMPHASIS_LIST (NULL)
563#endif
564
565#ifdef BLDCFG_VRM_ADDITIONAL_DELAY
566 #define CFG_VRM_ADDITIONAL_DELAY (BLDCFG_VRM_ADDITIONAL_DELAY)
567#else
568 #define CFG_VRM_ADDITIONAL_DELAY (0)
569#endif
570
571#ifdef BLDCFG_VRM_CURRENT_LIMIT
572 #define CFG_VRM_CURRENT_LIMIT BLDCFG_VRM_CURRENT_LIMIT
573#else
574 #define CFG_VRM_CURRENT_LIMIT 0
575#endif
576
577#ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD
578 #define CFG_VRM_LOW_POWER_THRESHOLD BLDCFG_VRM_LOW_POWER_THRESHOLD
579#else
580 #define CFG_VRM_LOW_POWER_THRESHOLD 0
581#endif
582
583#ifdef BLDCFG_VRM_SLEW_RATE
584 #define CFG_VRM_SLEW_RATE BLDCFG_VRM_SLEW_RATE
585#else
586 #define CFG_VRM_SLEW_RATE DFLT_VRM_SLEW_RATE
587#endif
588
589#ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT
590 #define CFG_VRM_INRUSH_CURRENT_LIMIT BLDCFG_VRM_INRUSH_CURRENT_LIMIT
591#else
592 #define CFG_VRM_INRUSH_CURRENT_LIMIT 0
593#endif
594
595#ifdef BLDCFG_VRM_NB_ADDITIONAL_DELAY
596 #define CFG_VRM_NB_ADDITIONAL_DELAY (BLDCFG_VRM_NB_ADDITIONAL_DELAY)
597#else
598 #define CFG_VRM_NB_ADDITIONAL_DELAY (0)
599#endif
600
601#ifdef BLDCFG_VRM_NB_CURRENT_LIMIT
602 #define CFG_VRM_NB_CURRENT_LIMIT BLDCFG_VRM_NB_CURRENT_LIMIT
603#else
604 #define CFG_VRM_NB_CURRENT_LIMIT (0)
605#endif
606
607#ifdef BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
608 #define CFG_VRM_NB_LOW_POWER_THRESHOLD BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
609#else
610 #define CFG_VRM_NB_LOW_POWER_THRESHOLD (0)
611#endif
612
613#ifdef BLDCFG_VRM_NB_SLEW_RATE
614 #define CFG_VRM_NB_SLEW_RATE BLDCFG_VRM_NB_SLEW_RATE
615#else
616 #define CFG_VRM_NB_SLEW_RATE DFLT_VRM_SLEW_RATE
617#endif
618
619#ifdef BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT
620 #define CFG_VRM_NB_INRUSH_CURRENT_LIMIT BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT
621#else
622 #define CFG_VRM_NB_INRUSH_CURRENT_LIMIT (0)
623#endif
624
625
626#ifdef BLDCFG_PLAT_NUM_IO_APICS
627 #define CFG_PLAT_NUM_IO_APICS BLDCFG_PLAT_NUM_IO_APICS
628#else
629 #define CFG_PLAT_NUM_IO_APICS 0
630#endif
631
632#ifdef BLDCFG_MEM_INIT_PSTATE
633 #define CFG_MEM_INIT_PSTATE BLDCFG_MEM_INIT_PSTATE
634#else
635 #define CFG_MEM_INIT_PSTATE 0
636#endif
637
638#ifdef BLDCFG_PLATFORM_C1E_MODE
639 #define CFG_C1E_MODE BLDCFG_PLATFORM_C1E_MODE
640#else
641 #define CFG_C1E_MODE C1eModeDisabled
642#endif
643
644#ifdef BLDCFG_PLATFORM_C1E_OPDATA
645 #define CFG_C1E_OPDATA BLDCFG_PLATFORM_C1E_OPDATA
646#else
647 #define CFG_C1E_OPDATA 0
648#endif
649
650#ifdef BLDCFG_PLATFORM_C1E_OPDATA1
651 #define CFG_C1E_OPDATA1 BLDCFG_PLATFORM_C1E_OPDATA1
652#else
653 #define CFG_C1E_OPDATA1 0
654#endif
655
656#ifdef BLDCFG_PLATFORM_C1E_OPDATA2
657 #define CFG_C1E_OPDATA2 BLDCFG_PLATFORM_C1E_OPDATA2
658#else
659 #define CFG_C1E_OPDATA2 0
660#endif
661
662#ifdef BLDCFG_PLATFORM_CSTATE_MODE
663 #define CFG_CSTATE_MODE BLDCFG_PLATFORM_CSTATE_MODE
664#else
665 #define CFG_CSTATE_MODE CStateModeDisabled
666#endif
667
668#ifdef BLDCFG_PLATFORM_CSTATE_OPDATA
669 #define CFG_CSTATE_OPDATA BLDCFG_PLATFORM_CSTATE_OPDATA
670#else
671 #define CFG_CSTATE_OPDATA 0
672#endif
673
674#ifdef BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
675 #define CFG_CSTATE_IO_BASE_ADDRESS BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
676#else
677 #define CFG_CSTATE_IO_BASE_ADDRESS 0
678#endif
679
680#ifdef BLDCFG_PLATFORM_CPB_MODE
681 #define CFG_CPB_MODE BLDCFG_PLATFORM_CPB_MODE
682#else
683 #define CFG_CPB_MODE CpbModeAuto
684#endif
685
686#ifdef BLDCFG_CORE_LEVELING_MODE
687 #define CFG_CORE_LEVELING_MODE BLDCFG_CORE_LEVELING_MODE
688#else
689 #define CFG_CORE_LEVELING_MODE 0
690#endif
691
692#ifdef BLDCFG_AMD_PSTATE_CAP_VALUE
693 #define CFG_AMD_PSTATE_CAP_VALUE BLDCFG_AMD_PSTATE_CAP_VALUE
694#else
695 #define CFG_AMD_PSTATE_CAP_VALUE 0
696#endif
697
698#ifdef BLDCFG_HEAP_DRAM_ADDRESS
699 #define CFG_HEAP_DRAM_ADDRESS BLDCFG_HEAP_DRAM_ADDRESS
700#else
701 #define CFG_HEAP_DRAM_ADDRESS AMD_HEAP_RAM_ADDRESS
702#endif
703
704#ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
705 #define CFG_MEMORY_BUS_FREQUENCY_LIMIT BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
706#else
707 #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR800_FREQUENCY
708#endif
709
710#ifdef BLDCFG_MEMORY_MODE_UNGANGED
711 #define CFG_MEMORY_MODE_UNGANGED BLDCFG_MEMORY_MODE_UNGANGED
712#else
713 #define CFG_MEMORY_MODE_UNGANGED TRUE
714#endif
715
716#ifdef BLDCFG_MEMORY_QUAD_RANK_CAPABLE
717 #define CFG_MEMORY_QUAD_RANK_CAPABLE BLDCFG_MEMORY_QUAD_RANK_CAPABLE
718#else
719 #define CFG_MEMORY_QUAD_RANK_CAPABLE TRUE
720#endif
721
722#ifdef BLDCFG_MEMORY_QUADRANK_TYPE
723 #define CFG_MEMORY_QUADRANK_TYPE BLDCFG_MEMORY_QUADRANK_TYPE
724#else
725 #define CFG_MEMORY_QUADRANK_TYPE DFLT_MEMORY_QUADRANK_TYPE
726#endif
727
728#ifdef BLDCFG_MEMORY_RDIMM_CAPABLE
729 #define CFG_MEMORY_RDIMM_CAPABLE BLDCFG_MEMORY_RDIMM_CAPABLE
730#else
731 #define CFG_MEMORY_RDIMM_CAPABLE TRUE
732#endif
733
734#ifdef BLDCFG_MEMORY_LRDIMM_CAPABLE
735 #define CFG_MEMORY_LRDIMM_CAPABLE BLDCFG_MEMORY_LRDIMM_CAPABLE
736#else
737 #define CFG_MEMORY_LRDIMM_CAPABLE TRUE
738#endif
739
740#ifdef BLDCFG_MEMORY_UDIMM_CAPABLE
741 #define CFG_MEMORY_UDIMM_CAPABLE BLDCFG_MEMORY_UDIMM_CAPABLE
742#else
743 #define CFG_MEMORY_UDIMM_CAPABLE TRUE
744#endif
745
746#ifdef BLDCFG_MEMORY_SODIMM_CAPABLE
747 #define CFG_MEMORY_SODIMM_CAPABLE BLDCFG_MEMORY_SODIMM_CAPABLE
748#else
749 #define CFG_MEMORY_SODIMM_CAPABLE FALSE
750#endif
751
752#ifdef BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
753 #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
754#else
755 #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
756#endif
757
758#ifdef BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
759 #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
760#else
761 #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
762#endif
763
764#ifdef BLDCFG_MEMORY_CHANNEL_INTERLEAVING
765 #define CFG_MEMORY_CHANNEL_INTERLEAVING BLDCFG_MEMORY_CHANNEL_INTERLEAVING
766#else
767 #define CFG_MEMORY_CHANNEL_INTERLEAVING TRUE
768#endif
769
770#ifdef BLDCFG_MEMORY_POWER_DOWN
771 #define CFG_MEMORY_POWER_DOWN BLDCFG_MEMORY_POWER_DOWN
772#else
773 #define CFG_MEMORY_POWER_DOWN FALSE
774#endif
775
776#ifdef BLDCFG_POWER_DOWN_MODE
777 #define CFG_POWER_DOWN_MODE BLDCFG_POWER_DOWN_MODE
778#else
779 #define CFG_POWER_DOWN_MODE POWER_DOWN_MODE_AUTO
780#endif
781
782#ifdef BLDCFG_ONLINE_SPARE
783 #define CFG_ONLINE_SPARE BLDCFG_ONLINE_SPARE
784#else
785 #define CFG_ONLINE_SPARE FALSE
786#endif
787
788#ifdef BLDCFG_MEMORY_PARITY_ENABLE
789 #define CFG_MEMORY_PARITY_ENABLE BLDCFG_MEMORY_PARITY_ENABLE
790#else
791 #define CFG_MEMORY_PARITY_ENABLE FALSE
792#endif
793
794#ifdef BLDCFG_BANK_SWIZZLE
795 #define CFG_BANK_SWIZZLE BLDCFG_BANK_SWIZZLE
796#else
797 #define CFG_BANK_SWIZZLE TRUE
798#endif
799
800#ifdef BLDCFG_TIMING_MODE_SELECT
801 #define CFG_TIMING_MODE_SELECT BLDCFG_TIMING_MODE_SELECT
802#else
803 #define CFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
804#endif
805
806#ifdef BLDCFG_MEMORY_CLOCK_SELECT
807 #define CFG_MEMORY_CLOCK_SELECT BLDCFG_MEMORY_CLOCK_SELECT
808#else
809 #define CFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY
810#endif
811
812#ifdef BLDCFG_DQS_TRAINING_CONTROL
813 #define CFG_DQS_TRAINING_CONTROL BLDCFG_DQS_TRAINING_CONTROL
814#else
815 #define CFG_DQS_TRAINING_CONTROL TRUE
816#endif
817
818#ifdef BLDCFG_IGNORE_SPD_CHECKSUM
819 #define CFG_IGNORE_SPD_CHECKSUM BLDCFG_IGNORE_SPD_CHECKSUM
820#else
821 #define CFG_IGNORE_SPD_CHECKSUM FALSE
822#endif
823
824#ifdef BLDCFG_USE_BURST_MODE
825 #define CFG_USE_BURST_MODE BLDCFG_USE_BURST_MODE
826#else
827 #define CFG_USE_BURST_MODE FALSE
828#endif
829
830#ifdef BLDCFG_MEMORY_ALL_CLOCKS_ON
831 #define CFG_MEMORY_ALL_CLOCKS_ON BLDCFG_MEMORY_ALL_CLOCKS_ON
832#else
833 #define CFG_MEMORY_ALL_CLOCKS_ON FALSE
834#endif
835
836#ifdef BLDCFG_ENABLE_ECC_FEATURE
837 #define CFG_ENABLE_ECC_FEATURE BLDCFG_ENABLE_ECC_FEATURE
838#else
839 #define CFG_ENABLE_ECC_FEATURE TRUE
840#endif
841
842#ifdef BLDCFG_ECC_REDIRECTION
843 #define CFG_ECC_REDIRECTION BLDCFG_ECC_REDIRECTION
844#else
845 #define CFG_ECC_REDIRECTION FALSE
846#endif
847
848#ifdef BLDCFG_SCRUB_DRAM_RATE
849 #define CFG_SCRUB_DRAM_RATE BLDCFG_SCRUB_DRAM_RATE
850#else
851 #define CFG_SCRUB_DRAM_RATE DFLT_SCRUB_DRAM_RATE
852#endif
853
854#ifdef BLDCFG_SCRUB_L2_RATE
855 #define CFG_SCRUB_L2_RATE BLDCFG_SCRUB_L2_RATE
856#else
857 #define CFG_SCRUB_L2_RATE DFLT_SCRUB_L2_RATE
858#endif
859
860#ifdef BLDCFG_SCRUB_L3_RATE
861 #define CFG_SCRUB_L3_RATE BLDCFG_SCRUB_L3_RATE
862#else
863 #define CFG_SCRUB_L3_RATE DFLT_SCRUB_L3_RATE
864#endif
865
866#ifdef BLDCFG_SCRUB_IC_RATE
867 #define CFG_SCRUB_IC_RATE BLDCFG_SCRUB_IC_RATE
868#else
869 #define CFG_SCRUB_IC_RATE DFLT_SCRUB_IC_RATE
870#endif
871
872#ifdef BLDCFG_SCRUB_DC_RATE
873 #define CFG_SCRUB_DC_RATE BLDCFG_SCRUB_DC_RATE
874#else
875 #define CFG_SCRUB_DC_RATE DFLT_SCRUB_DC_RATE
876#endif
877
878#ifdef BLDCFG_ECC_SYNC_FLOOD
879 #define CFG_ECC_SYNC_FLOOD BLDCFG_ECC_SYNC_FLOOD
880#else
881 #define CFG_ECC_SYNC_FLOOD 0
882#endif
883
884#ifdef BLDCFG_ECC_SYMBOL_SIZE
885 #define CFG_ECC_SYMBOL_SIZE BLDCFG_ECC_SYMBOL_SIZE
886#else
887 #define CFG_ECC_SYMBOL_SIZE 0
888#endif
889
890#ifdef BLDCFG_1GB_ALIGN
891 #define CFG_1GB_ALIGN BLDCFG_1GB_ALIGN
892#else
893 #define CFG_1GB_ALIGN FALSE
894#endif
895
896#ifdef BLDCFG_UMA_ALLOCATION_MODE
897 #define CFG_UMA_MODE BLDCFG_UMA_ALLOCATION_MODE
898#else
899 #define CFG_UMA_MODE UMA_AUTO
900#endif
901
902#ifdef BLDCFG_UMA_ALLOCATION_SIZE
903 #define CFG_UMA_SIZE BLDCFG_UMA_ALLOCATION_SIZE
904#else
905 #define CFG_UMA_SIZE 0
906#endif
907
908#ifdef BLDCFG_UMA_ABOVE4G_SUPPORT
909 #define CFG_UMA_ABOVE4G BLDCFG_UMA_ABOVE4G_SUPPORT
910#else
911 #define CFG_UMA_ABOVE4G FALSE
912#endif
913
914#ifdef BLDCFG_UMA_ALIGNMENT
915 #define CFG_UMA_ALIGNMENT BLDCFG_UMA_ALIGNMENT
916#else
917 #define CFG_UMA_ALIGNMENT NO_UMA_ALIGNED
918#endif
919
920#ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB
921 #define CFG_PROCESSOR_SCOPE_IN_SB BLDCFG_PROCESSOR_SCOPE_IN_SB
922#else
923 #define CFG_PROCESSOR_SCOPE_IN_SB FALSE
924#endif
925
926#ifdef BLDCFG_S3_LATE_RESTORE
927 #define CFG_S3_LATE_RESTORE BLDCFG_S3_LATE_RESTORE
928#else
929 #define CFG_S3_LATE_RESTORE TRUE
930#endif
931
932#ifdef BLDCFG_USE_32_BYTE_REFRESH
933 #define CFG_USE_32_BYTE_REFRESH (BLDCFG_USE_32_BYTE_REFRESH)
934#else
935 #define CFG_USE_32_BYTE_REFRESH (FALSE)
936#endif
937
938#ifdef BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY
939 #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
940#else
941 #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (FALSE)
942#endif
943
944#ifdef BLDCFG_PROCESSOR_SCOPE_NAME0
945 #define CFG_PROCESSOR_SCOPE_NAME0 BLDCFG_PROCESSOR_SCOPE_NAME0
946#else
947 #define CFG_PROCESSOR_SCOPE_NAME0 SCOPE_NAME_VALUE
948#endif
949
950#ifdef BLDCFG_PROCESSOR_SCOPE_NAME1
951 #define CFG_PROCESSOR_SCOPE_NAME1 BLDCFG_PROCESSOR_SCOPE_NAME1
952#else
953 #define CFG_PROCESSOR_SCOPE_NAME1 SCOPE_NAME_VALUE1
954#endif
955
956#ifdef BLDCFG_CFG_GNB_HD_AUDIO
957 #define CFG_GNB_HD_AUDIO BLDCFG_CFG_GNB_HD_AUDIO
958#else
959 #define CFG_GNB_HD_AUDIO TRUE
960#endif
961
962#ifdef BLDCFG_CFG_ABM_SUPPORT
963 #define CFG_ABM_SUPPORT BLDCFG_CFG_ABM_SUPPORT
964#else
965 #define CFG_ABM_SUPPORT FALSE
966#endif
967
968#ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE
969 #define CFG_DINAMIC_REFRESH_RATE BLDCFG_CFG_DYNAMIC_REFRESH_RATE
970#else
971 #define CFG_DYNAMIC_REFRESH_RATE 0
972#endif
973
974#ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
975 #define CFG_LCD_BACK_LIGHT_CONTROL BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
976#else
977 #define CFG_LCD_BACK_LIGHT_CONTROL 0
978#endif
979
980#ifdef BLDCFG_STEREO_3D_PINOUT
981 #define CFG_GNB_STEREO_3D_PINOUT BLDCFG_STEREO_3D_PINOUT
982#else
983 #define CFG_GNB_STEREO_3D_PINOUT 0
984#endif
985
986#ifdef BLDCFG_IGPU_SUBSYSTEM_ID
987 #define CFG_GNB_IGPU_SSID BLDCFG_IGPU_SUBSYSTEM_ID
988#else
989 #define CFG_GNB_IGPU_SSID 0
990#endif
991
992#ifdef BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
993 #define CFG_GNB_HDAUDIO_SSID BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
994#else
995 #define CFG_GNB_HDAUDIO_SSID 0
996#endif
997
998#ifdef BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
999 #define CFG_GNB_PCIE_SSID BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
1000#else
1001 #define CFG_GNB_PCIE_SSID 0x12341022
1002#endif
1003
1004#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
1005 #define CFG_GFX_LVDS_SPREAD_SPECTRUM BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
1006#else
1007 #define CFG_GFX_LVDS_SPREAD_SPECTRUM 0
1008#endif
1009
1010#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
1011 #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
1012#else
1013 #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE 0
1014#endif
1015
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]1016#ifdef BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
1017 #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
1018#else
1019 #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM 0
1020#endif
1021
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1022#ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
1023 #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
1024#else
1025 #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000
1026#endif
1027
1028#ifdef BLDOPT_REMOVE_EARLY_SAMPLES
1029 #if BLDOPT_REMOVE_EARLY_SAMPLES == TRUE
1030 #undef OPTION_EARLY_SAMPLES
1031 #define OPTION_EARLY_SAMPLES FALSE
1032 #else
1033 #undef OPTION_EARLY_SAMPLES
1034 #define OPTION_EARLY_SAMPLES TRUE
1035 #endif
1036#endif
1037
1038#ifdef BLDOPT_REMOVE_ALIB
1039 #if BLDOPT_REMOVE_ALIB == TRUE
1040 #undef OPTION_ALIB
1041 #define OPTION_ALIB FALSE
1042 #else
1043 #undef OPTION_ALIB
1044 #define OPTION_ALIB TRUE
1045 #endif
1046#endif
1047
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]1048#ifdef BLDCFG_LVDS_MISC_888_FPDI_MODE
1049 #define CFG_LVDS_MISC_888_FPDI_MODE BLDCFG_LVDS_MISC_888_FPDI_MODE
1050#else
1051 #define CFG_LVDS_MISC_888_FPDI_MODE FALSE
1052#endif
1053
1054#ifdef BLDCFG_LVDS_MISC_DL_CH_SWAP
1055 #define CFG_LVDS_MISC_DL_CH_SWAP BLDCFG_LVDS_MISC_DL_CH_SWAP
1056#else
1057 #define CFG_LVDS_MISC_DL_CH_SWAP FALSE
1058#endif
1059
1060#ifdef BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
1061 #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
1062#else
1063 #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW FALSE
1064#endif
1065
1066#ifdef BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
1067 #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
1068#else
1069 #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW FALSE
1070#endif
1071
1072#ifdef BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
1073 #define CFG_LVDS_MISC_BLON_ACTIVE_LOW BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
1074#else
1075 #define CFG_LVDS_MISC_BLON_ACTIVE_LOW FALSE
1076#endif
Kyösti Mälkki206e1572016-05-18 14:04:45 +0300[diff] [blame]1077
1078#ifdef BLDCFG_PLATFORM_POWER_POLICY_MODE
1079 #define CFG_PLATFORM_POWER_POLICY_MODE (BLDCFG_PLATFORM_POWER_POLICY_MODE)
1080#else
1081 #define CFG_PLATFORM_POWER_POLICY_MODE (Performance)
1082#endif
1083
1084#ifdef BLDCFG_PCI_MMIO_BASE
1085 #define CFG_PCI_MMIO_BASE (BLDCFG_PCI_MMIO_BASE)
1086#else
1087 #define CFG_PCI_MMIO_BASE (0)
1088#endif
1089
1090#ifdef BLDCFG_PCI_MMIO_SIZE
1091 #define CFG_PCI_MMIO_SIZE (BLDCFG_PCI_MMIO_SIZE)
1092#else
1093 #define CFG_PCI_MMIO_SIZE (0)
1094#endif
1095
1096#ifdef BLDCFG_AP_MTRR_SETTINGS_LIST
1097 #define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST)
1098#else
Angel Pons41b820c2020-05-21 00:58:33 +0200[diff] [blame^]1099 #define CFG_AP_MTRR_SETTINGS_LIST (&OntarioApMtrrSettingsList)
Kyösti Mälkki206e1572016-05-18 14:04:45 +0300[diff] [blame]1100#endif
1101
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1102/*---------------------------------------------------------------------------
1103 * Processing the options: Third, perform the option cross checks
1104 *--------------------------------------------------------------------------*/
1105// Assure that at least one type of memory support is included
1106#if OPTION_UDIMMS == FALSE
1107 #if OPTION_RDIMMS == FALSE
1108 #if OPTION_SODIMMS == FALSE
1109 #if OPTION_LRDIMMS == FALSE
1110 #error BLDOPT: No DIMM support selected. Either BLDOPT_REMOVE_UDIMMS_SUPPORT or BLDOPT_REMOVE_RDIMMS_SUPPORT or BLDOPT_REMOVE_SODIMMS_SUPPORT or BLDOPT_REMOVE_LRDIMMS_SUPPORT must be FALSE.
1111 #endif
1112 #endif
1113 #endif
1114#endif
1115// Ensure at least one dimm type is capable
1116#if CFG_MEMORY_RDIMM_CAPABLE == FALSE
1117 #if CFG_MEMORY_UDIMM_CAPABLE == FALSE
1118 #if CFG_MEMORY_SODIMM_CAPABLE == FALSE
1119 #if CFG_MEMORY_LRDIMM_CAPABLE == FALSE
1120 #error BLDCFG: No dimm type is capable
1121 #endif
1122 #endif
1123 #endif
1124#endif
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1125// Turn off multi-socket based features if only one node...
1126#if OPTION_MULTISOCKET == FALSE
1127 #undef OPTION_PARALLEL_TRAINING
1128 #define OPTION_PARALLEL_TRAINING FALSE
1129 #undef OPTION_NODE_INTERLEAVE
1130 #define OPTION_NODE_INTERLEAVE FALSE
1131#endif
1132// Ensure that at least one write leveling option is selected
1133#if OPTION_DDR3 == TRUE
1134 #if OPTION_HW_WRITE_LEV_TRAINING == FALSE
1135 #if OPTION_SW_WRITE_LEV_TRAINING == FALSE
1136 #error No Write leveling option selected for DDR3
1137 #endif
1138 #endif
1139 #if OPTION_SW_DRAM_INIT == FALSE
1140 #error Software dram init must be enabled for DDR3 dimms
1141 #endif
1142#endif
1143// Ensure at least one DQS receiver training option is selected
1144#if OPTION_HW_DQS_REC_EN_TRAINING == FALSE
1145 #if OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == FALSE
1146 #if OPTION_OPT_SW_DQS_REC_EN_TRAINING == FALSE
1147 #error No DQS receiver training option has been slected
1148 #endif
1149 #endif
1150#endif
1151// Ensure at least one Rd Wr position training option has been selected
1152#if OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == FALSE
1153 #if OPTION_OPT_SW_RD_WR_POS_TRAINING == FALSE
1154 #error No Rd Wr position training option has been selected
1155 #endif
1156#endif
1157// Ensure at least one dram init option has been selected
1158#if OPTION_HW_DRAM_INIT == FALSE
1159 #if OPTION_SW_DRAM_INIT == FALSE
1160 #error No Dram init option has been selected
1161 #endif
1162#endif
1163// Ensure the frequency limit is valid
1164#if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1866_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 933)
1165 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 800)
1166 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1333_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 667)
1167 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1066_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 533)
1168 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR800_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 400)
1169 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR667_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 333)
1170 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR533_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 266)
1171 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR400_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 200)
1172 #error BLDCFG: Unsupported memory bus frequency
1173 #endif
1174 #endif
1175 #endif
1176 #endif
1177 #endif
1178 #endif
1179 #endif
1180#endif
1181// Ensure timing mode is valid
1182#if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC
1183 #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED
1184 #if CFG_TIMING_MODE_SELECT != TIMING_MODE_AUTO
1185 #error BLDCFG: Invalid timing mode is set
1186 #endif
1187 #endif
1188#endif
1189// Ensure the scrub rate is valid
1190#if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF))
1191 #error BLDCFG: Unsupported dram scrub rate set
1192#endif
1193#if CFG_SCRUB_L2_RATE > 0x16
1194 #error BLDCFG: Unsupported L2 scrubber rate set
1195#endif
1196#if CFG_SCRUB_L3_RATE > 0x16
1197 #error BLDCFG: unsupported L3 scrubber rate set
1198#endif
1199#if CFG_SCRUB_IC_RATE > 0x16
1200 #error BLDCFG: Unsupported Instruction cache scrub rate set
1201#endif
1202#if CFG_SCRUB_DC_RATE > 0x16
1203 #error BLDCFG: Unsupported Dcache scrub rate set
1204#endif
1205// Ensure Quad rank dimm type is valid
1206#if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED
1207 #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED
1208 #error BLDCFG: Invalid quad rank dimm type set
1209 #endif
1210#endif
1211// Ensure ECC symbol size is valid
1212#if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG
1213 #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4
1214 #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X8
1215 #error BLDCFG: Invalid Ecc symbol size set
1216 #endif
1217 #endif
1218#endif
1219// Ensure power down mode is valid
1220#if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT
1221 #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL
1222 #error BLDCFG: Invalid power down mode set
1223 #endif
1224#endif
1225
1226/*****************************************************************************
1227 *
1228 * Process the option logic, setting local control variables
1229 *
1230 ****************************************************************************/
1231#if OPTION_ACPI_PSTATES == TRUE
1232 #define OPTFCN_ACPI_TABLES CreateAcpiTablesMain
1233 #define OPTFCN_GATHER_DATA PStateGatherData
1234 #if OPTION_MULTISOCKET == TRUE
1235 #define OPTFCN_PSTATE_LEVELING PStateLeveling
1236 #else
1237 #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess
1238 #endif
1239#else
1240 #define OPTFCN_ACPI_TABLES CommonReturnAgesaSuccess
1241 #define OPTFCN_GATHER_DATA CommonReturnAgesaSuccess
1242 #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess
1243#endif
1244
1245
1246/*****************************************************************************
1247 *
1248 * Include the structure definitions for the defaults table structures
1249 *
1250 ****************************************************************************/
Kyösti Mälkki062ef1c2016-04-19 15:18:02 +0300[diff] [blame]1251#include <CommonReturns.h>
1252#include <agesa-entry-cfg.h>
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1253#include "Options.h"
1254#include "OptionCpuFamiliesInstall.h"
1255#include "OptionsHt.h"
1256#include "OptionHtInstall.h"
1257#include "OptionMemory.h"
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1258#include "OptionMemoryInstall.h"
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1259#include "OptionCpuFeaturesInstall.h"
1260#include "OptionDmi.h"
1261#include "OptionDmiInstall.h"
1262#include "OptionPstate.h"
1263#include "OptionPstateInstall.h"
1264#include "OptionWhea.h"
1265#include "OptionWheaInstall.h"
1266#include "OptionSrat.h"
1267#include "OptionSratInstall.h"
1268#include "OptionSlit.h"
1269#include "OptionSlitInstall.h"
1270#include "OptionMultiSocket.h"
1271#include "OptionMultiSocketInstall.h"
1272#include "OptionIdsInstall.h"
1273#include "OptionGfxRecovery.h"
1274#include "OptionGfxRecoveryInstall.h"
1275#include "OptionGnb.h"
1276#include "OptionGnbInstall.h"
1277#include "OptionS3ScriptInstall.h"
1278
1279
1280/*****************************************************************************
1281 *
1282 * Generate the output structures (defaults tables)
1283 *
1284 ****************************************************************************/
1285BUILD_OPT_CFG UserOptions = {
1286 { // AGESA version string
1287 AGESA_CODE_SIGNATURE, // code header Signature
1288 AGESA_PACKAGE_STRING, // 8 character ID
1289 AGESA_VERSION_STRING, // 12 character version string
1290 0 // null string terminator
1291 },
1292 //Build Option Area
1293 OPTION_UDIMMS, //UDIMMS
1294 OPTION_RDIMMS, //RDIMMS
1295 OPTION_LRDIMMS, //LRDIMMS
1296 OPTION_ECC, //ECC
1297 OPTION_BANK_INTERLEAVE, //BANK_INTERLEAVE
1298 OPTION_DCT_INTERLEAVE, //DCT_INTERLEAVE
1299 OPTION_NODE_INTERLEAVE, //NODE_INTERLEAVE
1300 OPTION_PARALLEL_TRAINING, //PARALLEL_TRAINING
1301 OPTION_ONLINE_SPARE, //ONLINE_SPARE
1302 OPTION_MEM_RESTORE, //MEM CONTEXT RESTORE
1303 OPTION_MULTISOCKET, //MULTISOCKET
1304 OPTION_ACPI_PSTATES, //ACPI_PSTATES
1305 OPTION_SRAT, //SRAT
1306 OPTION_SLIT, //SLIT
1307 OPTION_WHEA, //WHEA
1308 OPTION_DMI, //DMI
1309 OPTION_EARLY_SAMPLES, //EARLY_SAMPLES
1310 OPTION_ADDR_TO_CS_TRANSLATOR, //ADDR_TO_CS_TRANSLATOR
1311
1312 //Build Configuration Area
1313 CFG_PCI_MMIO_BASE,
1314 CFG_PCI_MMIO_SIZE,
1315 {
1316 // CoreVrm
1317 {
1318 CFG_VRM_CURRENT_LIMIT, // VrmCurrentLimit
1319 CFG_VRM_LOW_POWER_THRESHOLD, // VrmLowPowerThershold
1320 CFG_VRM_SLEW_RATE, // VrmSlewRate
1321 CFG_VRM_ADDITIONAL_DELAY, // VrmAdditionalDelay
1322 CFG_VRM_HIGH_SPEED_ENABLE, // VrmHiSpeedEnable
1323 CFG_VRM_INRUSH_CURRENT_LIMIT // VrmInrushCurrentLimit
1324 },
1325 // NbVrm
1326 {
1327 CFG_VRM_NB_CURRENT_LIMIT, // VrmNbCurrentLimit
1328 CFG_VRM_NB_LOW_POWER_THRESHOLD, // VrmNbLowPowerThershold
1329 CFG_VRM_NB_SLEW_RATE, // VrmNbSlewRate
1330 CFG_VRM_NB_ADDITIONAL_DELAY, // VrmNbAdditionalDelay
1331 CFG_VRM_NB_HIGH_SPEED_ENABLE, // VrmNbHiSpeedEnable
1332 CFG_VRM_NB_INRUSH_CURRENT_LIMIT // VrmNbInrushCurrentLimit
1333 }
1334 },
1335 CFG_PLAT_NUM_IO_APICS, //PlatformApicIoNumber
1336 CFG_MEM_INIT_PSTATE, //MemoryInitPstate
1337 CFG_C1E_MODE, //C1eMode
1338 CFG_C1E_OPDATA, //C1ePlatformData
1339 CFG_C1E_OPDATA1, //C1ePlatformData1
1340 CFG_C1E_OPDATA2, //C1ePlatformData2
1341 CFG_CSTATE_MODE, //CStateMode
1342 CFG_CSTATE_OPDATA, //CStatePlatformData
1343 CFG_CSTATE_IO_BASE_ADDRESS, //CStateIoBaseAddress
1344 CFG_CPB_MODE, //CpbMode
1345 CFG_CORE_LEVELING_MODE, //CoreLevelingCofig
1346 {
1347 CFG_PLATFORM_CONTROL_FLOW_MODE, // The platform's control flow mode.
1348 CFG_USE_HT_ASSIST, // CfgUseHtAssist
1349 CFG_USE_ATM_MODE, // CfgUseAtmMode
1350 CFG_USE_32_BYTE_REFRESH, // Display Refresh uses 32 byte packets.
1351 CFG_USE_VARIABLE_MCT_ISOC_PRIORITY, // The Memory controller will be set to Variable Isoc Priority.
1352 CFG_PLATFORM_POWER_POLICY_MODE // The platform's power policy mode.
1353 },
1354 (CPU_HT_DEEMPHASIS_LEVEL *)CFG_PLATFORM_DEEMPHASIS_LIST, // Deemphasis settings
1355 CFG_AMD_PLATFORM_TYPE, //AmdPlatformType
1356 CFG_AMD_PSTATE_CAP_VALUE, // Amd pstate ceiling enabling deck
1357
1358 CFG_MEMORY_BUS_FREQUENCY_LIMIT, // CfgMemoryBusFrequencyLimit
1359 CFG_MEMORY_MODE_UNGANGED, // CfgMemoryModeUnganged
1360 CFG_MEMORY_QUAD_RANK_CAPABLE, // CfgMemoryQuadRankCapable
1361 CFG_MEMORY_QUADRANK_TYPE, // CfgMemoryQuadrankType
1362 CFG_MEMORY_RDIMM_CAPABLE, // CfgMemoryRDimmCapable
1363 CFG_MEMORY_LRDIMM_CAPABLE, // CfgMemoryLRDimmCapable
1364 CFG_MEMORY_UDIMM_CAPABLE, // CfgMemoryUDimmCapable
1365 CFG_MEMORY_SODIMM_CAPABLE, // CfgMemorySodimmCapable
1366 CFG_MEMORY_ENABLE_BANK_INTERLEAVING, // CfgMemoryEnableBankInterleaving
1367 CFG_MEMORY_ENABLE_NODE_INTERLEAVING, // CfgMemoryEnableNodeInterleaving
1368 CFG_MEMORY_CHANNEL_INTERLEAVING, // CfgMemoryChannelInterleaving
1369 CFG_MEMORY_POWER_DOWN, // CfgMemoryPowerDown
1370 CFG_POWER_DOWN_MODE, // CfgPowerDownMode
1371 CFG_ONLINE_SPARE, // CfgOnlineSpare
1372 CFG_MEMORY_PARITY_ENABLE, // CfgMemoryParityEnable
1373 CFG_BANK_SWIZZLE, // CfgBankSwizzle
1374 CFG_TIMING_MODE_SELECT, // CfgTimingModeSelect
1375 CFG_MEMORY_CLOCK_SELECT, // CfgMemoryClockSelect
1376 CFG_DQS_TRAINING_CONTROL, // CfgDqsTrainingControl
1377 CFG_IGNORE_SPD_CHECKSUM, // CfgIgnoreSpdChecksum
1378 CFG_USE_BURST_MODE, // CfgUseBurstMode
1379 CFG_MEMORY_ALL_CLOCKS_ON, // CfgMemoryAllClocksOn
1380 CFG_ENABLE_ECC_FEATURE, // CfgEnableEccFeature
1381 CFG_ECC_REDIRECTION, // CfgEccRedirection
1382 CFG_SCRUB_DRAM_RATE, // CfgScrubDramRate
1383 CFG_SCRUB_L2_RATE, // CfgScrubL2Rate
1384 CFG_SCRUB_L3_RATE, // CfgScrubL3Rate
1385 CFG_SCRUB_IC_RATE, // CfgScrubIcRate
1386 CFG_SCRUB_DC_RATE, // CfgScrubDcRate
1387 CFG_ECC_SYNC_FLOOD, // CfgEccSyncFlood
1388 CFG_ECC_SYMBOL_SIZE, // CfgEccSymbolSize
1389 CFG_HEAP_DRAM_ADDRESS, // CfgHeapDramAddress
1390 CFG_1GB_ALIGN, // CfgNodeMem1GBAlign
1391 CFG_S3_LATE_RESTORE, // CfgS3LateRestore
1392 CFG_ACPI_PSTATE_PSD_INDPX, // CfgAcpiPstateIndependent
1393 (AP_MTRR_SETTINGS *) CFG_AP_MTRR_SETTINGS_LIST, // CfgApMtrrSettingsList
1394 CFG_UMA_MODE, // CfgUmaMode
1395 CFG_UMA_SIZE, // CfgUmaSize
1396 CFG_UMA_ABOVE4G, // CfgUmaAbove4G
1397 CFG_UMA_ALIGNMENT, // CfgUmaAlignment
1398 CFG_PROCESSOR_SCOPE_IN_SB, // CfgProcessorScopeInSb
1399 CFG_PROCESSOR_SCOPE_NAME0, // CfgProcessorScopeName0
1400 CFG_PROCESSOR_SCOPE_NAME1, // CfgProcessorScopeName1
1401 CFG_GNB_HD_AUDIO, // CfgGnbHdAudio
1402 CFG_ABM_SUPPORT, // CfgAbmSupport
1403 CFG_DYNAMIC_REFRESH_RATE, // CfgDynamicRefreshRate
1404 CFG_LCD_BACK_LIGHT_CONTROL, // CfgLcdBackLightControl
1405 CFG_GNB_STEREO_3D_PINOUT, // CfgGnb3dStereoPinIndex
1406 CFG_TEMP_PCIE_MMIO_BASE_ADDRESS, // CfgTempPcieMmioBaseAddress
1407 CFG_GNB_IGPU_SSID, // CfgGnbIGPUSSID
1408 CFG_GNB_HDAUDIO_SSID, // CfgGnbHDAudioSSID
1409 CFG_GNB_PCIE_SSID, // CfgGnbPcieSSID
1410 CFG_GFX_LVDS_SPREAD_SPECTRUM, // CfgLvdsSpreadSpectrum
1411 CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE, // CfgLvdsSpreadSpectrumRate
1412
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]1413 {{
1414 CFG_LVDS_MISC_888_FPDI_MODE, // CfgLvdsMiscControl
1415 CFG_LVDS_MISC_DL_CH_SWAP, // CfgLvdsMiscControl
1416 CFG_LVDS_MISC_VSYNC_ACTIVE_LOW, // CfgLvdsMiscControl
1417 CFG_LVDS_MISC_HSYNC_ACTIVE_LOW, // CfgLvdsMiscControl
1418 CFG_LVDS_MISC_BLON_ACTIVE_LOW, // CfgLvdsMiscControl
1419 }},
1420 CFG_PCIE_REFCLK_SPREAD_SPECTRUM, // CfgPcieRefClkSpreadSpectrum
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1421 0, //reserved...
1422};
1423
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1424
1425CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] =
1426{
1427 IDS_LATE_RUN_AP_TASK
1428 // Get DMI info
1429 CPU_DMI_AP_GET_TYPE4_TYPE7
1430 // Probe filter enable
1431 HT_ASSIST_AP_DISABLE_CACHE
1432 HT_ASSIST_AP_ENABLE_CACHE
1433
1434 { 0, NULL }
1435};
1436
1437#if AGESA_ENTRY_INIT_RESET == TRUE
1438 #if IDSOPT_IDS_ENABLED == TRUE
1439 #if IDSOPT_TRACING_ENABLED == TRUE
1440 #define MAKE_DBG_STR(x, y) MAKE_AS_A_STRING(x : y)
1441 CONST CHAR8 *BldOptDebugOutput[] = {
1442 #if IDS_TRACE_SHOW_BLD_OPT_CFG == TRUE
1443 //Build Option Area
1444 MAKE_DBG_STR (\nOptUDIMM, OPTION_UDIMMS)
1445 MAKE_DBG_STR (\nOptRDIMM, OPTION_RDIMMS)
1446 MAKE_DBG_STR (\nOptLRDIMM, OPTION_LRDIMMS)
1447 MAKE_DBG_STR (\nOptECC, OPTION_ECC)
1448 MAKE_DBG_STR (\nOptCsIntlv, OPTION_BANK_INTERLEAVE)
1449 MAKE_DBG_STR (\nOptDctIntlv, OPTION_DCT_INTERLEAVE)
1450 MAKE_DBG_STR (\nOptNodeIntlv, OPTION_NODE_INTERLEAVE)
1451 //MAKE_DBG_STR (\nOptParallelTraining, OPTION_PARALLEL_TRAINING)
1452 MAKE_DBG_STR (\nOptOnlineSpare, OPTION_ONLINE_SPARE)
1453 MAKE_DBG_STR (\nOptAddr2CsTranslator, OPTION_ADDR_TO_CS_TRANSLATOR)
1454 MAKE_DBG_STR (\nOptMemRestore, OPTION_MEM_RESTORE)
1455 MAKE_DBG_STR (\nOptMultiSocket, OPTION_MULTISOCKET)
1456 MAKE_DBG_STR (\nOptPstates, OPTION_ACPI_PSTATES)
1457 MAKE_DBG_STR (\nOptSRAT, OPTION_SRAT)
1458 MAKE_DBG_STR (\nOptSLIT, OPTION_SLIT)
1459 MAKE_DBG_STR (\nOptWHEA, OPTION_WHEA)
1460 MAKE_DBG_STR (\nOptDMI, OPTION_DMI)
1461 MAKE_DBG_STR (\nOptEarlySamples, OPTION_EARLY_SAMPLES),
1462
1463 //Build Configuration Area
1464 // CoreVrm
1465 MAKE_DBG_STR (\nVrmCurrentLimit , CFG_VRM_CURRENT_LIMIT)
1466 MAKE_DBG_STR (\nVrmLowPowerThreshold , CFG_VRM_LOW_POWER_THRESHOLD)
1467 MAKE_DBG_STR (\nVrmSlewRate , CFG_VRM_SLEW_RATE)
1468 MAKE_DBG_STR (\nVrmAdditionalDelay , CFG_VRM_ADDITIONAL_DELAY)
1469 MAKE_DBG_STR (\nVrmHiSpeedEnable , CFG_VRM_HIGH_SPEED_ENABLE)
1470 MAKE_DBG_STR (\nVrmInrushCurrentLimit, CFG_VRM_INRUSH_CURRENT_LIMIT)
1471 // NbVrm
1472 MAKE_DBG_STR (\nNbVrmCurrentLimit , CFG_VRM_NB_CURRENT_LIMIT)
1473 MAKE_DBG_STR (\nNbVrmLowPowerThreshold , CFG_VRM_NB_LOW_POWER_THRESHOLD)
1474 MAKE_DBG_STR (\nNbVrmSlewRate , CFG_VRM_NB_SLEW_RATE)
1475 MAKE_DBG_STR (\nNbVrmAdditionalDelay , CFG_VRM_NB_ADDITIONAL_DELAY)
1476 MAKE_DBG_STR (\nNbVrmHiSpeedEnable , CFG_VRM_NB_HIGH_SPEED_ENABLE)
1477 MAKE_DBG_STR (\nNbVrmInrushCurrentLimit, CFG_VRM_NB_INRUSH_CURRENT_LIMIT),
1478
1479 MAKE_DBG_STR (\nNumIoApics , CFG_PLAT_NUM_IO_APICS)
1480 MAKE_DBG_STR (\nMemInitPstate , CFG_MEM_INIT_PSTATE)
1481 MAKE_DBG_STR (\nC1eMode , CFG_C1E_MODE)
1482 MAKE_DBG_STR (\nC1eOpData , CFG_C1E_OPDATA)
1483 MAKE_DBG_STR (\nC1eOpdata1 , CFG_C1E_OPDATA1)
1484 MAKE_DBG_STR (\nC1eOpdata2 , CFG_C1E_OPDATA2)
1485 MAKE_DBG_STR (\nCStateMode , CFG_CSTATE_MODE)
1486 MAKE_DBG_STR (\nCStateOpData , CFG_CSTATE_OPDATA)
1487 MAKE_DBG_STR (\nCStateIoBaseAddr , CFG_CSTATE_IO_BASE_ADDRESS)
1488 MAKE_DBG_STR (\nCpbMode , CFG_CPB_MODE)
1489 MAKE_DBG_STR (\nCoreLevelingMode , CFG_CORE_LEVELING_MODE),
1490
1491 MAKE_DBG_STR (\nControlFlowMode , CFG_PLATFORM_CONTROL_FLOW_MODE)
1492 MAKE_DBG_STR (\nUseHtAssist , CFG_USE_HT_ASSIST)
1493 MAKE_DBG_STR (\nUseAtmMode , CFG_USE_ATM_MODE)
1494 MAKE_DBG_STR (\nUse32ByteRefresh , CFG_USE_32_BYTE_REFRESH)
1495 MAKE_DBG_STR (\nUseVarMctIsocPriority , CFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
1496 MAKE_DBG_STR (\nPowerPolicy , CFG_PLATFORM_POWER_POLICY_MOD)
1497
1498 MAKE_DBG_STR (\nDeemphasisList , CFG_PLATFORM_DEEMPHASIS_LIST)
1499
1500 MAKE_DBG_STR (\nPciMmioAddr , CFG_PCI_MMIO_BASE)
1501 MAKE_DBG_STR (\nPciMmioSize , CFG_PCI_MMIO_SIZE)
1502 MAKE_DBG_STR (\nPlatformType , CFG_AMD_PLATFORM_TYPE)
1503 MAKE_DBG_STR (\nPstateCapValue , CFG_AMD_PSTATE_CAP_VALUE),
1504
1505 MAKE_DBG_STR (\nMemBusFreqLimit , CFG_MEMORY_BUS_FREQUENCY_LIMIT)
1506 MAKE_DBG_STR (\nTimingModeSelect , CFG_TIMING_MODE_SELECT)
1507 MAKE_DBG_STR (\nMemoryClockSelect , CFG_MEMORY_CLOCK_SELECT)
1508
1509 MAKE_DBG_STR (\nMemUnganged , CFG_MEMORY_MODE_UNGANGED)
1510 MAKE_DBG_STR (\nQRCap , CFG_MEMORY_QUAD_RANK_CAPABLE)
1511 MAKE_DBG_STR (\nQRType , CFG_MEMORY_QUADRANK_TYPE)
1512 MAKE_DBG_STR (\nRDimmCap , CFG_MEMORY_RDIMM_CAPABLE)
1513 MAKE_DBG_STR (\nLRDimmCap , CFG_MEMORY_LRDIMM_CAPABLE)
1514 MAKE_DBG_STR (\nUDimmCap , CFG_MEMORY_UDIMM_CAPABLE)
1515 MAKE_DBG_STR (\nSODimmCap , CFG_MEMORY_SODIMM_CAPABLE)
1516 MAKE_DBG_STR (\nDqsTrainingControl , CFG_DQS_TRAINING_CONTROL)
1517 MAKE_DBG_STR (\nIgnoreSpdChecksum , CFG_IGNORE_SPD_CHECKSUM)
1518 MAKE_DBG_STR (\nUseBurstMode , CFG_USE_BURST_MODE)
1519 MAKE_DBG_STR (\nAllMemClkOn , CFG_MEMORY_ALL_CLOCKS_ON),
1520
1521 MAKE_DBG_STR (\nPowerDownEn , CFG_MEMORY_POWER_DOWN)
1522 MAKE_DBG_STR (\nPowerDownMode , CFG_POWER_DOWN_MODE)
1523 MAKE_DBG_STR (\nOnlineSpare , CFG_ONLINE_SPARE)
1524 MAKE_DBG_STR (\nAddrParityEn , CFG_MEMORY_PARITY_ENABLE)
1525 MAKE_DBG_STR (\nBankSwizzle , CFG_BANK_SWIZZLE)
1526 MAKE_DBG_STR (\nCsIntlvEn , CFG_MEMORY_ENABLE_BANK_INTERLEAVING)
1527 MAKE_DBG_STR (\nNodeIntlvEn , CFG_MEMORY_ENABLE_NODE_INTERLEAVING)
1528 MAKE_DBG_STR (\nDctIntlvEn , CFG_MEMORY_CHANNEL_INTERLEAVING),
1529
1530 MAKE_DBG_STR (\nUmaMode , CFG_UMA_MODE)
1531 MAKE_DBG_STR (\nUmaSize , CFG_UMA_SIZE)
1532 MAKE_DBG_STR (\nUmaAbove4G , CFG_UMA_ABOVE4G)
1533 MAKE_DBG_STR (\nUmaAlignment , CFG_UMA_ALIGNMENT)
1534
1535 MAKE_DBG_STR (\nEccEn , CFG_ENABLE_ECC_FEATURE)
1536 MAKE_DBG_STR (\nEccRedirect , CFG_ECC_REDIRECTION)
1537 MAKE_DBG_STR (\nScrubDramRate , CFG_SCRUB_DRAM_RATE)
1538 MAKE_DBG_STR (\nScrubL2Rate , CFG_SCRUB_L2_RATE)
1539 MAKE_DBG_STR (\nScrubL3Rate , CFG_SCRUB_L3_RATE)
1540 MAKE_DBG_STR (\nScrubIcRate , CFG_SCRUB_IC_RATE)
1541 MAKE_DBG_STR (\nScrubDcRate , CFG_SCRUB_DC_RATE)
1542 MAKE_DBG_STR (\nEccSyncFlood , CFG_ECC_SYNC_FLOOD)
1543 MAKE_DBG_STR (\nEccSymbolSize , CFG_ECC_SYMBOL_SIZE)
1544 MAKE_DBG_STR (\nHeapDramAddress , CFG_HEAP_DRAM_ADDRESS)
1545 MAKE_DBG_STR (\nNodeMem1GBAlign , CFG_1GB_ALIGN),
1546
1547 MAKE_DBG_STR (\nS3LateRestore , CFG_S3_LATE_RESTORE)
1548 MAKE_DBG_STR (\nAcpiPstateIndependent , CFG_ACPI_PSTATE_PSD_INDPX)
1549
1550 MAKE_DBG_STR (\nApMtrrSettingsList , CFG_AP_MTRR_SETTINGS_LIST)
1551
1552 MAKE_DBG_STR (\nProcessorScopeInSb , CFG_PROCESSOR_SCOPE_IN_SB)
1553 MAKE_DBG_STR (\nProcessorScopeName0 , CFG_PROCESSOR_SCOPE_NAME0)
1554 MAKE_DBG_STR (\nProcessorScopeName1 , CFG_PROCESSOR_SCOPE_NAME1)
1555 MAKE_DBG_STR (\nGnbHdAudio , CFG_GNB_HD_AUDIO)
1556 MAKE_DBG_STR (\nAbmSupport , CFG_ABM_SUPPORT)
1557 MAKE_DBG_STR (\nDynamicRefreshRate , CFG_DYNAMIC_REFRESH_RATE)
1558 MAKE_DBG_STR (\nLcdBackLightControl , CFG_LCD_BACK_LIGHT_CONTROL)
1559 MAKE_DBG_STR (\nGnb3dStereoPinIndex , CFG_GNB_STEREO_3D_PINOUT)
1560 MAKE_DBG_STR (\nTempPcieMmioBaseAddress, CFG_TEMP_PCIE_MMIO_BASE_ADDRESS),
1561 MAKE_DBG_STR (\nCfgGnbIGPUSSID , CFG_GNB_IGPU_SSID),
1562 MAKE_DBG_STR (\nCfgGnbHDAudioSSID , CFG_GNB_HDAUDIO_SSID),
1563 MAKE_DBG_STR (\nCfgGnbPcieSSID , CFG_GNB_PCIE_SSID),
1564
1565 MAKE_DBG_STR (\nCfgLvdsSpreadSpectrum , CFG_GFX_LVDS_SPREAD_SPECTRUM),
1566 MAKE_DBG_STR (\nCfgLvdsSpreadSpectrumRate , CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE),
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]1567 MAKE_DBG_STR (\nCfgLvdsMiscControl.FpdiMode , CFG_LVDS_MISC_888_FPDI_MODE),
1568 MAKE_DBG_STR (\nCfgLvdsMiscControl.DlChSwap , CFG_LVDS_MISC_DL_CH_SWAP),
1569 MAKE_DBG_STR (\nCfgLvdsMiscControl.VsyncActiveLow , CFG_LVDS_MISC_VSYNC_ACTIVE_LOW),
1570 MAKE_DBG_STR (\nCfgLvdsMiscControl.HsyncActiveLow , CFG_LVDS_MISC_HSYNC_ACTIVE_LOW),
1571 MAKE_DBG_STR (\nCfgLvdsMiscControl.BLONActiveLow , CFG_LVDS_MISC_BLON_ACTIVE_LOW),
1572 MAKE_DBG_STR (\nCfgPcieRefClkSpreadSpectrum , CFG_PCIE_REFCLK_SPREAD_SPECTRUM),
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1573 #endif
1574 NULL
1575 };
1576 #endif
1577 #endif
1578#endif