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review.coreboot.org / coreboot / e963b388ba552c0d4179425d55171775df3606e2 / . / src / vendorcode / amd / agesa / f14 / Include / PlatformInstall.h
blob: 8641589f96ba743a46bbe9ce5e984f7d80e3a9c6 [file] [log] [blame]
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * Install of build options for a combination of package type, processor, and features.
6 *
7 * This file generates the defaults tables for the all platform solution
8 * combinations. The documented build options are imported from a user
9 * controlled file for processing.
10 *
11 * @xrefitem bom "File Content Label" "Release Content"
12 * @e project: AGESA
13 * @e sub-project: Core
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]14 * @e \$Revision: 47417 $ @e \$Date: 2011-02-18 12:48:20 -0700 (Fri, 18 Feb 2011) $
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]15 */
16/*
17 *****************************************************************************
18 *
19 * Copyright (c) 2011, Advanced Micro Devices, Inc.
20 * All rights reserved.
Edward O'Callaghane963b382014-07-06 19:27:14 +1000[diff] [blame^]21 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions are met:
24 * * Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * * Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in the
28 * documentation and/or other materials provided with the distribution.
Edward O'Callaghane963b382014-07-06 19:27:14 +1000[diff] [blame^]29 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
30 * its contributors may be used to endorse or promote products derived
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]31 * from this software without specific prior written permission.
Edward O'Callaghane963b382014-07-06 19:27:14 +1000[diff] [blame^]32 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
35 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
36 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
37 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
38 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
40 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
41 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
42 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Edward O'Callaghane963b382014-07-06 19:27:14 +1000[diff] [blame^]43 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]44 * ***************************************************************************
45 *
46 */
47
48/*****************************************************************************
49 *
50 * Start processing the user options: First, set default settings
51 *
52 ****************************************************************************/
53
54/* Available options for image builds.
55 *
56 * As part of the image build for each image, define the options below to select the
57 * AGESA entry points included in that image. Turn these on in your option c file, not
58 * here.
59 */
60// #define AGESA_ENTRY_INIT_RESET TRUE
61// #define AGESA_ENTRY_INIT_RECOVERY TRUE
62// #define AGESA_ENTRY_INIT_EARLY TRUE
63// #define AGESA_ENTRY_INIT_POST TRUE
64// #define AGESA_ENTRY_INIT_ENV TRUE
65// #define AGESA_ENTRY_INIT_MID TRUE
66// #define AGESA_ENTRY_INIT_LATE TRUE
67// #define AGESA_ENTRY_INIT_S3SAVE TRUE
68// #define AGESA_ENTRY_INIT_RESUME TRUE
69// #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
70// #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
71
72/* Defaults for private/internal build control settings */
73/* Available options for image builds.
74 *
75 * As part of the image build for each image, define the options below to select the
76 * AGESA entry points included in that image.
77 */
78
79VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
80 //ModuleHeaderSignature
81 // Remove 'DOM$' as temp solution before update BinUtil.exe ,
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]82 Int32FromChar ('0', '0', '0', '0'),
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]83 //ModuleIdentifier[8]
84 AGESA_ID,
85 //ModuleVersion[12]
86 AGESA_VERSION_STRING,
87 //ModuleDispatcher
88 NULL,//(VOID *)(UINT64)((MODULE_ENTRY)AmdAgesaDispatcher),
89 //NextBlock
90 NULL
91};
92
93/* Process user desired AGESA entry points */
94#ifndef AGESA_ENTRY_INIT_RESET
95 #define AGESA_ENTRY_INIT_RESET FALSE
96#endif
97
98#ifndef AGESA_ENTRY_INIT_RECOVERY
99 #define AGESA_ENTRY_INIT_RECOVERY FALSE
100#endif
101
102#ifndef AGESA_ENTRY_INIT_EARLY
103 #define AGESA_ENTRY_INIT_EARLY FALSE
104#endif
105
106#ifndef AGESA_ENTRY_INIT_POST
107 #define AGESA_ENTRY_INIT_POST FALSE
108#endif
109
110#ifndef AGESA_ENTRY_INIT_ENV
111 #define AGESA_ENTRY_INIT_ENV FALSE
112#endif
113
114#ifndef AGESA_ENTRY_INIT_MID
115 #define AGESA_ENTRY_INIT_MID FALSE
116#endif
117
118#ifndef AGESA_ENTRY_INIT_LATE
119 #define AGESA_ENTRY_INIT_LATE FALSE
120#endif
121
122#ifndef AGESA_ENTRY_INIT_S3SAVE
123 #define AGESA_ENTRY_INIT_S3SAVE FALSE
124#endif
125
126#ifndef AGESA_ENTRY_INIT_RESUME
127 #define AGESA_ENTRY_INIT_RESUME FALSE
128#endif
129
130#ifndef AGESA_ENTRY_INIT_LATE_RESTORE
131 #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE
132#endif
133
134#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES
135 #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE
136#endif
137
138/* Default the late AP entry point to off. It can be enabled
139 by any family that may need the late AP functionality, or
140 by any feature code that may need it. The IBVs no longer
141 have control over this entry point. */
142#ifdef AGESA_ENTRY_LATE_RUN_AP_TASK
143 #undef AGESA_ENTRY_LATE_RUN_AP_TASK
144#endif
145#define AGESA_ENTRY_LATE_RUN_AP_TASK FALSE
146
147
148
149/* Process solution defined socket / family installations
150 *
151 * As part of the release package for each image, define the options below to select the
152 * AGESA processor support included in that image.
153 */
154
155/* Default sockets to off */
156#define OPTION_G34_SOCKET_SUPPORT FALSE
157#define OPTION_C32_SOCKET_SUPPORT FALSE
158#define OPTION_S1G3_SOCKET_SUPPORT FALSE
159#define OPTION_S1G4_SOCKET_SUPPORT FALSE
160#define OPTION_ASB2_SOCKET_SUPPORT FALSE
161#define OPTION_FS1_SOCKET_SUPPORT FALSE
162#define OPTION_FM1_SOCKET_SUPPORT FALSE
163#define OPTION_FP1_SOCKET_SUPPORT FALSE
164#define OPTION_FT1_SOCKET_SUPPORT FALSE
165#define OPTION_AM3_SOCKET_SUPPORT FALSE
166
167/* Default families to off */
168#define OPTION_FAMILY10H FALSE
169#define OPTION_FAMILY12H FALSE
170#define OPTION_FAMILY14H FALSE
171#define OPTION_FAMILY15H FALSE
172
173
174/* Enable the appropriate socket support */
175#ifdef INSTALL_G34_SOCKET_SUPPORT
176 #if INSTALL_G34_SOCKET_SUPPORT == TRUE
177 #undef OPTION_G34_SOCKET_SUPPORT
178 #define OPTION_G34_SOCKET_SUPPORT TRUE
179 #endif
180#endif
181
182#ifdef INSTALL_C32_SOCKET_SUPPORT
183 #if INSTALL_C32_SOCKET_SUPPORT == TRUE
184 #undef OPTION_C32_SOCKET_SUPPORT
185 #define OPTION_C32_SOCKET_SUPPORT TRUE
186 #endif
187#endif
188
189#ifdef INSTALL_S1G3_SOCKET_SUPPORT
190 #if INSTALL_S1G3_SOCKET_SUPPORT == TRUE
191 #undef OPTION_S1G3_SOCKET_SUPPORT
192 #define OPTION_S1G3_SOCKET_SUPPORT TRUE
193 #endif
194#endif
195
196#ifdef INSTALL_S1G4_SOCKET_SUPPORT
197 #if INSTALL_S1G4_SOCKET_SUPPORT == TRUE
198 #undef OPTION_S1G4_SOCKET_SUPPORT
199 #define OPTION_S1G4_SOCKET_SUPPORT TRUE
200 #endif
201#endif
202
203#ifdef INSTALL_ASB2_SOCKET_SUPPORT
204 #if INSTALL_ASB2_SOCKET_SUPPORT == TRUE
205 #undef OPTION_ASB2_SOCKET_SUPPORT
206 #define OPTION_ASB2_SOCKET_SUPPORT TRUE
207 #endif
208#endif
209
210#ifdef INSTALL_FS1_SOCKET_SUPPORT
211 #if INSTALL_FS1_SOCKET_SUPPORT == TRUE
212 #undef OPTION_FS1_SOCKET_SUPPORT
213 #define OPTION_FS1_SOCKET_SUPPORT TRUE
214 #endif
215#endif
216
217#ifdef INSTALL_FM1_SOCKET_SUPPORT
218 #if INSTALL_FM1_SOCKET_SUPPORT == TRUE
219 #undef OPTION_FM1_SOCKET_SUPPORT
220 #define OPTION_FM1_SOCKET_SUPPORT TRUE
221 #endif
222#endif
223
224#ifdef INSTALL_FP1_SOCKET_SUPPORT
225 #if INSTALL_FP1_SOCKET_SUPPORT == TRUE
226 #undef OPTION_FP1_SOCKET_SUPPORT
227 #define OPTION_FP1_SOCKET_SUPPORT TRUE
228 #endif
229#endif
230
231#ifdef INSTALL_FT1_SOCKET_SUPPORT
232 #if INSTALL_FT1_SOCKET_SUPPORT == TRUE
233 #undef OPTION_FT1_SOCKET_SUPPORT
234 #define OPTION_FT1_SOCKET_SUPPORT TRUE
235 #endif
236#endif
237
238#ifdef INSTALL_AM3_SOCKET_SUPPORT
239 #if INSTALL_AM3_SOCKET_SUPPORT == TRUE
240 #undef OPTION_AM3_SOCKET_SUPPORT
241 #define OPTION_AM3_SOCKET_SUPPORT TRUE
242 #endif
243#endif
244
245
246/* Enable the appropriate family support */
247// F10 is supported in G34, C32, S1g4, ASB2, S1g3, & AM3
248#ifdef INSTALL_FAMILY_10_SUPPORT
249 #if INSTALL_FAMILY_10_SUPPORT == TRUE
250 #undef OPTION_FAMILY10H
251 #define OPTION_FAMILY10H TRUE
252 #endif
253#endif
254
255// F12 is supported in FP1, FS1, & FM1
256#ifdef INSTALL_FAMILY_12_SUPPORT
257 #if INSTALL_FAMILY_12_SUPPORT == TRUE
258 #undef OPTION_FAMILY12H
259 #define OPTION_FAMILY12H TRUE
260 #endif
261#endif
262
263// F14 is supported in FT1
264#ifdef INSTALL_FAMILY_14_SUPPORT
265 #if INSTALL_FAMILY_14_SUPPORT == TRUE
266 #undef OPTION_FAMILY14H
267 #define OPTION_FAMILY14H TRUE
268 #endif
269#endif
270
271// F15 is supported in G34, C32, & AM3
272#ifdef INSTALL_FAMILY_15_SUPPORT
273 #if INSTALL_FAMILY_15_SUPPORT == TRUE
274 #undef OPTION_FAMILY15H
275 #define OPTION_FAMILY15H TRUE
276 #endif
277#endif
278
279
280/* Turn off families not required by socket designations */
281#if (OPTION_FAMILY10H == TRUE)
282 #if (OPTION_G34_SOCKET_SUPPORT == FALSE) && (OPTION_C32_SOCKET_SUPPORT == FALSE) && (OPTION_S1G3_SOCKET_SUPPORT == FALSE) && (OPTION_S1G4_SOCKET_SUPPORT == FALSE) && (OPTION_ASB2_SOCKET_SUPPORT == FALSE) && (OPTION_AM3_SOCKET_SUPPORT == FALSE)
283 #undef OPTION_FAMILY10H
284 #define OPTION_FAMILY10H FALSE
285 #endif
286#endif
287
288#if (OPTION_FAMILY12H == TRUE)
289 #if (OPTION_FS1_SOCKET_SUPPORT == FALSE) && (OPTION_FM1_SOCKET_SUPPORT == FALSE) && (OPTION_FP1_SOCKET_SUPPORT == FALSE)
290 #undef OPTION_FAMILY12H
291 #define OPTION_FAMILY12H FALSE
292 #endif
293#endif
294
295#if (OPTION_FAMILY14H == TRUE)
296 #if (OPTION_FT1_SOCKET_SUPPORT == FALSE)
297 #undef OPTION_FAMILY14H
298 #define OPTION_FAMILY14H FALSE
299 #endif
300#endif
301
302#if (OPTION_FAMILY15H == TRUE)
303 #if (OPTION_G34_SOCKET_SUPPORT == FALSE) && (OPTION_C32_SOCKET_SUPPORT == FALSE) && (OPTION_AM3_SOCKET_SUPPORT == FALSE)
304 #undef OPTION_FAMILY15H
305 #define OPTION_FAMILY15H FALSE
306 #endif
307#endif
308
309
310/* Check for invalid combinations of socket/family */
311#if (OPTION_G34_SOCKET_SUPPORT == TRUE)
312 #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H == FALSE)
313 #error No G34 supported families included in the build
314 #endif
315#endif
316
317#if (OPTION_C32_SOCKET_SUPPORT == TRUE)
318 #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H == FALSE)
319 #error No C32 supported families included in the build
320 #endif
321#endif
322
323#if (OPTION_S1G3_SOCKET_SUPPORT == TRUE)
324 #if (OPTION_FAMILY10H == FALSE)
325 #error No S1G3 supported families included in the build
326 #endif
327#endif
328
329#if (OPTION_S1G4_SOCKET_SUPPORT == TRUE)
330 #if (OPTION_FAMILY10H == FALSE)
331 #error No S1G4 supported families included in the build
332 #endif
333#endif
334
335#if (OPTION_ASB2_SOCKET_SUPPORT == TRUE)
336 #if (OPTION_FAMILY10H == FALSE)
337 #error No ASB2 supported families included in the build
338 #endif
339#endif
340
341#if (OPTION_FS1_SOCKET_SUPPORT == TRUE)
342 #if (OPTION_FAMILY12H == FALSE)
343 #error No FS1 supported families included in the build
344 #endif
345#endif
346
347#if (OPTION_FM1_SOCKET_SUPPORT == TRUE)
348 #if (OPTION_FAMILY12H == FALSE)
349 #error No FM1 supported families included in the build
350 #endif
351#endif
352
353#if (OPTION_FP1_SOCKET_SUPPORT == TRUE)
354 #if (OPTION_FAMILY12H == FALSE)
355 #error No FP1 supported families included in the build
356 #endif
357#endif
358
359#if (OPTION_FT1_SOCKET_SUPPORT == TRUE)
360 #if (OPTION_FAMILY14H == FALSE)
361 #error No FT1 supported families included in the build
362 #endif
363#endif
364
365#if (OPTION_AM3_SOCKET_SUPPORT == TRUE)
366 #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H == FALSE)
367 #error No AM3 supported families included in the build
368 #endif
369#endif
370
371
372/* Process AGESA private data
373 *
374 * Turn on appropriate CPU models and memory controllers,
375 * as well as some other memory controls.
376 */
377
378/* Default all models to off */
379#define OPTION_FAMILY10H_BL FALSE
380#define OPTION_FAMILY10H_DA FALSE
381#define OPTION_FAMILY10H_HY FALSE
382#define OPTION_FAMILY10H_PH FALSE
383#define OPTION_FAMILY10H_RB FALSE
384#define OPTION_FAMILY12H_LN FALSE
385#define OPTION_FAMILY14H_ON FALSE
386#define OPTION_FAMILY15H_OR FALSE
387
388/* Default all memory controllers to off */
389#define OPTION_MEMCTLR_DR FALSE
390#define OPTION_MEMCTLR_HY FALSE
391#define OPTION_MEMCTLR_OR FALSE
392#define OPTION_MEMCTLR_C32 FALSE
393#define OPTION_MEMCTLR_DA FALSE
394#define OPTION_MEMCTLR_LN FALSE
395#define OPTION_MEMCTLR_ON FALSE
396#define OPTION_MEMCTLR_Ni FALSE
397#define OPTION_MEMCTLR_PH FALSE
398#define OPTION_MEMCTLR_RB FALSE
399
400/* Default all memory controls to off */
401#define OPTION_HW_WRITE_LEV_TRAINING FALSE
402#define OPTION_SW_WRITE_LEV_TRAINING FALSE
403#define OPTION_CONTINOUS_PATTERN_GENERATION FALSE
404#define OPTION_HW_DQS_REC_EN_TRAINING FALSE
405#define OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING FALSE
406#define OPTION_OPT_SW_DQS_REC_EN_TRAINING FALSE
407#define OPTION_NON_OPT_SW_RD_WR_POS_TRAINING FALSE
408#define OPTION_OPT_SW_RD_WR_POS_TRAINING FALSE
409#define OPTION_MAX_RD_LAT_TRAINING FALSE
410#define OPTION_HW_DRAM_INIT FALSE
411#define OPTION_SW_DRAM_INIT FALSE
412#define OPTION_S3_MEM_SUPPORT FALSE
413#define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
414
415/* Defaults for public user options */
416#define OPTION_UDIMMS FALSE
417#define OPTION_RDIMMS FALSE
418#define OPTION_SODIMMS FALSE
419#define OPTION_LRDIMMS FALSE
420#define OPTION_DDR2 FALSE
421#define OPTION_DDR3 FALSE
422#define OPTION_ECC FALSE
423#define OPTION_BANK_INTERLEAVE FALSE
424#define OPTION_DCT_INTERLEAVE FALSE
425#define OPTION_NODE_INTERLEAVE FALSE
426#define OPTION_PARALLEL_TRAINING FALSE
427#define OPTION_ONLINE_SPARE FALSE
428#define OPTION_MEM_RESTORE FALSE
429#define OPTION_DIMM_EXCLUDE FALSE
430
431/* Default all CPU controls to off */
432#define OPTION_MULTISOCKET FALSE
433#define OPTION_SRAT FALSE
434#define OPTION_SLIT FALSE
435#define OPTION_HT_ASSIST FALSE
436#define OPTION_ATM_MODE FALSE
437#define OPTION_CPU_CORELEVLING FALSE
438#define OPTION_MSG_BASED_C1E FALSE
439#define OPTION_CPU_CFOH FALSE
440#define OPTION_C6_STATE FALSE
441#define OPTION_IO_CSTATE FALSE
442#define OPTION_CPB FALSE
443#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT FALSE
444#define OPTION_S3SCRIPT FALSE
445#define OPTION_GFX_RECOVERY FALSE
446
447/* Enable all private controls based on socket/family enables */
448#if (OPTION_G34_SOCKET_SUPPORT == TRUE)
449 #if (OPTION_FAMILY10H == TRUE)
450 #undef OPTION_FAMILY10H_HY
451 #define OPTION_FAMILY10H_HY TRUE
452 #undef OPTION_MEMCTLR_HY
453 #define OPTION_MEMCTLR_HY TRUE
454 #undef OPTION_HW_WRITE_LEV_TRAINING
455 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
456 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
457 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
458 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
459 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
460 #undef OPTION_MAX_RD_LAT_TRAINING
461 #define OPTION_MAX_RD_LAT_TRAINING TRUE
462 #undef OPTION_SW_DRAM_INIT
463 #define OPTION_SW_DRAM_INIT TRUE
464 #undef OPTION_S3_MEM_SUPPORT
465 #define OPTION_S3_MEM_SUPPORT TRUE
466 #undef OPTION_MULTISOCKET
467 #define OPTION_MULTISOCKET TRUE
468 #undef OPTION_SRAT
469 #define OPTION_SRAT TRUE
470 #undef OPTION_SLIT
471 #define OPTION_SLIT TRUE
472 #undef OPTION_HT_ASSIST
473 #define OPTION_HT_ASSIST TRUE
474 #undef OPTION_CPU_CORELEVLING
475 #define OPTION_CPU_CORELEVLING TRUE
476 #undef OPTION_MSG_BASED_C1E
477 #define OPTION_MSG_BASED_C1E TRUE
478 #undef OPTION_CPU_CFOH
479 #define OPTION_CPU_CFOH TRUE
480 #undef OPTION_UDIMMS
481 #define OPTION_UDIMMS TRUE
482 #undef OPTION_RDIMMS
483 #define OPTION_RDIMMS TRUE
484 #undef OPTION_SODIMMS
485 #define OPTION_SODIMMS TRUE
486 #undef OPTION_DDR3
487 #define OPTION_DDR3 TRUE
488 #undef OPTION_ECC
489 #define OPTION_ECC TRUE
490 #undef OPTION_BANK_INTERLEAVE
491 #define OPTION_BANK_INTERLEAVE TRUE
492 #undef OPTION_DCT_INTERLEAVE
493 #define OPTION_DCT_INTERLEAVE TRUE
494 #undef OPTION_NODE_INTERLEAVE
495 #define OPTION_NODE_INTERLEAVE TRUE
496 #undef OPTION_PARALLEL_TRAINING
497 #define OPTION_PARALLEL_TRAINING TRUE
498 #undef OPTION_MEM_RESTORE
499 #define OPTION_MEM_RESTORE TRUE
500 #undef OPTION_ONLINE_SPARE
501 #define OPTION_ONLINE_SPARE TRUE
502 #undef OPTION_DIMM_EXCLUDE
503 #define OPTION_DIMM_EXCLUDE TRUE
504 #endif
505 #if (OPTION_FAMILY15H == TRUE)
506 #undef OPTION_FAMILY15H_OR
507 #define OPTION_FAMILY15H_OR TRUE
508 #undef OPTION_MEMCTLR_OR
509 #define OPTION_MEMCTLR_OR TRUE
510 #undef OPTION_HW_WRITE_LEV_TRAINING
511 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
512 #undef OPTION_CONTINOUS_PATTERN_GENERATION
513 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
514 #undef OPTION_HW_DQS_REC_EN_TRAINING
515 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
516 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
517 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
518 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
519 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
520 #undef OPTION_MAX_RD_LAT_TRAINING
521 #define OPTION_MAX_RD_LAT_TRAINING TRUE
522 #undef OPTION_SW_DRAM_INIT
523 #define OPTION_SW_DRAM_INIT TRUE
524 #undef OPTION_S3_MEM_SUPPORT
525 #define OPTION_S3_MEM_SUPPORT TRUE
526 #undef OPTION_MULTISOCKET
527 #define OPTION_MULTISOCKET TRUE
528 #undef OPTION_C6_STATE
529 #define OPTION_C6_STATE TRUE
530 #undef OPTION_IO_CSTATE
531 #define OPTION_IO_CSTATE TRUE
532 #undef OPTION_CPB
533 #define OPTION_CPB TRUE
534 #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
535 #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE
536 #undef OPTION_SRAT
537 #define OPTION_SRAT TRUE
538 #undef OPTION_SLIT
539 #define OPTION_SLIT TRUE
540 #undef OPTION_HT_ASSIST
541 #define OPTION_HT_ASSIST TRUE
542 #undef OPTION_ATM_MODE
543 #define OPTION_ATM_MODE TRUE
544 #undef OPTION_CPU_CORELEVLING
545 #define OPTION_CPU_CORELEVLING TRUE
546 #undef OPTION_MSG_BASED_C1E
547 #define OPTION_MSG_BASED_C1E TRUE
548 #undef OPTION_CPU_CFOH
549 #define OPTION_CPU_CFOH TRUE
550 #undef OPTION_UDIMMS
551 #define OPTION_UDIMMS TRUE
552 #undef OPTION_RDIMMS
553 #define OPTION_RDIMMS TRUE
554 #undef OPTION_SODIMMS
555 #define OPTION_SODIMMS TRUE
556 #undef OPTION_LRDIMMS
557 #define OPTION_LRDIMMS TRUE
558 #undef OPTION_DDR3
559 #define OPTION_DDR3 TRUE
560 #undef OPTION_ECC
561 #define OPTION_ECC TRUE
562 #undef OPTION_BANK_INTERLEAVE
563 #define OPTION_BANK_INTERLEAVE TRUE
564 #undef OPTION_DCT_INTERLEAVE
565 #define OPTION_DCT_INTERLEAVE TRUE
566 #undef OPTION_NODE_INTERLEAVE
567 #define OPTION_NODE_INTERLEAVE TRUE
568 #undef OPTION_MEM_RESTORE
569 #define OPTION_MEM_RESTORE TRUE
570 #undef OPTION_ONLINE_SPARE
571 #define OPTION_ONLINE_SPARE TRUE
572 #undef OPTION_DIMM_EXCLUDE
573 #define OPTION_DIMM_EXCLUDE TRUE
574 #endif
575#endif
576
577#if (OPTION_C32_SOCKET_SUPPORT == TRUE)
578 #if (OPTION_FAMILY10H == TRUE)
579 #undef OPTION_FAMILY10H_HY
580 #define OPTION_FAMILY10H_HY TRUE
581 #undef OPTION_MEMCTLR_C32
582 #define OPTION_MEMCTLR_C32 TRUE
583 #undef OPTION_HW_WRITE_LEV_TRAINING
584 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
585 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
586 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
587 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
588 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
589 #undef OPTION_MAX_RD_LAT_TRAINING
590 #define OPTION_MAX_RD_LAT_TRAINING TRUE
591 #undef OPTION_SW_DRAM_INIT
592 #define OPTION_SW_DRAM_INIT TRUE
593 #undef OPTION_S3_MEM_SUPPORT
594 #define OPTION_S3_MEM_SUPPORT TRUE
595 #undef OPTION_ADDR_TO_CS_TRANSLATOR
596 #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
597 #undef OPTION_MULTISOCKET
598 #define OPTION_MULTISOCKET TRUE
599 #undef OPTION_SRAT
600 #define OPTION_SRAT TRUE
601 #undef OPTION_SLIT
602 #define OPTION_SLIT TRUE
603 #undef OPTION_HT_ASSIST
604 #define OPTION_HT_ASSIST TRUE
605 #undef OPTION_CPU_CORELEVLING
606 #define OPTION_CPU_CORELEVLING TRUE
607 #undef OPTION_MSG_BASED_C1E
608 #define OPTION_MSG_BASED_C1E TRUE
609 #undef OPTION_CPU_CFOH
610 #define OPTION_CPU_CFOH TRUE
611 #undef OPTION_UDIMMS
612 #define OPTION_UDIMMS TRUE
613 #undef OPTION_RDIMMS
614 #define OPTION_RDIMMS TRUE
615 #undef OPTION_SODIMMS
616 #define OPTION_SODIMMS TRUE
617 #undef OPTION_DDR3
618 #define OPTION_DDR3 TRUE
619 #undef OPTION_ECC
620 #define OPTION_ECC TRUE
621 #undef OPTION_BANK_INTERLEAVE
622 #define OPTION_BANK_INTERLEAVE TRUE
623 #undef OPTION_DCT_INTERLEAVE
624 #define OPTION_DCT_INTERLEAVE TRUE
625 #undef OPTION_NODE_INTERLEAVE
626 #define OPTION_NODE_INTERLEAVE TRUE
627 #undef OPTION_PARALLEL_TRAINING
628 #define OPTION_PARALLEL_TRAINING TRUE
629 #undef OPTION_MEM_RESTORE
630 #define OPTION_MEM_RESTORE TRUE
631 #undef OPTION_ONLINE_SPARE
632 #define OPTION_ONLINE_SPARE TRUE
633 #undef OPTION_DIMM_EXCLUDE
634 #define OPTION_DIMM_EXCLUDE TRUE
635 #endif
636 #if (OPTION_FAMILY15H == TRUE)
637 #undef OPTION_FAMILY15H_OR
638 #define OPTION_FAMILY15H_OR TRUE
639 #undef OPTION_MEMCTLR_OR
640 #define OPTION_MEMCTLR_OR TRUE
641 #undef OPTION_HW_WRITE_LEV_TRAINING
642 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
643 #undef OPTION_CONTINOUS_PATTERN_GENERATION
644 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
645 #undef OPTION_HW_DQS_REC_EN_TRAINING
646 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
647 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
648 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
649 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
650 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
651 #undef OPTION_MAX_RD_LAT_TRAINING
652 #define OPTION_MAX_RD_LAT_TRAINING TRUE
653 #undef OPTION_SW_DRAM_INIT
654 #define OPTION_SW_DRAM_INIT TRUE
655 #undef OPTION_S3_MEM_SUPPORT
656 #define OPTION_S3_MEM_SUPPORT TRUE
657 #undef OPTION_ADDR_TO_CS_TRANSLATOR
658 #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE
659 #undef OPTION_MULTISOCKET
660 #define OPTION_MULTISOCKET TRUE
661 #undef OPTION_C6_STATE
662 #define OPTION_C6_STATE TRUE
663 #undef OPTION_IO_CSTATE
664 #define OPTION_IO_CSTATE TRUE
665 #undef OPTION_CPB
666 #define OPTION_CPB TRUE
667 #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
668 #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE
669 #undef OPTION_SRAT
670 #define OPTION_SRAT TRUE
671 #undef OPTION_SLIT
672 #define OPTION_SLIT TRUE
673 #undef OPTION_HT_ASSIST
674 #define OPTION_HT_ASSIST TRUE
675 #undef OPTION_ATM_MODE
676 #define OPTION_ATM_MODE TRUE
677 #undef OPTION_CPU_CORELEVLING
678 #define OPTION_CPU_CORELEVLING TRUE
679 #undef OPTION_MSG_BASED_C1E
680 #define OPTION_MSG_BASED_C1E TRUE
681 #undef OPTION_CPU_CFOH
682 #define OPTION_CPU_CFOH TRUE
683 #undef OPTION_UDIMMS
684 #define OPTION_UDIMMS TRUE
685 #undef OPTION_RDIMMS
686 #define OPTION_RDIMMS TRUE
687 #undef OPTION_SODIMMS
688 #define OPTION_SODIMMS TRUE
689 #undef OPTION_LRDIMMS
690 #define OPTION_LRDIMMS TRUE
691 #undef OPTION_DDR3
692 #define OPTION_DDR3 TRUE
693 #undef OPTION_ECC
694 #define OPTION_ECC TRUE
695 #undef OPTION_BANK_INTERLEAVE
696 #define OPTION_BANK_INTERLEAVE TRUE
697 #undef OPTION_DCT_INTERLEAVE
698 #define OPTION_DCT_INTERLEAVE TRUE
699 #undef OPTION_NODE_INTERLEAVE
700 #define OPTION_NODE_INTERLEAVE TRUE
701 #undef OPTION_MEM_RESTORE
702 #define OPTION_MEM_RESTORE TRUE
703 #undef OPTION_ONLINE_SPARE
704 #define OPTION_ONLINE_SPARE TRUE
705 #undef OPTION_DIMM_EXCLUDE
706 #define OPTION_DIMM_EXCLUDE TRUE
707 #endif
708#endif
709
710#if (OPTION_S1G3_SOCKET_SUPPORT == TRUE)
711 #if (OPTION_FAMILY10H == TRUE)
712 #undef OPTION_FAMILY10H_BL
713 #define OPTION_FAMILY10H_BL TRUE
714 #undef OPTION_FAMILY10H_DA
715 #define OPTION_FAMILY10H_DA TRUE
716 #undef OPTION_MEMCTLR_DA
717 #define OPTION_MEMCTLR_DA TRUE
718 #undef OPTION_HW_WRITE_LEV_TRAINING
719 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
720 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
721 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
722 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
723 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
724 #undef OPTION_MAX_RD_LAT_TRAINING
725 #define OPTION_MAX_RD_LAT_TRAINING TRUE
726 #undef OPTION_SW_DRAM_INIT
727 #define OPTION_SW_DRAM_INIT TRUE
728 #undef OPTION_S3_MEM_SUPPORT
729 #define OPTION_S3_MEM_SUPPORT TRUE
730 #undef OPTION_CPU_CORELEVLING
731 #define OPTION_CPU_CORELEVLING TRUE
732 #undef OPTION_CPU_CFOH
733 #define OPTION_CPU_CFOH TRUE
734 #undef OPTION_UDIMMS
735 #define OPTION_UDIMMS TRUE
736 #undef OPTION_SODIMMS
737 #define OPTION_SODIMMS TRUE
738 #undef OPTION_DDR3
739 #define OPTION_DDR3 TRUE
740 #undef OPTION_ECC
741 #define OPTION_ECC TRUE
742 #undef OPTION_BANK_INTERLEAVE
743 #define OPTION_BANK_INTERLEAVE TRUE
744 #undef OPTION_DCT_INTERLEAVE
745 #define OPTION_DCT_INTERLEAVE TRUE
746 #undef OPTION_NODE_INTERLEAVE
747 #define OPTION_NODE_INTERLEAVE TRUE
748 #undef OPTION_PARALLEL_TRAINING
749 #define OPTION_PARALLEL_TRAINING TRUE
750 #undef OPTION_MEM_RESTORE
751 #define OPTION_MEM_RESTORE TRUE
752 #undef OPTION_ONLINE_SPARE
753 #define OPTION_ONLINE_SPARE TRUE
754 #undef OPTION_DIMM_EXCLUDE
755 #define OPTION_DIMM_EXCLUDE TRUE
756 #endif
757#endif
758
759#if (OPTION_S1G4_SOCKET_SUPPORT == TRUE)
760 #if (OPTION_FAMILY10H == TRUE)
761 #undef OPTION_FAMILY10H_BL
762 #define OPTION_FAMILY10H_BL TRUE
763 #undef OPTION_FAMILY10H_DA
764 #define OPTION_FAMILY10H_DA TRUE
765 #undef OPTION_MEMCTLR_DA
766 #define OPTION_MEMCTLR_DA TRUE
767 #undef OPTION_HW_WRITE_LEV_TRAINING
768 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
769 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
770 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
771 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
772 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
773 #undef OPTION_MAX_RD_LAT_TRAINING
774 #define OPTION_MAX_RD_LAT_TRAINING TRUE
775 #undef OPTION_SW_DRAM_INIT
776 #define OPTION_SW_DRAM_INIT TRUE
777 #undef OPTION_S3_MEM_SUPPORT
778 #define OPTION_S3_MEM_SUPPORT TRUE
779 #undef OPTION_CPU_CORELEVLING
780 #define OPTION_CPU_CORELEVLING TRUE
781 #undef OPTION_CPU_CFOH
782 #define OPTION_CPU_CFOH TRUE
783 #undef OPTION_UDIMMS
784 #define OPTION_UDIMMS TRUE
785 #undef OPTION_SODIMMS
786 #define OPTION_SODIMMS TRUE
787 #undef OPTION_DDR3
788 #define OPTION_DDR3 TRUE
789 #undef OPTION_ECC
790 #define OPTION_ECC TRUE
791 #undef OPTION_BANK_INTERLEAVE
792 #define OPTION_BANK_INTERLEAVE TRUE
793 #undef OPTION_DCT_INTERLEAVE
794 #define OPTION_DCT_INTERLEAVE TRUE
795 #undef OPTION_NODE_INTERLEAVE
796 #define OPTION_NODE_INTERLEAVE TRUE
797 #undef OPTION_MEM_RESTORE
798 #define OPTION_MEM_RESTORE TRUE
799 #undef OPTION_DIMM_EXCLUDE
800 #define OPTION_DIMM_EXCLUDE TRUE
801 #endif
802#endif
803
804#if (OPTION_ASB2_SOCKET_SUPPORT == TRUE)
805 #if (OPTION_FAMILY10H == TRUE)
806 #undef OPTION_FAMILY10H_BL
807 #define OPTION_FAMILY10H_BL TRUE
808 #undef OPTION_FAMILY10H_DA
809 #define OPTION_FAMILY10H_DA TRUE
810 #undef OPTION_MEMCTLR_Ni
811 #define OPTION_MEMCTLR_Ni TRUE
812 #undef OPTION_HW_WRITE_LEV_TRAINING
813 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
814 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
815 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
816 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
817 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
818 #undef OPTION_MAX_RD_LAT_TRAINING
819 #define OPTION_MAX_RD_LAT_TRAINING TRUE
820 #undef OPTION_SW_DRAM_INIT
821 #define OPTION_SW_DRAM_INIT TRUE
822 #undef OPTION_S3_MEM_SUPPORT
823 #define OPTION_S3_MEM_SUPPORT TRUE
824 #undef OPTION_CPU_CORELEVLING
825 #define OPTION_CPU_CORELEVLING TRUE
826 #undef OPTION_CPU_CFOH
827 #define OPTION_CPU_CFOH TRUE
828 #undef OPTION_UDIMMS
829 #define OPTION_UDIMMS TRUE
830 #undef OPTION_SODIMMS
831 #define OPTION_SODIMMS TRUE
832 #undef OPTION_DDR3
833 #define OPTION_DDR3 TRUE
834 #undef OPTION_ECC
835 #define OPTION_ECC TRUE
836 #undef OPTION_BANK_INTERLEAVE
837 #define OPTION_BANK_INTERLEAVE TRUE
838 #undef OPTION_DCT_INTERLEAVE
839 #define OPTION_DCT_INTERLEAVE TRUE
840 #undef OPTION_NODE_INTERLEAVE
841 #define OPTION_NODE_INTERLEAVE TRUE
842 #undef OPTION_MEM_RESTORE
843 #define OPTION_MEM_RESTORE TRUE
844 #undef OPTION_DIMM_EXCLUDE
845 #define OPTION_DIMM_EXCLUDE TRUE
846 #endif
847#endif
848
849#if (OPTION_FS1_SOCKET_SUPPORT == TRUE)
850 #if (OPTION_FAMILY12H == TRUE)
851 #undef OPTION_FAMILY12H_LN
852 #define OPTION_FAMILY12H_LN TRUE
853 #undef OPTION_MEMCTLR_LN
854 #define OPTION_MEMCTLR_LN TRUE
855 #undef OPTION_HW_WRITE_LEV_TRAINING
856 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
857 #undef OPTION_CONTINOUS_PATTERN_GENERATION
858 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
859 #undef OPTION_HW_DQS_REC_EN_TRAINING
860 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
861 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
862 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
863 #undef OPTION_MAX_RD_LAT_TRAINING
864 #define OPTION_MAX_RD_LAT_TRAINING TRUE
865 #undef OPTION_SW_DRAM_INIT
866 #define OPTION_SW_DRAM_INIT TRUE
867 #undef OPTION_S3_MEM_SUPPORT
868 #define OPTION_S3_MEM_SUPPORT TRUE
869 #undef OPTION_GFX_RECOVERY
870 #define OPTION_GFX_RECOVERY TRUE
871 #undef OPTION_C6_STATE
872 #define OPTION_C6_STATE TRUE
873 #undef OPTION_IO_CSTATE
874 #define OPTION_IO_CSTATE TRUE
875 #undef OPTION_CPB
876 #define OPTION_CPB TRUE
877 #undef OPTION_S3SCRIPT
878 #define OPTION_S3SCRIPT TRUE
879 #undef OPTION_UDIMMS
880 #define OPTION_UDIMMS TRUE
881 #undef OPTION_SODIMMS
882 #define OPTION_SODIMMS TRUE
883 #undef OPTION_DDR3
884 #define OPTION_DDR3 TRUE
885 #undef OPTION_BANK_INTERLEAVE
886 #define OPTION_BANK_INTERLEAVE TRUE
887 #undef OPTION_DCT_INTERLEAVE
888 #define OPTION_DCT_INTERLEAVE TRUE
889 #undef OPTION_MEM_RESTORE
890 #define OPTION_MEM_RESTORE TRUE
891 #undef OPTION_DIMM_EXCLUDE
892 #define OPTION_DIMM_EXCLUDE TRUE
893 #endif
894#endif
895
896#if (OPTION_FM1_SOCKET_SUPPORT == TRUE)
897 #if (OPTION_FAMILY12H == TRUE)
898 #undef OPTION_FAMILY12H_LN
899 #define OPTION_FAMILY12H_LN TRUE
900 #undef OPTION_MEMCTLR_LN
901 #define OPTION_MEMCTLR_LN TRUE
902 #undef OPTION_HW_WRITE_LEV_TRAINING
903 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
904 #undef OPTION_CONTINOUS_PATTERN_GENERATION
905 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
906 #undef OPTION_HW_DQS_REC_EN_TRAINING
907 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
908 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
909 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
910 #undef OPTION_MAX_RD_LAT_TRAINING
911 #define OPTION_MAX_RD_LAT_TRAINING TRUE
912 #undef OPTION_SW_DRAM_INIT
913 #define OPTION_SW_DRAM_INIT TRUE
914 #undef OPTION_S3_MEM_SUPPORT
915 #define OPTION_S3_MEM_SUPPORT TRUE
916 #undef OPTION_GFX_RECOVERY
917 #define OPTION_GFX_RECOVERY TRUE
918 #undef OPTION_C6_STATE
919 #define OPTION_C6_STATE TRUE
920 #undef OPTION_IO_CSTATE
921 #define OPTION_IO_CSTATE TRUE
922 #undef OPTION_CPB
923 #define OPTION_CPB TRUE
924 #undef OPTION_S3SCRIPT
925 #define OPTION_S3SCRIPT TRUE
926 #undef OPTION_UDIMMS
927 #define OPTION_UDIMMS TRUE
928 #undef OPTION_SODIMMS
929 #define OPTION_SODIMMS TRUE
930 #undef OPTION_DDR3
931 #define OPTION_DDR3 TRUE
932 #undef OPTION_BANK_INTERLEAVE
933 #define OPTION_BANK_INTERLEAVE TRUE
934 #undef OPTION_DCT_INTERLEAVE
935 #define OPTION_DCT_INTERLEAVE TRUE
936 #undef OPTION_MEM_RESTORE
937 #define OPTION_MEM_RESTORE TRUE
938 #undef OPTION_DIMM_EXCLUDE
939 #define OPTION_DIMM_EXCLUDE TRUE
940 #endif
941#endif
942
943#if (OPTION_FP1_SOCKET_SUPPORT == TRUE)
944 #if (OPTION_FAMILY12H == TRUE)
945 #undef OPTION_FAMILY12H_LN
946 #define OPTION_FAMILY12H_LN TRUE
947 #undef OPTION_MEMCTLR_LN
948 #define OPTION_MEMCTLR_LN TRUE
949 #undef OPTION_HW_WRITE_LEV_TRAINING
950 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
951 #undef OPTION_CONTINOUS_PATTERN_GENERATION
952 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
953 #undef OPTION_HW_DQS_REC_EN_TRAINING
954 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
955 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
956 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
957 #undef OPTION_MAX_RD_LAT_TRAINING
958 #define OPTION_MAX_RD_LAT_TRAINING TRUE
959 #undef OPTION_SW_DRAM_INIT
960 #define OPTION_SW_DRAM_INIT TRUE
961 #undef OPTION_S3_MEM_SUPPORT
962 #define OPTION_S3_MEM_SUPPORT TRUE
963 #undef OPTION_ADDR_TO_CS_TRANSLATOR
964 #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE
965 #undef OPTION_GFX_RECOVERY
966 #define OPTION_GFX_RECOVERY TRUE
967 #undef OPTION_C6_STATE
968 #define OPTION_C6_STATE TRUE
969 #undef OPTION_IO_CSTATE
970 #define OPTION_IO_CSTATE TRUE
971 #undef OPTION_CPB
972 #define OPTION_CPB TRUE
973 #undef OPTION_S3SCRIPT
974 #define OPTION_S3SCRIPT TRUE
975 #undef OPTION_UDIMMS
976 #define OPTION_UDIMMS TRUE
977 #undef OPTION_SODIMMS
978 #define OPTION_SODIMMS TRUE
979 #undef OPTION_DDR3
980 #define OPTION_DDR3 TRUE
981 #undef OPTION_BANK_INTERLEAVE
982 #define OPTION_BANK_INTERLEAVE TRUE
983 #undef OPTION_DCT_INTERLEAVE
984 #define OPTION_DCT_INTERLEAVE TRUE
985 #undef OPTION_MEM_RESTORE
986 #define OPTION_MEM_RESTORE TRUE
987 #undef OPTION_ONLINE_SPARE
988 #define OPTION_ONLINE_SPARE TRUE
989 #undef OPTION_DIMM_EXCLUDE
990 #define OPTION_DIMM_EXCLUDE TRUE
991 #endif
992#endif
993
994#if (OPTION_FT1_SOCKET_SUPPORT == TRUE)
995 #if (OPTION_FAMILY14H == TRUE)
996 #undef OPTION_FAMILY14H_ON
997 #define OPTION_FAMILY14H_ON TRUE
998 #undef OPTION_MEMCTLR_ON
999 #define OPTION_MEMCTLR_ON TRUE
1000 #undef OPTION_HW_WRITE_LEV_TRAINING
1001 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
1002 #undef OPTION_CONTINOUS_PATTERN_GENERATION
1003 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
1004 #undef OPTION_MAX_RD_LAT_TRAINING
1005 #define OPTION_MAX_RD_LAT_TRAINING TRUE
1006 #undef OPTION_HW_DQS_REC_EN_TRAINING
1007 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
1008 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
1009 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
1010 #undef OPTION_SW_DRAM_INIT
1011 #define OPTION_SW_DRAM_INIT TRUE
1012 #undef OPTION_S3_MEM_SUPPORT
1013 #define OPTION_S3_MEM_SUPPORT TRUE
1014 #undef OPTION_GFX_RECOVERY
1015 #define OPTION_GFX_RECOVERY TRUE
1016 #undef OPTION_C6_STATE
1017 #define OPTION_C6_STATE TRUE
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]1018 #undef OPTION_CPB
1019 #define OPTION_CPB TRUE
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1020 #undef OPTION_IO_CSTATE
1021 #define OPTION_IO_CSTATE TRUE
1022 #undef OPTION_S3SCRIPT
1023 #define OPTION_S3SCRIPT TRUE
1024 #undef OPTION_UDIMMS
1025 #define OPTION_UDIMMS TRUE
1026 #undef OPTION_SODIMMS
1027 #define OPTION_SODIMMS TRUE
1028 #undef OPTION_DDR3
1029 #define OPTION_DDR3 TRUE
1030 #undef OPTION_BANK_INTERLEAVE
1031 #define OPTION_BANK_INTERLEAVE TRUE
1032 #undef OPTION_MEM_RESTORE
1033 #define OPTION_MEM_RESTORE TRUE
1034 #undef OPTION_DIMM_EXCLUDE
1035 #define OPTION_DIMM_EXCLUDE TRUE
1036 #endif
1037#endif
1038
1039#if (OPTION_AM3_SOCKET_SUPPORT == TRUE)
1040 #if (OPTION_FAMILY10H == TRUE)
1041 #undef OPTION_FAMILY10H_BL
1042 #define OPTION_FAMILY10H_BL TRUE
1043 #undef OPTION_FAMILY10H_DA
1044 #define OPTION_FAMILY10H_DA TRUE
1045 #undef OPTION_FAMILY10H_PH
1046 #define OPTION_FAMILY10H_PH TRUE
1047 #undef OPTION_FAMILY10H_RB
1048 #define OPTION_FAMILY10H_RB TRUE
1049 #undef OPTION_MEMCTLR_RB
1050 #define OPTION_MEMCTLR_RB TRUE
1051 #undef OPTION_MEMCTLR_DA
1052 #define OPTION_MEMCTLR_DA TRUE
1053 #undef OPTION_MEMCTLR_PH
1054 #define OPTION_MEMCTLR_PH TRUE
1055 #undef OPTION_HW_WRITE_LEV_TRAINING
1056 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
1057 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
1058 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
1059 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
1060 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
1061 #undef OPTION_MAX_RD_LAT_TRAINING
1062 #define OPTION_MAX_RD_LAT_TRAINING TRUE
1063 #undef OPTION_SW_DRAM_INIT
1064 #define OPTION_SW_DRAM_INIT TRUE
1065 #undef OPTION_S3_MEM_SUPPORT
1066 #define OPTION_S3_MEM_SUPPORT TRUE
1067 #undef OPTION_CPU_CORELEVLING
1068 #define OPTION_CPU_CORELEVLING TRUE
1069 #undef OPTION_CPU_CFOH
1070 #define OPTION_CPU_CFOH TRUE
1071 #undef OPTION_IO_CSTATE
1072 #define OPTION_IO_CSTATE TRUE
1073 #undef OPTION_CPB
1074 #define OPTION_CPB TRUE
1075 #undef OPTION_UDIMMS
1076 #define OPTION_UDIMMS TRUE
1077 #undef OPTION_SODIMMS
1078 #define OPTION_SODIMMS TRUE
1079 #undef OPTION_DDR3
1080 #define OPTION_DDR3 TRUE
1081 #undef OPTION_ECC
1082 #define OPTION_ECC TRUE
1083 #undef OPTION_BANK_INTERLEAVE
1084 #define OPTION_BANK_INTERLEAVE TRUE
1085 #undef OPTION_DCT_INTERLEAVE
1086 #define OPTION_DCT_INTERLEAVE TRUE
1087 #undef OPTION_NODE_INTERLEAVE
1088 #define OPTION_NODE_INTERLEAVE TRUE
1089 #undef OPTION_PARALLEL_TRAINING
1090 #define OPTION_PARALLEL_TRAINING TRUE
1091 #undef OPTION_MEM_RESTORE
1092 #define OPTION_MEM_RESTORE TRUE
1093 #undef OPTION_ONLINE_SPARE
1094 #define OPTION_ONLINE_SPARE TRUE
1095 #undef OPTION_DIMM_EXCLUDE
1096 #define OPTION_DIMM_EXCLUDE TRUE
1097 #endif
1098 #if (OPTION_FAMILY15H == TRUE)
1099 #undef OPTION_FAMILY15H_OR
1100 #define OPTION_FAMILY15H_OR TRUE
1101 #undef OPTION_MEMCTLR_OR
1102 #define OPTION_MEMCTLR_OR TRUE
1103 #undef OPTION_HW_WRITE_LEV_TRAINING
1104 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
1105 #undef OPTION_CONTINOUS_PATTERN_GENERATION
1106 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
1107 #undef OPTION_HW_DQS_REC_EN_TRAINING
1108 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
1109 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
1110 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
1111 #undef OPTION_MAX_RD_LAT_TRAINING
1112 #define OPTION_MAX_RD_LAT_TRAINING TRUE
1113 #undef OPTION_SW_DRAM_INIT
1114 #define OPTION_SW_DRAM_INIT TRUE
1115 #undef OPTION_C6_STATE
1116 #define OPTION_C6_STATE TRUE
1117 #undef OPTION_IO_CSTATE
1118 #define OPTION_IO_CSTATE TRUE
1119 #undef OPTION_CPB
1120 #define OPTION_CPB TRUE
1121 #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
1122 #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE
1123 #undef OPTION_S3_MEM_SUPPORT
1124 #define OPTION_S3_MEM_SUPPORT TRUE
1125 #undef OPTION_ADDR_TO_CS_TRANSLATOR
1126 #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE
1127 #undef OPTION_CPU_CORELEVLING
1128 #define OPTION_CPU_CORELEVLING TRUE
1129 #undef OPTION_CPU_CFOH
1130 #define OPTION_CPU_CFOH TRUE
1131 #undef OPTION_MSG_BASED_C1E
1132 #define OPTION_MSG_BASED_C1E TRUE
1133 #undef OPTION_UDIMMS
1134 #define OPTION_UDIMMS TRUE
1135 #undef OPTION_RDIMMS
1136 #define OPTION_RDIMMS TRUE
1137 #undef OPTION_LRDIMMS
1138 #define OPTION_LRDIMMS TRUE
1139 #undef OPTION_SODIMMS
1140 #define OPTION_SODIMMS TRUE
1141 #undef OPTION_DDR3
1142 #define OPTION_DDR3 TRUE
1143 #undef OPTION_ECC
1144 #define OPTION_ECC TRUE
1145 #undef OPTION_BANK_INTERLEAVE
1146 #define OPTION_BANK_INTERLEAVE TRUE
1147 #undef OPTION_DCT_INTERLEAVE
1148 #define OPTION_DCT_INTERLEAVE TRUE
1149 #undef OPTION_NODE_INTERLEAVE
1150 #define OPTION_NODE_INTERLEAVE TRUE
1151 #undef OPTION_MEM_RESTORE
1152 #define OPTION_MEM_RESTORE TRUE
1153 #undef OPTION_ONLINE_SPARE
1154 #define OPTION_ONLINE_SPARE TRUE
1155 #undef OPTION_DIMM_EXCLUDE
1156 #define OPTION_DIMM_EXCLUDE TRUE
1157 #endif
1158#endif
1159
1160#if (OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE)
1161 #undef GNB_SUPPORT
1162 #define GNB_SUPPORT TRUE
1163#endif
1164
1165#define OPTION_ACPI_PSTATES TRUE
1166#define OPTION_WHEA TRUE
1167#define OPTION_DMI TRUE
1168#define OPTION_EARLY_SAMPLES FALSE
1169#define CFG_ACPI_PSTATES_PPC TRUE
1170#define CFG_ACPI_PSTATES_PCT TRUE
1171#define CFG_ACPI_PSTATES_PSD TRUE
1172#define CFG_ACPI_PSTATES_PSS TRUE
1173#define CFG_ACPI_PSTATES_XPSS TRUE
1174#define CFG_ACPI_PSTATE_PSD_INDPX FALSE
1175#define CFG_VRM_HIGH_SPEED_ENABLE FALSE
1176#define CFG_VRM_NB_HIGH_SPEED_ENABLE FALSE
1177#define OPTION_ALIB TRUE
1178/*---------------------------------------------------------------------------
1179 * Processing the options: Second, process the user's selections
1180 *--------------------------------------------------------------------------*/
1181#ifdef BLDOPT_REMOVE_MULTISOCKET_SUPPORT
1182 #if BLDOPT_REMOVE_MULTISOCKET_SUPPORT == TRUE
1183 #undef OPTION_MULTISOCKET
1184 #define OPTION_MULTISOCKET FALSE
1185 #endif
1186#endif
1187#ifdef BLDOPT_REMOVE_ECC_SUPPORT
1188 #if BLDOPT_REMOVE_ECC_SUPPORT == TRUE
1189 #undef OPTION_ECC
1190 #define OPTION_ECC FALSE
1191 #endif
1192#endif
1193#ifdef BLDOPT_REMOVE_UDIMMS_SUPPORT
1194 #if BLDOPT_REMOVE_UDIMMS_SUPPORT == TRUE
1195 #undef OPTION_UDIMMS
1196 #define OPTION_UDIMMS FALSE
1197 #endif
1198#endif
1199#ifdef BLDOPT_REMOVE_RDIMMS_SUPPORT
1200 #if BLDOPT_REMOVE_RDIMMS_SUPPORT == TRUE
1201 #undef OPTION_RDIMMS
1202 #define OPTION_RDIMMS FALSE
1203 #endif
1204#endif
1205#ifdef BLDOPT_REMOVE_SODIMMS_SUPPORT
1206 #if BLDOPT_REMOVE_SODIMMS_SUPPORT == TRUE
1207 #undef OPTION_SODIMMS
1208 #define OPTION_SODIMMS FALSE
1209 #endif
1210#endif
1211#ifdef BLDOPT_REMOVE_LRDIMMS_SUPPORT
1212 #if BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE
1213 #undef OPTION_LRDIMMS
1214 #define OPTION_LRDIMMS FALSE
1215 #endif
1216#endif
1217#ifdef BLDOPT_REMOVE_BANK_INTERLEAVE
1218 #if BLDOPT_REMOVE_BANK_INTERLEAVE == TRUE
1219 #undef OPTION_BANK_INTERLEAVE
1220 #define OPTION_BANK_INTERLEAVE FALSE
1221 #endif
1222#endif
1223#ifdef BLDOPT_REMOVE_DCT_INTERLEAVE
1224 #if BLDOPT_REMOVE_DCT_INTERLEAVE == TRUE
1225 #undef OPTION_DCT_INTERLEAVE
1226 #define OPTION_DCT_INTERLEAVE FALSE
1227 #endif
1228#endif
1229#ifdef BLDOPT_REMOVE_NODE_INTERLEAVE
1230 #if BLDOPT_REMOVE_NODE_INTERLEAVE == TRUE
1231 #undef OPTION_NODE_INTERLEAVE
1232 #define OPTION_NODE_INTERLEAVE FALSE
1233 #endif
1234#endif
1235#ifdef BLDOPT_REMOVE_PARALLEL_TRAINING
1236 #if BLDOPT_REMOVE_PARALLEL_TRAINING == TRUE
1237 #undef OPTION_PARALLEL_TRAINING
1238 #define OPTION_PARALLEL_TRAINING FALSE
1239 #endif
1240#endif
1241#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
1242 #if BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE
1243 #undef OPTION_ONLINE_SPARE
1244 #define OPTION_ONLINE_SPARE FALSE
1245 #endif
1246#endif
1247#ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
1248 #if BLDOPT_REMOVE_MEM_RESTORE_SUPPORT == TRUE
1249 #undef OPTION_MEM_RESTORE
1250 #define OPTION_MEM_RESTORE FALSE
1251 #endif
1252#endif
1253#ifdef BLDOPT_REMOVE_ACPI_PSTATES
1254 #if BLDOPT_REMOVE_ACPI_PSTATES == TRUE
1255 #undef OPTION_ACPI_PSTATES
1256 #define OPTION_ACPI_PSTATES FALSE
1257 #endif
1258#endif
1259#ifdef BLDOPT_REMOVE_SRAT
1260 #if BLDOPT_REMOVE_SRAT == TRUE
1261 #undef OPTION_SRAT
1262 #define OPTION_SRAT FALSE
1263 #endif
1264#endif
1265#ifdef BLDOPT_REMOVE_SLIT
1266 #if BLDOPT_REMOVE_SLIT == TRUE
1267 #undef OPTION_SLIT
1268 #define OPTION_SLIT FALSE
1269 #endif
1270#endif
1271#ifdef BLDOPT_REMOVE_WHEA
1272 #if BLDOPT_REMOVE_WHEA == TRUE
1273 #undef OPTION_WHEA
1274 #define OPTION_WHEA FALSE
1275 #endif
1276#endif
1277#ifdef BLDOPT_REMOVE_DMI
1278 #if BLDOPT_REMOVE_DMI == TRUE
1279 #undef OPTION_DMI
1280 #define OPTION_DMI FALSE
1281 #endif
1282#endif
1283#ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR
1284 #if BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR == TRUE
1285 #undef OPTION_ADDR_TO_CS_TRANSLATOR
1286 #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
1287 #endif
1288#endif
1289
1290#ifdef BLDOPT_REMOVE_HT_ASSIST
1291 #if BLDOPT_REMOVE_HT_ASSIST == TRUE
1292 #undef OPTION_HT_ASSIST
1293 #define OPTION_HT_ASSIST FALSE
1294 #endif
1295#endif
1296
1297#ifdef BLDOPT_REMOVE_ATM_MODE
1298 #if BLDOPT_REMOVE_ATM_MODE == TRUE
1299 #undef OPTION_ATM_MODE
1300 #define OPTION_ATM_MODE FALSE
1301 #endif
1302#endif
1303
1304#ifdef BLDOPT_REMOVE_MSG_BASED_C1E
1305 #if BLDOPT_REMOVE_MSG_BASED_C1E == TRUE
1306 #undef OPTION_MSG_BASED_C1E
1307 #define OPTION_MSG_BASED_C1E FALSE
1308 #endif
1309#endif
1310
1311#ifdef BLDOPT_REMOVE_C6_STATE
1312 #if BLDOPT_REMOVE_C6_STATE == TRUE
1313 #undef OPTION_C6_STATE
1314 #define OPTION_C6_STATE FALSE
1315 #endif
1316#endif
1317
1318#ifdef BLDOPT_REMOVE_GFX_RECOVERY
1319 #if BLDOPT_REMOVE_GFX_RECOVERY == TRUE
1320 #undef OPTION_GFX_RECOVERY
1321 #define OPTION_GFX_RECOVERY FALSE
1322 #endif
1323#endif
1324
1325#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PPC
1326 #if BLDCFG_REMOVE_ACPI_PSTATES_PPC == TRUE
1327 #undef CFG_ACPI_PSTATES_PPC
1328 #define CFG_ACPI_PSTATES_PPC FALSE
1329 #endif
1330#endif
1331
1332#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PCT
1333 #if BLDCFG_REMOVE_ACPI_PSTATES_PCT == TRUE
1334 #undef CFG_ACPI_PSTATES_PCT
1335 #define CFG_ACPI_PSTATES_PCT FALSE
1336 #endif
1337#endif
1338
1339#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSD
1340 #if BLDCFG_REMOVE_ACPI_PSTATES_PSD == TRUE
1341 #undef CFG_ACPI_PSTATES_PSD
1342 #define CFG_ACPI_PSTATES_PSD FALSE
1343 #endif
1344#endif
1345
1346#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSS
1347 #if BLDCFG_REMOVE_ACPI_PSTATES_PSS == TRUE
1348 #undef CFG_ACPI_PSTATES_PSS
1349 #define CFG_ACPI_PSTATES_PSS FALSE
1350 #endif
1351#endif
1352
1353#ifdef BLDCFG_REMOVE_ACPI_PSTATES_XPSS
1354 #if BLDCFG_REMOVE_ACPI_PSTATES_XPSS == TRUE
1355 #undef CFG_ACPI_PSTATES_XPSS
1356 #define CFG_ACPI_PSTATES_XPSS FALSE
1357 #endif
1358#endif
1359
1360#ifdef BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT
1361 #if BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT == TRUE
1362 #undef CFG_ACPI_PSTATE_PSD_INDPX
1363 #define CFG_ACPI_PSTATE_PSD_INDPX TRUE
1364 #endif
1365#endif
1366
1367#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE
1368 #if BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE
1369 #undef CFG_VRM_HIGH_SPEED_ENABLE
1370 #define CFG_VRM_HIGH_SPEED_ENABLE TRUE
1371 #endif
1372#endif
1373
1374#ifdef BLDCFG_VRM_NB_HIGH_SPEED_ENABLE
1375 #if BLDCFG_VRM_NB_HIGH_SPEED_ENABLE == TRUE
1376 #undef CFG_VRM_NB_HIGH_SPEED_ENABLE
1377 #define CFG_VRM_NB_HIGH_SPEED_ENABLE TRUE
1378 #endif
1379#endif
1380
1381#ifdef BLDCFG_STARTING_BUSNUM
1382 #define CFG_STARTING_BUSNUM (BLDCFG_STARTING_BUSNUM)
1383#else
1384 #define CFG_STARTING_BUSNUM (0)
1385#endif
1386
1387#ifdef BLDCFG_AMD_PLATFORM_TYPE
1388 #define CFG_AMD_PLATFORM_TYPE BLDCFG_AMD_PLATFORM_TYPE
1389#else
1390 #define CFG_AMD_PLATFORM_TYPE 0
1391#endif
1392
1393CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
1394
1395#ifdef BLDCFG_MAXIMUM_BUSNUM
1396 #define CFG_MAXIMUM_BUSNUM (BLDCFG_MAXIMUM_BUSNUM)
1397#else
1398 #define CFG_MAXIMUM_BUSNUM (0xF8)
1399#endif
1400
1401#ifdef BLDCFG_ALLOCATED_BUSNUM
1402 #define CFG_ALLOCATED_BUSNUM (BLDCFG_ALLOCATED_BUSNUM)
1403#else
1404 #define CFG_ALLOCATED_BUSNUM (0x20)
1405#endif
1406
1407#ifdef BLDCFG_BUID_SWAP_LIST
1408 #define CFG_BUID_SWAP_LIST (BLDCFG_BUID_SWAP_LIST)
1409#else
1410 #define CFG_BUID_SWAP_LIST (NULL)
1411#endif
1412
1413#ifdef BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST
1414 #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST)
1415#else
1416 #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (NULL)
1417#endif
1418
1419#ifdef BLDCFG_HTFABRIC_LIMITS_LIST
1420 #define CFG_HTFABRIC_LIMITS_LIST (BLDCFG_HTFABRIC_LIMITS_LIST)
1421#else
1422 #define CFG_HTFABRIC_LIMITS_LIST (NULL)
1423#endif
1424
1425#ifdef BLDCFG_HTCHAIN_LIMITS_LIST
1426 #define CFG_HTCHAIN_LIMITS_LIST (BLDCFG_HTCHAIN_LIMITS_LIST)
1427#else
1428 #define CFG_HTCHAIN_LIMITS_LIST (NULL)
1429#endif
1430
1431#ifdef BLDCFG_BUS_NUMBERS_LIST
1432 #define CFG_BUS_NUMBERS_LIST (BLDCFG_BUS_NUMBERS_LIST)
1433#else
1434 #define CFG_BUS_NUMBERS_LIST (NULL)
1435#endif
1436
1437#ifdef BLDCFG_IGNORE_LINK_LIST
1438 #define CFG_IGNORE_LINK_LIST (BLDCFG_IGNORE_LINK_LIST)
1439#else
1440 #define CFG_IGNORE_LINK_LIST (NULL)
1441#endif
1442
1443#ifdef BLDCFG_LINK_SKIP_REGANG_LIST
1444 #define CFG_LINK_SKIP_REGANG_LIST (BLDCFG_LINK_SKIP_REGANG_LIST)
1445#else
1446 #define CFG_LINK_SKIP_REGANG_LIST (NULL)
1447#endif
1448
1449#ifdef BLDCFG_SET_HTCRC_SYNC_FLOOD
1450 #define CFG_SET_HTCRC_SYNC_FLOOD (BLDCFG_SET_HTCRC_SYNC_FLOOD)
1451#else
1452 #define CFG_SET_HTCRC_SYNC_FLOOD (FALSE)
1453#endif
1454
1455#ifdef BLDCFG_USE_UNIT_ID_CLUMPING
1456 #define CFG_USE_UNIT_ID_CLUMPING (BLDCFG_USE_UNIT_ID_CLUMPING)
1457#else
1458 #define CFG_USE_UNIT_ID_CLUMPING (FALSE)
1459#endif
1460
1461#ifdef BLDCFG_ADDITIONAL_TOPOLOGIES_LIST
1462 #define CFG_ADDITIONAL_TOPOLOGIES_LIST (BLDCFG_ADDITIONAL_TOPOLOGIES_LIST)
1463#else
1464 #define CFG_ADDITIONAL_TOPOLOGIES_LIST (NULL)
1465#endif
1466
1467#ifdef BLDCFG_USE_HT_ASSIST
1468 #define CFG_USE_HT_ASSIST (BLDCFG_USE_HT_ASSIST)
1469#else
1470 #define CFG_USE_HT_ASSIST (TRUE)
1471#endif
1472
1473#ifdef BLDCFG_USE_ATM_MODE
1474 #define CFG_USE_ATM_MODE (BLDCFG_USE_ATM_MODE)
1475#else
1476 #define CFG_USE_ATM_MODE (TRUE)
1477#endif
1478
1479#ifdef BLDCFG_PLATFORM_CONTROL_FLOW_MODE
1480 #define CFG_PLATFORM_CONTROL_FLOW_MODE (BLDCFG_PLATFORM_CONTROL_FLOW_MODE)
1481#else
1482 #define CFG_PLATFORM_CONTROL_FLOW_MODE (Nfcm)
1483#endif
1484
1485#ifdef BLDCFG_PLATFORM_DEEMPHASIS_LIST
1486 #define CFG_PLATFORM_DEEMPHASIS_LIST (BLDCFG_PLATFORM_DEEMPHASIS_LIST)
1487#else
1488 #define CFG_PLATFORM_DEEMPHASIS_LIST (NULL)
1489#endif
1490
1491#ifdef BLDCFG_VRM_ADDITIONAL_DELAY
1492 #define CFG_VRM_ADDITIONAL_DELAY (BLDCFG_VRM_ADDITIONAL_DELAY)
1493#else
1494 #define CFG_VRM_ADDITIONAL_DELAY (0)
1495#endif
1496
1497#ifdef BLDCFG_VRM_CURRENT_LIMIT
1498 #define CFG_VRM_CURRENT_LIMIT BLDCFG_VRM_CURRENT_LIMIT
1499#else
1500 #define CFG_VRM_CURRENT_LIMIT 0
1501#endif
1502
1503#ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD
1504 #define CFG_VRM_LOW_POWER_THRESHOLD BLDCFG_VRM_LOW_POWER_THRESHOLD
1505#else
1506 #define CFG_VRM_LOW_POWER_THRESHOLD 0
1507#endif
1508
1509#ifdef BLDCFG_VRM_SLEW_RATE
1510 #define CFG_VRM_SLEW_RATE BLDCFG_VRM_SLEW_RATE
1511#else
1512 #define CFG_VRM_SLEW_RATE DFLT_VRM_SLEW_RATE
1513#endif
1514
1515#ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT
1516 #define CFG_VRM_INRUSH_CURRENT_LIMIT BLDCFG_VRM_INRUSH_CURRENT_LIMIT
1517#else
1518 #define CFG_VRM_INRUSH_CURRENT_LIMIT 0
1519#endif
1520
1521#ifdef BLDCFG_VRM_NB_ADDITIONAL_DELAY
1522 #define CFG_VRM_NB_ADDITIONAL_DELAY (BLDCFG_VRM_NB_ADDITIONAL_DELAY)
1523#else
1524 #define CFG_VRM_NB_ADDITIONAL_DELAY (0)
1525#endif
1526
1527#ifdef BLDCFG_VRM_NB_CURRENT_LIMIT
1528 #define CFG_VRM_NB_CURRENT_LIMIT BLDCFG_VRM_NB_CURRENT_LIMIT
1529#else
1530 #define CFG_VRM_NB_CURRENT_LIMIT (0)
1531#endif
1532
1533#ifdef BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
1534 #define CFG_VRM_NB_LOW_POWER_THRESHOLD BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
1535#else
1536 #define CFG_VRM_NB_LOW_POWER_THRESHOLD (0)
1537#endif
1538
1539#ifdef BLDCFG_VRM_NB_SLEW_RATE
1540 #define CFG_VRM_NB_SLEW_RATE BLDCFG_VRM_NB_SLEW_RATE
1541#else
1542 #define CFG_VRM_NB_SLEW_RATE DFLT_VRM_SLEW_RATE
1543#endif
1544
1545#ifdef BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT
1546 #define CFG_VRM_NB_INRUSH_CURRENT_LIMIT BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT
1547#else
1548 #define CFG_VRM_NB_INRUSH_CURRENT_LIMIT (0)
1549#endif
1550
1551
1552#ifdef BLDCFG_PLAT_NUM_IO_APICS
1553 #define CFG_PLAT_NUM_IO_APICS BLDCFG_PLAT_NUM_IO_APICS
1554#else
1555 #define CFG_PLAT_NUM_IO_APICS 0
1556#endif
1557
1558#ifdef BLDCFG_MEM_INIT_PSTATE
1559 #define CFG_MEM_INIT_PSTATE BLDCFG_MEM_INIT_PSTATE
1560#else
1561 #define CFG_MEM_INIT_PSTATE 0
1562#endif
1563
1564#ifdef BLDCFG_PLATFORM_C1E_MODE
1565 #define CFG_C1E_MODE BLDCFG_PLATFORM_C1E_MODE
1566#else
1567 #define CFG_C1E_MODE C1eModeDisabled
1568#endif
1569
1570#ifdef BLDCFG_PLATFORM_C1E_OPDATA
1571 #define CFG_C1E_OPDATA BLDCFG_PLATFORM_C1E_OPDATA
1572#else
1573 #define CFG_C1E_OPDATA 0
1574#endif
1575
1576#ifdef BLDCFG_PLATFORM_C1E_OPDATA1
1577 #define CFG_C1E_OPDATA1 BLDCFG_PLATFORM_C1E_OPDATA1
1578#else
1579 #define CFG_C1E_OPDATA1 0
1580#endif
1581
1582#ifdef BLDCFG_PLATFORM_C1E_OPDATA2
1583 #define CFG_C1E_OPDATA2 BLDCFG_PLATFORM_C1E_OPDATA2
1584#else
1585 #define CFG_C1E_OPDATA2 0
1586#endif
1587
1588#ifdef BLDCFG_PLATFORM_CSTATE_MODE
1589 #define CFG_CSTATE_MODE BLDCFG_PLATFORM_CSTATE_MODE
1590#else
1591 #define CFG_CSTATE_MODE CStateModeDisabled
1592#endif
1593
1594#ifdef BLDCFG_PLATFORM_CSTATE_OPDATA
1595 #define CFG_CSTATE_OPDATA BLDCFG_PLATFORM_CSTATE_OPDATA
1596#else
1597 #define CFG_CSTATE_OPDATA 0
1598#endif
1599
1600#ifdef BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
1601 #define CFG_CSTATE_IO_BASE_ADDRESS BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
1602#else
1603 #define CFG_CSTATE_IO_BASE_ADDRESS 0
1604#endif
1605
1606#ifdef BLDCFG_PLATFORM_CPB_MODE
1607 #define CFG_CPB_MODE BLDCFG_PLATFORM_CPB_MODE
1608#else
1609 #define CFG_CPB_MODE CpbModeAuto
1610#endif
1611
1612#ifdef BLDCFG_CORE_LEVELING_MODE
1613 #define CFG_CORE_LEVELING_MODE BLDCFG_CORE_LEVELING_MODE
1614#else
1615 #define CFG_CORE_LEVELING_MODE 0
1616#endif
1617
1618#ifdef BLDCFG_AMD_PSTATE_CAP_VALUE
1619 #define CFG_AMD_PSTATE_CAP_VALUE BLDCFG_AMD_PSTATE_CAP_VALUE
1620#else
1621 #define CFG_AMD_PSTATE_CAP_VALUE 0
1622#endif
1623
1624#ifdef BLDCFG_HEAP_DRAM_ADDRESS
1625 #define CFG_HEAP_DRAM_ADDRESS BLDCFG_HEAP_DRAM_ADDRESS
1626#else
1627 #define CFG_HEAP_DRAM_ADDRESS AMD_HEAP_RAM_ADDRESS
1628#endif
1629
1630#ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
1631 #define CFG_MEMORY_BUS_FREQUENCY_LIMIT BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
1632#else
1633 #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR800_FREQUENCY
1634#endif
1635
1636#ifdef BLDCFG_MEMORY_MODE_UNGANGED
1637 #define CFG_MEMORY_MODE_UNGANGED BLDCFG_MEMORY_MODE_UNGANGED
1638#else
1639 #define CFG_MEMORY_MODE_UNGANGED TRUE
1640#endif
1641
1642#ifdef BLDCFG_MEMORY_QUAD_RANK_CAPABLE
1643 #define CFG_MEMORY_QUAD_RANK_CAPABLE BLDCFG_MEMORY_QUAD_RANK_CAPABLE
1644#else
1645 #define CFG_MEMORY_QUAD_RANK_CAPABLE TRUE
1646#endif
1647
1648#ifdef BLDCFG_MEMORY_QUADRANK_TYPE
1649 #define CFG_MEMORY_QUADRANK_TYPE BLDCFG_MEMORY_QUADRANK_TYPE
1650#else
1651 #define CFG_MEMORY_QUADRANK_TYPE DFLT_MEMORY_QUADRANK_TYPE
1652#endif
1653
1654#ifdef BLDCFG_MEMORY_RDIMM_CAPABLE
1655 #define CFG_MEMORY_RDIMM_CAPABLE BLDCFG_MEMORY_RDIMM_CAPABLE
1656#else
1657 #define CFG_MEMORY_RDIMM_CAPABLE TRUE
1658#endif
1659
1660#ifdef BLDCFG_MEMORY_LRDIMM_CAPABLE
1661 #define CFG_MEMORY_LRDIMM_CAPABLE BLDCFG_MEMORY_LRDIMM_CAPABLE
1662#else
1663 #define CFG_MEMORY_LRDIMM_CAPABLE TRUE
1664#endif
1665
1666#ifdef BLDCFG_MEMORY_UDIMM_CAPABLE
1667 #define CFG_MEMORY_UDIMM_CAPABLE BLDCFG_MEMORY_UDIMM_CAPABLE
1668#else
1669 #define CFG_MEMORY_UDIMM_CAPABLE TRUE
1670#endif
1671
1672#ifdef BLDCFG_MEMORY_SODIMM_CAPABLE
1673 #define CFG_MEMORY_SODIMM_CAPABLE BLDCFG_MEMORY_SODIMM_CAPABLE
1674#else
1675 #define CFG_MEMORY_SODIMM_CAPABLE FALSE
1676#endif
1677
1678#ifdef BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
1679 #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
1680#else
1681 #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
1682#endif
1683
1684#ifdef BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
1685 #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
1686#else
1687 #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
1688#endif
1689
1690#ifdef BLDCFG_MEMORY_CHANNEL_INTERLEAVING
1691 #define CFG_MEMORY_CHANNEL_INTERLEAVING BLDCFG_MEMORY_CHANNEL_INTERLEAVING
1692#else
1693 #define CFG_MEMORY_CHANNEL_INTERLEAVING TRUE
1694#endif
1695
1696#ifdef BLDCFG_MEMORY_POWER_DOWN
1697 #define CFG_MEMORY_POWER_DOWN BLDCFG_MEMORY_POWER_DOWN
1698#else
1699 #define CFG_MEMORY_POWER_DOWN FALSE
1700#endif
1701
1702#ifdef BLDCFG_POWER_DOWN_MODE
1703 #define CFG_POWER_DOWN_MODE BLDCFG_POWER_DOWN_MODE
1704#else
1705 #define CFG_POWER_DOWN_MODE POWER_DOWN_MODE_AUTO
1706#endif
1707
1708#ifdef BLDCFG_ONLINE_SPARE
1709 #define CFG_ONLINE_SPARE BLDCFG_ONLINE_SPARE
1710#else
1711 #define CFG_ONLINE_SPARE FALSE
1712#endif
1713
1714#ifdef BLDCFG_MEMORY_PARITY_ENABLE
1715 #define CFG_MEMORY_PARITY_ENABLE BLDCFG_MEMORY_PARITY_ENABLE
1716#else
1717 #define CFG_MEMORY_PARITY_ENABLE FALSE
1718#endif
1719
1720#ifdef BLDCFG_BANK_SWIZZLE
1721 #define CFG_BANK_SWIZZLE BLDCFG_BANK_SWIZZLE
1722#else
1723 #define CFG_BANK_SWIZZLE TRUE
1724#endif
1725
1726#ifdef BLDCFG_TIMING_MODE_SELECT
1727 #define CFG_TIMING_MODE_SELECT BLDCFG_TIMING_MODE_SELECT
1728#else
1729 #define CFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
1730#endif
1731
1732#ifdef BLDCFG_MEMORY_CLOCK_SELECT
1733 #define CFG_MEMORY_CLOCK_SELECT BLDCFG_MEMORY_CLOCK_SELECT
1734#else
1735 #define CFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY
1736#endif
1737
1738#ifdef BLDCFG_DQS_TRAINING_CONTROL
1739 #define CFG_DQS_TRAINING_CONTROL BLDCFG_DQS_TRAINING_CONTROL
1740#else
1741 #define CFG_DQS_TRAINING_CONTROL TRUE
1742#endif
1743
1744#ifdef BLDCFG_IGNORE_SPD_CHECKSUM
1745 #define CFG_IGNORE_SPD_CHECKSUM BLDCFG_IGNORE_SPD_CHECKSUM
1746#else
1747 #define CFG_IGNORE_SPD_CHECKSUM FALSE
1748#endif
1749
1750#ifdef BLDCFG_USE_BURST_MODE
1751 #define CFG_USE_BURST_MODE BLDCFG_USE_BURST_MODE
1752#else
1753 #define CFG_USE_BURST_MODE FALSE
1754#endif
1755
1756#ifdef BLDCFG_MEMORY_ALL_CLOCKS_ON
1757 #define CFG_MEMORY_ALL_CLOCKS_ON BLDCFG_MEMORY_ALL_CLOCKS_ON
1758#else
1759 #define CFG_MEMORY_ALL_CLOCKS_ON FALSE
1760#endif
1761
1762#ifdef BLDCFG_ENABLE_ECC_FEATURE
1763 #define CFG_ENABLE_ECC_FEATURE BLDCFG_ENABLE_ECC_FEATURE
1764#else
1765 #define CFG_ENABLE_ECC_FEATURE TRUE
1766#endif
1767
1768#ifdef BLDCFG_ECC_REDIRECTION
1769 #define CFG_ECC_REDIRECTION BLDCFG_ECC_REDIRECTION
1770#else
1771 #define CFG_ECC_REDIRECTION FALSE
1772#endif
1773
1774#ifdef BLDCFG_SCRUB_DRAM_RATE
1775 #define CFG_SCRUB_DRAM_RATE BLDCFG_SCRUB_DRAM_RATE
1776#else
1777 #define CFG_SCRUB_DRAM_RATE DFLT_SCRUB_DRAM_RATE
1778#endif
1779
1780#ifdef BLDCFG_SCRUB_L2_RATE
1781 #define CFG_SCRUB_L2_RATE BLDCFG_SCRUB_L2_RATE
1782#else
1783 #define CFG_SCRUB_L2_RATE DFLT_SCRUB_L2_RATE
1784#endif
1785
1786#ifdef BLDCFG_SCRUB_L3_RATE
1787 #define CFG_SCRUB_L3_RATE BLDCFG_SCRUB_L3_RATE
1788#else
1789 #define CFG_SCRUB_L3_RATE DFLT_SCRUB_L3_RATE
1790#endif
1791
1792#ifdef BLDCFG_SCRUB_IC_RATE
1793 #define CFG_SCRUB_IC_RATE BLDCFG_SCRUB_IC_RATE
1794#else
1795 #define CFG_SCRUB_IC_RATE DFLT_SCRUB_IC_RATE
1796#endif
1797
1798#ifdef BLDCFG_SCRUB_DC_RATE
1799 #define CFG_SCRUB_DC_RATE BLDCFG_SCRUB_DC_RATE
1800#else
1801 #define CFG_SCRUB_DC_RATE DFLT_SCRUB_DC_RATE
1802#endif
1803
1804#ifdef BLDCFG_ECC_SYNC_FLOOD
1805 #define CFG_ECC_SYNC_FLOOD BLDCFG_ECC_SYNC_FLOOD
1806#else
1807 #define CFG_ECC_SYNC_FLOOD 0
1808#endif
1809
1810#ifdef BLDCFG_ECC_SYMBOL_SIZE
1811 #define CFG_ECC_SYMBOL_SIZE BLDCFG_ECC_SYMBOL_SIZE
1812#else
1813 #define CFG_ECC_SYMBOL_SIZE 0
1814#endif
1815
1816#ifdef BLDCFG_1GB_ALIGN
1817 #define CFG_1GB_ALIGN BLDCFG_1GB_ALIGN
1818#else
1819 #define CFG_1GB_ALIGN FALSE
1820#endif
1821
1822#ifdef BLDCFG_UMA_ALLOCATION_MODE
1823 #define CFG_UMA_MODE BLDCFG_UMA_ALLOCATION_MODE
1824#else
1825 #define CFG_UMA_MODE UMA_AUTO
1826#endif
1827
1828#ifdef BLDCFG_UMA_ALLOCATION_SIZE
1829 #define CFG_UMA_SIZE BLDCFG_UMA_ALLOCATION_SIZE
1830#else
1831 #define CFG_UMA_SIZE 0
1832#endif
1833
1834#ifdef BLDCFG_UMA_ABOVE4G_SUPPORT
1835 #define CFG_UMA_ABOVE4G BLDCFG_UMA_ABOVE4G_SUPPORT
1836#else
1837 #define CFG_UMA_ABOVE4G FALSE
1838#endif
1839
1840#ifdef BLDCFG_UMA_ALIGNMENT
1841 #define CFG_UMA_ALIGNMENT BLDCFG_UMA_ALIGNMENT
1842#else
1843 #define CFG_UMA_ALIGNMENT NO_UMA_ALIGNED
1844#endif
1845
1846#ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB
1847 #define CFG_PROCESSOR_SCOPE_IN_SB BLDCFG_PROCESSOR_SCOPE_IN_SB
1848#else
1849 #define CFG_PROCESSOR_SCOPE_IN_SB FALSE
1850#endif
1851
1852#ifdef BLDCFG_S3_LATE_RESTORE
1853 #define CFG_S3_LATE_RESTORE BLDCFG_S3_LATE_RESTORE
1854#else
1855 #define CFG_S3_LATE_RESTORE TRUE
1856#endif
1857
1858#ifdef BLDCFG_USE_32_BYTE_REFRESH
1859 #define CFG_USE_32_BYTE_REFRESH (BLDCFG_USE_32_BYTE_REFRESH)
1860#else
1861 #define CFG_USE_32_BYTE_REFRESH (FALSE)
1862#endif
1863
1864#ifdef BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY
1865 #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
1866#else
1867 #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (FALSE)
1868#endif
1869
1870#ifdef BLDCFG_PROCESSOR_SCOPE_NAME0
1871 #define CFG_PROCESSOR_SCOPE_NAME0 BLDCFG_PROCESSOR_SCOPE_NAME0
1872#else
1873 #define CFG_PROCESSOR_SCOPE_NAME0 SCOPE_NAME_VALUE
1874#endif
1875
1876#ifdef BLDCFG_PROCESSOR_SCOPE_NAME1
1877 #define CFG_PROCESSOR_SCOPE_NAME1 BLDCFG_PROCESSOR_SCOPE_NAME1
1878#else
1879 #define CFG_PROCESSOR_SCOPE_NAME1 SCOPE_NAME_VALUE1
1880#endif
1881
1882#ifdef BLDCFG_CFG_GNB_HD_AUDIO
1883 #define CFG_GNB_HD_AUDIO BLDCFG_CFG_GNB_HD_AUDIO
1884#else
1885 #define CFG_GNB_HD_AUDIO TRUE
1886#endif
1887
1888#ifdef BLDCFG_CFG_ABM_SUPPORT
1889 #define CFG_ABM_SUPPORT BLDCFG_CFG_ABM_SUPPORT
1890#else
1891 #define CFG_ABM_SUPPORT FALSE
1892#endif
1893
1894#ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE
1895 #define CFG_DINAMIC_REFRESH_RATE BLDCFG_CFG_DYNAMIC_REFRESH_RATE
1896#else
1897 #define CFG_DYNAMIC_REFRESH_RATE 0
1898#endif
1899
1900#ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
1901 #define CFG_LCD_BACK_LIGHT_CONTROL BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
1902#else
1903 #define CFG_LCD_BACK_LIGHT_CONTROL 0
1904#endif
1905
1906#ifdef BLDCFG_STEREO_3D_PINOUT
1907 #define CFG_GNB_STEREO_3D_PINOUT BLDCFG_STEREO_3D_PINOUT
1908#else
1909 #define CFG_GNB_STEREO_3D_PINOUT 0
1910#endif
1911
1912#ifdef BLDCFG_IGPU_SUBSYSTEM_ID
1913 #define CFG_GNB_IGPU_SSID BLDCFG_IGPU_SUBSYSTEM_ID
1914#else
1915 #define CFG_GNB_IGPU_SSID 0
1916#endif
1917
1918#ifdef BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
1919 #define CFG_GNB_HDAUDIO_SSID BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
1920#else
1921 #define CFG_GNB_HDAUDIO_SSID 0
1922#endif
1923
1924#ifdef BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
1925 #define CFG_GNB_PCIE_SSID BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
1926#else
1927 #define CFG_GNB_PCIE_SSID 0x12341022
1928#endif
1929
1930#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
1931 #define CFG_GFX_LVDS_SPREAD_SPECTRUM BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
1932#else
1933 #define CFG_GFX_LVDS_SPREAD_SPECTRUM 0
1934#endif
1935
1936#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
1937 #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
1938#else
1939 #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE 0
1940#endif
1941
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]1942#ifdef BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
1943 #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
1944#else
1945 #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM 0
1946#endif
1947
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1948#ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
1949 #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
1950#else
1951 #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000
1952#endif
1953
1954#ifdef BLDOPT_REMOVE_EARLY_SAMPLES
1955 #if BLDOPT_REMOVE_EARLY_SAMPLES == TRUE
1956 #undef OPTION_EARLY_SAMPLES
1957 #define OPTION_EARLY_SAMPLES FALSE
1958 #else
1959 #undef OPTION_EARLY_SAMPLES
1960 #define OPTION_EARLY_SAMPLES TRUE
1961 #endif
1962#endif
1963
1964#ifdef BLDOPT_REMOVE_ALIB
1965 #if BLDOPT_REMOVE_ALIB == TRUE
1966 #undef OPTION_ALIB
1967 #define OPTION_ALIB FALSE
1968 #else
1969 #undef OPTION_ALIB
1970 #define OPTION_ALIB TRUE
1971 #endif
1972#endif
1973
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]1974#ifdef BLDCFG_LVDS_MISC_888_FPDI_MODE
1975 #define CFG_LVDS_MISC_888_FPDI_MODE BLDCFG_LVDS_MISC_888_FPDI_MODE
1976#else
1977 #define CFG_LVDS_MISC_888_FPDI_MODE FALSE
1978#endif
1979
1980#ifdef BLDCFG_LVDS_MISC_DL_CH_SWAP
1981 #define CFG_LVDS_MISC_DL_CH_SWAP BLDCFG_LVDS_MISC_DL_CH_SWAP
1982#else
1983 #define CFG_LVDS_MISC_DL_CH_SWAP FALSE
1984#endif
1985
1986#ifdef BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
1987 #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
1988#else
1989 #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW FALSE
1990#endif
1991
1992#ifdef BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
1993 #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
1994#else
1995 #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW FALSE
1996#endif
1997
1998#ifdef BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
1999 #define CFG_LVDS_MISC_BLON_ACTIVE_LOW BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
2000#else
2001 #define CFG_LVDS_MISC_BLON_ACTIVE_LOW FALSE
2002#endif
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]2003/*---------------------------------------------------------------------------
2004 * Processing the options: Third, perform the option cross checks
2005 *--------------------------------------------------------------------------*/
2006// Assure that at least one type of memory support is included
2007#if OPTION_UDIMMS == FALSE
2008 #if OPTION_RDIMMS == FALSE
2009 #if OPTION_SODIMMS == FALSE
2010 #if OPTION_LRDIMMS == FALSE
2011 #error BLDOPT: No DIMM support selected. Either BLDOPT_REMOVE_UDIMMS_SUPPORT or BLDOPT_REMOVE_RDIMMS_SUPPORT or BLDOPT_REMOVE_SODIMMS_SUPPORT or BLDOPT_REMOVE_LRDIMMS_SUPPORT must be FALSE.
2012 #endif
2013 #endif
2014 #endif
2015#endif
2016// Ensure at least one dimm type is capable
2017#if CFG_MEMORY_RDIMM_CAPABLE == FALSE
2018 #if CFG_MEMORY_UDIMM_CAPABLE == FALSE
2019 #if CFG_MEMORY_SODIMM_CAPABLE == FALSE
2020 #if CFG_MEMORY_LRDIMM_CAPABLE == FALSE
2021 #error BLDCFG: No dimm type is capable
2022 #endif
2023 #endif
2024 #endif
2025#endif
2026// Check LRDIMM CODE and LRDIMM CFG item
2027#if CFG_MEMORY_LRDIMM_CAPABLE == FALSE
2028 #if BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE
2029 #error Warning: LRDIMM capability is false, but LRIDMM support code included
2030 #endif
2031#endif
2032// Turn off multi-socket based features if only one node...
2033#if OPTION_MULTISOCKET == FALSE
2034 #undef OPTION_PARALLEL_TRAINING
2035 #define OPTION_PARALLEL_TRAINING FALSE
2036 #undef OPTION_NODE_INTERLEAVE
2037 #define OPTION_NODE_INTERLEAVE FALSE
2038#endif
2039// Ensure that at least one write leveling option is selected
2040#if OPTION_DDR3 == TRUE
2041 #if OPTION_HW_WRITE_LEV_TRAINING == FALSE
2042 #if OPTION_SW_WRITE_LEV_TRAINING == FALSE
2043 #error No Write leveling option selected for DDR3
2044 #endif
2045 #endif
2046 #if OPTION_SW_DRAM_INIT == FALSE
2047 #error Software dram init must be enabled for DDR3 dimms
2048 #endif
2049#endif
2050// Ensure at least one DQS receiver training option is selected
2051#if OPTION_HW_DQS_REC_EN_TRAINING == FALSE
2052 #if OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == FALSE
2053 #if OPTION_OPT_SW_DQS_REC_EN_TRAINING == FALSE
2054 #error No DQS receiver training option has been slected
2055 #endif
2056 #endif
2057#endif
2058// Ensure at least one Rd Wr position training option has been selected
2059#if OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == FALSE
2060 #if OPTION_OPT_SW_RD_WR_POS_TRAINING == FALSE
2061 #error No Rd Wr position training option has been selected
2062 #endif
2063#endif
2064// Ensure at least one dram init option has been selected
2065#if OPTION_HW_DRAM_INIT == FALSE
2066 #if OPTION_SW_DRAM_INIT == FALSE
2067 #error No Dram init option has been selected
2068 #endif
2069#endif
2070// Ensure the frequency limit is valid
2071#if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1866_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 933)
2072 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 800)
2073 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1333_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 667)
2074 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1066_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 533)
2075 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR800_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 400)
2076 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR667_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 333)
2077 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR533_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 266)
2078 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR400_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 200)
2079 #error BLDCFG: Unsupported memory bus frequency
2080 #endif
2081 #endif
2082 #endif
2083 #endif
2084 #endif
2085 #endif
2086 #endif
2087#endif
2088// Ensure timing mode is valid
2089#if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC
2090 #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED
2091 #if CFG_TIMING_MODE_SELECT != TIMING_MODE_AUTO
2092 #error BLDCFG: Invalid timing mode is set
2093 #endif
2094 #endif
2095#endif
2096// Ensure the scrub rate is valid
2097#if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF))
2098 #error BLDCFG: Unsupported dram scrub rate set
2099#endif
2100#if CFG_SCRUB_L2_RATE > 0x16
2101 #error BLDCFG: Unsupported L2 scrubber rate set
2102#endif
2103#if CFG_SCRUB_L3_RATE > 0x16
2104 #error BLDCFG: unsupported L3 scrubber rate set
2105#endif
2106#if CFG_SCRUB_IC_RATE > 0x16
2107 #error BLDCFG: Unsupported Instruction cache scrub rate set
2108#endif
2109#if CFG_SCRUB_DC_RATE > 0x16
2110 #error BLDCFG: Unsupported Dcache scrub rate set
2111#endif
2112// Ensure Quad rank dimm type is valid
2113#if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED
2114 #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED
2115 #error BLDCFG: Invalid quad rank dimm type set
2116 #endif
2117#endif
2118// Ensure ECC symbol size is valid
2119#if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG
2120 #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4
2121 #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X8
2122 #error BLDCFG: Invalid Ecc symbol size set
2123 #endif
2124 #endif
2125#endif
2126// Ensure power down mode is valid
2127#if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT
2128 #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL
2129 #error BLDCFG: Invalid power down mode set
2130 #endif
2131#endif
2132
2133/*****************************************************************************
2134 *
2135 * Process the option logic, setting local control variables
2136 *
2137 ****************************************************************************/
2138#if OPTION_ACPI_PSTATES == TRUE
2139 #define OPTFCN_ACPI_TABLES CreateAcpiTablesMain
2140 #define OPTFCN_GATHER_DATA PStateGatherData
2141 #if OPTION_MULTISOCKET == TRUE
2142 #define OPTFCN_PSTATE_LEVELING PStateLeveling
2143 #else
2144 #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess
2145 #endif
2146#else
2147 #define OPTFCN_ACPI_TABLES CommonReturnAgesaSuccess
2148 #define OPTFCN_GATHER_DATA CommonReturnAgesaSuccess
2149 #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess
2150#endif
2151
2152
2153/*****************************************************************************
2154 *
2155 * Include the structure definitions for the defaults table structures
2156 *
2157 ****************************************************************************/
2158#include "Options.h"
2159#include "OptionCpuFamiliesInstall.h"
2160#include "OptionsHt.h"
2161#include "OptionHtInstall.h"
2162#include "OptionMemory.h"
2163#include "PlatformMemoryConfiguration.h"
2164#include "OptionMemoryInstall.h"
2165#include "OptionMemoryRecovery.h"
2166#include "OptionMemoryRecoveryInstall.h"
2167#include "OptionCpuFeaturesInstall.h"
2168#include "OptionDmi.h"
2169#include "OptionDmiInstall.h"
2170#include "OptionPstate.h"
2171#include "OptionPstateInstall.h"
2172#include "OptionWhea.h"
2173#include "OptionWheaInstall.h"
2174#include "OptionSrat.h"
2175#include "OptionSratInstall.h"
2176#include "OptionSlit.h"
2177#include "OptionSlitInstall.h"
2178#include "OptionMultiSocket.h"
2179#include "OptionMultiSocketInstall.h"
2180#include "OptionIdsInstall.h"
2181#include "OptionGfxRecovery.h"
2182#include "OptionGfxRecoveryInstall.h"
2183#include "OptionGnb.h"
2184#include "OptionGnbInstall.h"
2185#include "OptionS3ScriptInstall.h"
2186
2187
2188/*****************************************************************************
2189 *
2190 * Generate the output structures (defaults tables)
2191 *
2192 ****************************************************************************/
2193BUILD_OPT_CFG UserOptions = {
2194 { // AGESA version string
2195 AGESA_CODE_SIGNATURE, // code header Signature
2196 AGESA_PACKAGE_STRING, // 8 character ID
2197 AGESA_VERSION_STRING, // 12 character version string
2198 0 // null string terminator
2199 },
2200 //Build Option Area
2201 OPTION_UDIMMS, //UDIMMS
2202 OPTION_RDIMMS, //RDIMMS
2203 OPTION_LRDIMMS, //LRDIMMS
2204 OPTION_ECC, //ECC
2205 OPTION_BANK_INTERLEAVE, //BANK_INTERLEAVE
2206 OPTION_DCT_INTERLEAVE, //DCT_INTERLEAVE
2207 OPTION_NODE_INTERLEAVE, //NODE_INTERLEAVE
2208 OPTION_PARALLEL_TRAINING, //PARALLEL_TRAINING
2209 OPTION_ONLINE_SPARE, //ONLINE_SPARE
2210 OPTION_MEM_RESTORE, //MEM CONTEXT RESTORE
2211 OPTION_MULTISOCKET, //MULTISOCKET
2212 OPTION_ACPI_PSTATES, //ACPI_PSTATES
2213 OPTION_SRAT, //SRAT
2214 OPTION_SLIT, //SLIT
2215 OPTION_WHEA, //WHEA
2216 OPTION_DMI, //DMI
2217 OPTION_EARLY_SAMPLES, //EARLY_SAMPLES
2218 OPTION_ADDR_TO_CS_TRANSLATOR, //ADDR_TO_CS_TRANSLATOR
2219
2220 //Build Configuration Area
2221 CFG_PCI_MMIO_BASE,
2222 CFG_PCI_MMIO_SIZE,
2223 {
2224 // CoreVrm
2225 {
2226 CFG_VRM_CURRENT_LIMIT, // VrmCurrentLimit
2227 CFG_VRM_LOW_POWER_THRESHOLD, // VrmLowPowerThershold
2228 CFG_VRM_SLEW_RATE, // VrmSlewRate
2229 CFG_VRM_ADDITIONAL_DELAY, // VrmAdditionalDelay
2230 CFG_VRM_HIGH_SPEED_ENABLE, // VrmHiSpeedEnable
2231 CFG_VRM_INRUSH_CURRENT_LIMIT // VrmInrushCurrentLimit
2232 },
2233 // NbVrm
2234 {
2235 CFG_VRM_NB_CURRENT_LIMIT, // VrmNbCurrentLimit
2236 CFG_VRM_NB_LOW_POWER_THRESHOLD, // VrmNbLowPowerThershold
2237 CFG_VRM_NB_SLEW_RATE, // VrmNbSlewRate
2238 CFG_VRM_NB_ADDITIONAL_DELAY, // VrmNbAdditionalDelay
2239 CFG_VRM_NB_HIGH_SPEED_ENABLE, // VrmNbHiSpeedEnable
2240 CFG_VRM_NB_INRUSH_CURRENT_LIMIT // VrmNbInrushCurrentLimit
2241 }
2242 },
2243 CFG_PLAT_NUM_IO_APICS, //PlatformApicIoNumber
2244 CFG_MEM_INIT_PSTATE, //MemoryInitPstate
2245 CFG_C1E_MODE, //C1eMode
2246 CFG_C1E_OPDATA, //C1ePlatformData
2247 CFG_C1E_OPDATA1, //C1ePlatformData1
2248 CFG_C1E_OPDATA2, //C1ePlatformData2
2249 CFG_CSTATE_MODE, //CStateMode
2250 CFG_CSTATE_OPDATA, //CStatePlatformData
2251 CFG_CSTATE_IO_BASE_ADDRESS, //CStateIoBaseAddress
2252 CFG_CPB_MODE, //CpbMode
2253 CFG_CORE_LEVELING_MODE, //CoreLevelingCofig
2254 {
2255 CFG_PLATFORM_CONTROL_FLOW_MODE, // The platform's control flow mode.
2256 CFG_USE_HT_ASSIST, // CfgUseHtAssist
2257 CFG_USE_ATM_MODE, // CfgUseAtmMode
2258 CFG_USE_32_BYTE_REFRESH, // Display Refresh uses 32 byte packets.
2259 CFG_USE_VARIABLE_MCT_ISOC_PRIORITY, // The Memory controller will be set to Variable Isoc Priority.
2260 CFG_PLATFORM_POWER_POLICY_MODE // The platform's power policy mode.
2261 },
2262 (CPU_HT_DEEMPHASIS_LEVEL *)CFG_PLATFORM_DEEMPHASIS_LIST, // Deemphasis settings
2263 CFG_AMD_PLATFORM_TYPE, //AmdPlatformType
2264 CFG_AMD_PSTATE_CAP_VALUE, // Amd pstate ceiling enabling deck
2265
2266 CFG_MEMORY_BUS_FREQUENCY_LIMIT, // CfgMemoryBusFrequencyLimit
2267 CFG_MEMORY_MODE_UNGANGED, // CfgMemoryModeUnganged
2268 CFG_MEMORY_QUAD_RANK_CAPABLE, // CfgMemoryQuadRankCapable
2269 CFG_MEMORY_QUADRANK_TYPE, // CfgMemoryQuadrankType
2270 CFG_MEMORY_RDIMM_CAPABLE, // CfgMemoryRDimmCapable
2271 CFG_MEMORY_LRDIMM_CAPABLE, // CfgMemoryLRDimmCapable
2272 CFG_MEMORY_UDIMM_CAPABLE, // CfgMemoryUDimmCapable
2273 CFG_MEMORY_SODIMM_CAPABLE, // CfgMemorySodimmCapable
2274 CFG_MEMORY_ENABLE_BANK_INTERLEAVING, // CfgMemoryEnableBankInterleaving
2275 CFG_MEMORY_ENABLE_NODE_INTERLEAVING, // CfgMemoryEnableNodeInterleaving
2276 CFG_MEMORY_CHANNEL_INTERLEAVING, // CfgMemoryChannelInterleaving
2277 CFG_MEMORY_POWER_DOWN, // CfgMemoryPowerDown
2278 CFG_POWER_DOWN_MODE, // CfgPowerDownMode
2279 CFG_ONLINE_SPARE, // CfgOnlineSpare
2280 CFG_MEMORY_PARITY_ENABLE, // CfgMemoryParityEnable
2281 CFG_BANK_SWIZZLE, // CfgBankSwizzle
2282 CFG_TIMING_MODE_SELECT, // CfgTimingModeSelect
2283 CFG_MEMORY_CLOCK_SELECT, // CfgMemoryClockSelect
2284 CFG_DQS_TRAINING_CONTROL, // CfgDqsTrainingControl
2285 CFG_IGNORE_SPD_CHECKSUM, // CfgIgnoreSpdChecksum
2286 CFG_USE_BURST_MODE, // CfgUseBurstMode
2287 CFG_MEMORY_ALL_CLOCKS_ON, // CfgMemoryAllClocksOn
2288 CFG_ENABLE_ECC_FEATURE, // CfgEnableEccFeature
2289 CFG_ECC_REDIRECTION, // CfgEccRedirection
2290 CFG_SCRUB_DRAM_RATE, // CfgScrubDramRate
2291 CFG_SCRUB_L2_RATE, // CfgScrubL2Rate
2292 CFG_SCRUB_L3_RATE, // CfgScrubL3Rate
2293 CFG_SCRUB_IC_RATE, // CfgScrubIcRate
2294 CFG_SCRUB_DC_RATE, // CfgScrubDcRate
2295 CFG_ECC_SYNC_FLOOD, // CfgEccSyncFlood
2296 CFG_ECC_SYMBOL_SIZE, // CfgEccSymbolSize
2297 CFG_HEAP_DRAM_ADDRESS, // CfgHeapDramAddress
2298 CFG_1GB_ALIGN, // CfgNodeMem1GBAlign
2299 CFG_S3_LATE_RESTORE, // CfgS3LateRestore
2300 CFG_ACPI_PSTATE_PSD_INDPX, // CfgAcpiPstateIndependent
2301 (AP_MTRR_SETTINGS *) CFG_AP_MTRR_SETTINGS_LIST, // CfgApMtrrSettingsList
2302 CFG_UMA_MODE, // CfgUmaMode
2303 CFG_UMA_SIZE, // CfgUmaSize
2304 CFG_UMA_ABOVE4G, // CfgUmaAbove4G
2305 CFG_UMA_ALIGNMENT, // CfgUmaAlignment
2306 CFG_PROCESSOR_SCOPE_IN_SB, // CfgProcessorScopeInSb
2307 CFG_PROCESSOR_SCOPE_NAME0, // CfgProcessorScopeName0
2308 CFG_PROCESSOR_SCOPE_NAME1, // CfgProcessorScopeName1
2309 CFG_GNB_HD_AUDIO, // CfgGnbHdAudio
2310 CFG_ABM_SUPPORT, // CfgAbmSupport
2311 CFG_DYNAMIC_REFRESH_RATE, // CfgDynamicRefreshRate
2312 CFG_LCD_BACK_LIGHT_CONTROL, // CfgLcdBackLightControl
2313 CFG_GNB_STEREO_3D_PINOUT, // CfgGnb3dStereoPinIndex
2314 CFG_TEMP_PCIE_MMIO_BASE_ADDRESS, // CfgTempPcieMmioBaseAddress
2315 CFG_GNB_IGPU_SSID, // CfgGnbIGPUSSID
2316 CFG_GNB_HDAUDIO_SSID, // CfgGnbHDAudioSSID
2317 CFG_GNB_PCIE_SSID, // CfgGnbPcieSSID
2318 CFG_GFX_LVDS_SPREAD_SPECTRUM, // CfgLvdsSpreadSpectrum
2319 CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE, // CfgLvdsSpreadSpectrumRate
2320
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]2321 {{
2322 CFG_LVDS_MISC_888_FPDI_MODE, // CfgLvdsMiscControl
2323 CFG_LVDS_MISC_DL_CH_SWAP, // CfgLvdsMiscControl
2324 CFG_LVDS_MISC_VSYNC_ACTIVE_LOW, // CfgLvdsMiscControl
2325 CFG_LVDS_MISC_HSYNC_ACTIVE_LOW, // CfgLvdsMiscControl
2326 CFG_LVDS_MISC_BLON_ACTIVE_LOW, // CfgLvdsMiscControl
2327 }},
2328 CFG_PCIE_REFCLK_SPREAD_SPECTRUM, // CfgPcieRefClkSpreadSpectrum
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]2329 0, //reserved...
2330};
2331
2332CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] =
2333{
2334 #if AGESA_ENTRY_INIT_RESET == TRUE
2335 { AMD_INIT_RESET,
2336 sizeof (AMD_RESET_PARAMS),
2337 (PF_AGESA_FUNCTION) AmdInitResetConstructor,
2338 (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
2339 AMD_INIT_RESET_HANDLE
2340 },
2341 #endif
2342
2343 #if AGESA_ENTRY_INIT_RECOVERY == TRUE
2344 { AMD_INIT_RECOVERY,
2345 sizeof (AMD_RECOVERY_PARAMS),
2346 (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer,
2347 (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
2348 AMD_INIT_POST_HANDLE
2349 },
2350 #endif
2351
2352 #if AGESA_ENTRY_INIT_EARLY == TRUE
2353 { AMD_INIT_EARLY,
2354 sizeof (AMD_EARLY_PARAMS),
2355 (PF_AGESA_FUNCTION) AmdInitEarlyInitializer,
2356 (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
2357 AMD_INIT_EARLY_HANDLE
2358 },
2359 #endif
2360
2361 #if AGESA_ENTRY_INIT_ENV == TRUE
2362 { AMD_INIT_ENV,
2363 sizeof (AMD_ENV_PARAMS),
2364 (PF_AGESA_FUNCTION) AmdInitEnvInitializer,
2365 (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
2366 AMD_INIT_ENV_HANDLE
2367 },
2368 #endif
2369
2370 #if AGESA_ENTRY_INIT_LATE == TRUE
2371 { AMD_INIT_LATE,
2372 sizeof (AMD_LATE_PARAMS),
2373 (PF_AGESA_FUNCTION) AmdInitLateInitializer,
2374 (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor,
2375 AMD_INIT_LATE_HANDLE
2376 },
2377 #endif
2378
2379 #if AGESA_ENTRY_INIT_MID == TRUE
2380 { AMD_INIT_MID,
2381 sizeof (AMD_MID_PARAMS),
2382 (PF_AGESA_FUNCTION) AmdInitMidInitializer,
2383 (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
2384 AMD_INIT_MID_HANDLE
2385 },
2386 #endif
2387
2388 #if AGESA_ENTRY_INIT_POST == TRUE
2389 { AMD_INIT_POST,
2390 sizeof (AMD_POST_PARAMS),
2391 (PF_AGESA_FUNCTION) AmdInitPostInitializer,
2392 (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor,
2393 AMD_INIT_POST_HANDLE
2394 },
2395 #endif
2396
2397 #if AGESA_ENTRY_INIT_RESUME == TRUE
2398 { AMD_INIT_RESUME,
2399 sizeof (AMD_RESUME_PARAMS),
2400 (PF_AGESA_FUNCTION) AmdInitResumeInitializer,
2401 (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor,
2402 AMD_INIT_RESUME_HANDLE
2403 },
2404 #endif
2405
2406 #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
2407 { AMD_S3LATE_RESTORE,
2408 sizeof (AMD_S3LATE_PARAMS),
2409 (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer,
2410 (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
2411 AMD_S3_LATE_RESTORE_HANDLE
2412 },
2413 #endif
2414
2415 #if AGESA_ENTRY_INIT_S3SAVE == TRUE
2416 { AMD_S3_SAVE,
2417 sizeof (AMD_S3SAVE_PARAMS),
2418 (PF_AGESA_FUNCTION) AmdS3SaveInitializer,
2419 (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor,
2420 AMD_S3_SAVE_HANDLE
2421 },
2422 #endif
2423
2424 #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
2425 { AMD_LATE_RUN_AP_TASK,
2426 sizeof (AP_EXE_PARAMS),
2427 (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer,
2428 (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
2429 AMD_LATE_RUN_AP_TASK_HANDLE
2430 },
2431 #endif
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]2432 { 0, 0, NULL }
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]2433};
2434
2435CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0])));
2436
2437CONST DISPATCH_TABLE ROMDATA DispatchTable[] =
2438{
2439 { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct },
2440 { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct },
2441
2442 #if AGESA_ENTRY_INIT_RESET == TRUE
2443 { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset },
2444 #endif
2445
2446 #if AGESA_ENTRY_INIT_RECOVERY == TRUE
2447 { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery },
2448 #endif
2449
2450 #if AGESA_ENTRY_INIT_EARLY == TRUE
2451 { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly },
2452 #endif
2453
2454 #if AGESA_ENTRY_INIT_POST == TRUE
2455 { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost },
2456 #endif
2457
2458 #if AGESA_ENTRY_INIT_ENV == TRUE
2459 { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv },
2460 #endif
2461
2462 #if AGESA_ENTRY_INIT_MID == TRUE
2463 { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid },
2464 #endif
2465
2466 #if AGESA_ENTRY_INIT_LATE == TRUE
2467 { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate },
2468 #endif
2469
2470 #if AGESA_ENTRY_INIT_S3SAVE == TRUE
2471 { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save },
2472 #endif
2473
2474 #if AGESA_ENTRY_INIT_RESUME == TRUE
2475 { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume },
2476 #endif
2477
2478 #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
2479 { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore },
2480 #endif
2481
2482 #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
2483 { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId },
2484 { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress },
2485 { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore },
2486 { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog },
2487 { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm },
2488 { AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize },
2489 #endif
2490
2491 #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
2492 { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask },
2493 #endif
2494 { 0, NULL }
2495};
2496
2497CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] =
2498{
2499 IDS_LATE_RUN_AP_TASK
2500 // Get DMI info
2501 CPU_DMI_AP_GET_TYPE4_TYPE7
2502 // Probe filter enable
2503 HT_ASSIST_AP_DISABLE_CACHE
2504 HT_ASSIST_AP_ENABLE_CACHE
2505
2506 { 0, NULL }
2507};
2508
2509#if AGESA_ENTRY_INIT_RESET == TRUE
2510 #if IDSOPT_IDS_ENABLED == TRUE
2511 #if IDSOPT_TRACING_ENABLED == TRUE
2512 #define MAKE_DBG_STR(x, y) MAKE_AS_A_STRING(x : y)
2513 CONST CHAR8 *BldOptDebugOutput[] = {
2514 #if IDS_TRACE_SHOW_BLD_OPT_CFG == TRUE
2515 //Build Option Area
2516 MAKE_DBG_STR (\nOptUDIMM, OPTION_UDIMMS)
2517 MAKE_DBG_STR (\nOptRDIMM, OPTION_RDIMMS)
2518 MAKE_DBG_STR (\nOptLRDIMM, OPTION_LRDIMMS)
2519 MAKE_DBG_STR (\nOptECC, OPTION_ECC)
2520 MAKE_DBG_STR (\nOptCsIntlv, OPTION_BANK_INTERLEAVE)
2521 MAKE_DBG_STR (\nOptDctIntlv, OPTION_DCT_INTERLEAVE)
2522 MAKE_DBG_STR (\nOptNodeIntlv, OPTION_NODE_INTERLEAVE)
2523 //MAKE_DBG_STR (\nOptParallelTraining, OPTION_PARALLEL_TRAINING)
2524 MAKE_DBG_STR (\nOptOnlineSpare, OPTION_ONLINE_SPARE)
2525 MAKE_DBG_STR (\nOptAddr2CsTranslator, OPTION_ADDR_TO_CS_TRANSLATOR)
2526 MAKE_DBG_STR (\nOptMemRestore, OPTION_MEM_RESTORE)
2527 MAKE_DBG_STR (\nOptMultiSocket, OPTION_MULTISOCKET)
2528 MAKE_DBG_STR (\nOptPstates, OPTION_ACPI_PSTATES)
2529 MAKE_DBG_STR (\nOptSRAT, OPTION_SRAT)
2530 MAKE_DBG_STR (\nOptSLIT, OPTION_SLIT)
2531 MAKE_DBG_STR (\nOptWHEA, OPTION_WHEA)
2532 MAKE_DBG_STR (\nOptDMI, OPTION_DMI)
2533 MAKE_DBG_STR (\nOptEarlySamples, OPTION_EARLY_SAMPLES),
2534
2535 //Build Configuration Area
2536 // CoreVrm
2537 MAKE_DBG_STR (\nVrmCurrentLimit , CFG_VRM_CURRENT_LIMIT)
2538 MAKE_DBG_STR (\nVrmLowPowerThreshold , CFG_VRM_LOW_POWER_THRESHOLD)
2539 MAKE_DBG_STR (\nVrmSlewRate , CFG_VRM_SLEW_RATE)
2540 MAKE_DBG_STR (\nVrmAdditionalDelay , CFG_VRM_ADDITIONAL_DELAY)
2541 MAKE_DBG_STR (\nVrmHiSpeedEnable , CFG_VRM_HIGH_SPEED_ENABLE)
2542 MAKE_DBG_STR (\nVrmInrushCurrentLimit, CFG_VRM_INRUSH_CURRENT_LIMIT)
2543 // NbVrm
2544 MAKE_DBG_STR (\nNbVrmCurrentLimit , CFG_VRM_NB_CURRENT_LIMIT)
2545 MAKE_DBG_STR (\nNbVrmLowPowerThreshold , CFG_VRM_NB_LOW_POWER_THRESHOLD)
2546 MAKE_DBG_STR (\nNbVrmSlewRate , CFG_VRM_NB_SLEW_RATE)
2547 MAKE_DBG_STR (\nNbVrmAdditionalDelay , CFG_VRM_NB_ADDITIONAL_DELAY)
2548 MAKE_DBG_STR (\nNbVrmHiSpeedEnable , CFG_VRM_NB_HIGH_SPEED_ENABLE)
2549 MAKE_DBG_STR (\nNbVrmInrushCurrentLimit, CFG_VRM_NB_INRUSH_CURRENT_LIMIT),
2550
2551 MAKE_DBG_STR (\nNumIoApics , CFG_PLAT_NUM_IO_APICS)
2552 MAKE_DBG_STR (\nMemInitPstate , CFG_MEM_INIT_PSTATE)
2553 MAKE_DBG_STR (\nC1eMode , CFG_C1E_MODE)
2554 MAKE_DBG_STR (\nC1eOpData , CFG_C1E_OPDATA)
2555 MAKE_DBG_STR (\nC1eOpdata1 , CFG_C1E_OPDATA1)
2556 MAKE_DBG_STR (\nC1eOpdata2 , CFG_C1E_OPDATA2)
2557 MAKE_DBG_STR (\nCStateMode , CFG_CSTATE_MODE)
2558 MAKE_DBG_STR (\nCStateOpData , CFG_CSTATE_OPDATA)
2559 MAKE_DBG_STR (\nCStateIoBaseAddr , CFG_CSTATE_IO_BASE_ADDRESS)
2560 MAKE_DBG_STR (\nCpbMode , CFG_CPB_MODE)
2561 MAKE_DBG_STR (\nCoreLevelingMode , CFG_CORE_LEVELING_MODE),
2562
2563 MAKE_DBG_STR (\nControlFlowMode , CFG_PLATFORM_CONTROL_FLOW_MODE)
2564 MAKE_DBG_STR (\nUseHtAssist , CFG_USE_HT_ASSIST)
2565 MAKE_DBG_STR (\nUseAtmMode , CFG_USE_ATM_MODE)
2566 MAKE_DBG_STR (\nUse32ByteRefresh , CFG_USE_32_BYTE_REFRESH)
2567 MAKE_DBG_STR (\nUseVarMctIsocPriority , CFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
2568 MAKE_DBG_STR (\nPowerPolicy , CFG_PLATFORM_POWER_POLICY_MOD)
2569
2570 MAKE_DBG_STR (\nDeemphasisList , CFG_PLATFORM_DEEMPHASIS_LIST)
2571
2572 MAKE_DBG_STR (\nPciMmioAddr , CFG_PCI_MMIO_BASE)
2573 MAKE_DBG_STR (\nPciMmioSize , CFG_PCI_MMIO_SIZE)
2574 MAKE_DBG_STR (\nPlatformType , CFG_AMD_PLATFORM_TYPE)
2575 MAKE_DBG_STR (\nPstateCapValue , CFG_AMD_PSTATE_CAP_VALUE),
2576
2577 MAKE_DBG_STR (\nMemBusFreqLimit , CFG_MEMORY_BUS_FREQUENCY_LIMIT)
2578 MAKE_DBG_STR (\nTimingModeSelect , CFG_TIMING_MODE_SELECT)
2579 MAKE_DBG_STR (\nMemoryClockSelect , CFG_MEMORY_CLOCK_SELECT)
2580
2581 MAKE_DBG_STR (\nMemUnganged , CFG_MEMORY_MODE_UNGANGED)
2582 MAKE_DBG_STR (\nQRCap , CFG_MEMORY_QUAD_RANK_CAPABLE)
2583 MAKE_DBG_STR (\nQRType , CFG_MEMORY_QUADRANK_TYPE)
2584 MAKE_DBG_STR (\nRDimmCap , CFG_MEMORY_RDIMM_CAPABLE)
2585 MAKE_DBG_STR (\nLRDimmCap , CFG_MEMORY_LRDIMM_CAPABLE)
2586 MAKE_DBG_STR (\nUDimmCap , CFG_MEMORY_UDIMM_CAPABLE)
2587 MAKE_DBG_STR (\nSODimmCap , CFG_MEMORY_SODIMM_CAPABLE)
2588 MAKE_DBG_STR (\nDqsTrainingControl , CFG_DQS_TRAINING_CONTROL)
2589 MAKE_DBG_STR (\nIgnoreSpdChecksum , CFG_IGNORE_SPD_CHECKSUM)
2590 MAKE_DBG_STR (\nUseBurstMode , CFG_USE_BURST_MODE)
2591 MAKE_DBG_STR (\nAllMemClkOn , CFG_MEMORY_ALL_CLOCKS_ON),
2592
2593 MAKE_DBG_STR (\nPowerDownEn , CFG_MEMORY_POWER_DOWN)
2594 MAKE_DBG_STR (\nPowerDownMode , CFG_POWER_DOWN_MODE)
2595 MAKE_DBG_STR (\nOnlineSpare , CFG_ONLINE_SPARE)
2596 MAKE_DBG_STR (\nAddrParityEn , CFG_MEMORY_PARITY_ENABLE)
2597 MAKE_DBG_STR (\nBankSwizzle , CFG_BANK_SWIZZLE)
2598 MAKE_DBG_STR (\nCsIntlvEn , CFG_MEMORY_ENABLE_BANK_INTERLEAVING)
2599 MAKE_DBG_STR (\nNodeIntlvEn , CFG_MEMORY_ENABLE_NODE_INTERLEAVING)
2600 MAKE_DBG_STR (\nDctIntlvEn , CFG_MEMORY_CHANNEL_INTERLEAVING),
2601
2602 MAKE_DBG_STR (\nUmaMode , CFG_UMA_MODE)
2603 MAKE_DBG_STR (\nUmaSize , CFG_UMA_SIZE)
2604 MAKE_DBG_STR (\nUmaAbove4G , CFG_UMA_ABOVE4G)
2605 MAKE_DBG_STR (\nUmaAlignment , CFG_UMA_ALIGNMENT)
2606
2607 MAKE_DBG_STR (\nEccEn , CFG_ENABLE_ECC_FEATURE)
2608 MAKE_DBG_STR (\nEccRedirect , CFG_ECC_REDIRECTION)
2609 MAKE_DBG_STR (\nScrubDramRate , CFG_SCRUB_DRAM_RATE)
2610 MAKE_DBG_STR (\nScrubL2Rate , CFG_SCRUB_L2_RATE)
2611 MAKE_DBG_STR (\nScrubL3Rate , CFG_SCRUB_L3_RATE)
2612 MAKE_DBG_STR (\nScrubIcRate , CFG_SCRUB_IC_RATE)
2613 MAKE_DBG_STR (\nScrubDcRate , CFG_SCRUB_DC_RATE)
2614 MAKE_DBG_STR (\nEccSyncFlood , CFG_ECC_SYNC_FLOOD)
2615 MAKE_DBG_STR (\nEccSymbolSize , CFG_ECC_SYMBOL_SIZE)
2616 MAKE_DBG_STR (\nHeapDramAddress , CFG_HEAP_DRAM_ADDRESS)
2617 MAKE_DBG_STR (\nNodeMem1GBAlign , CFG_1GB_ALIGN),
2618
2619 MAKE_DBG_STR (\nS3LateRestore , CFG_S3_LATE_RESTORE)
2620 MAKE_DBG_STR (\nAcpiPstateIndependent , CFG_ACPI_PSTATE_PSD_INDPX)
2621
2622 MAKE_DBG_STR (\nApMtrrSettingsList , CFG_AP_MTRR_SETTINGS_LIST)
2623
2624 MAKE_DBG_STR (\nProcessorScopeInSb , CFG_PROCESSOR_SCOPE_IN_SB)
2625 MAKE_DBG_STR (\nProcessorScopeName0 , CFG_PROCESSOR_SCOPE_NAME0)
2626 MAKE_DBG_STR (\nProcessorScopeName1 , CFG_PROCESSOR_SCOPE_NAME1)
2627 MAKE_DBG_STR (\nGnbHdAudio , CFG_GNB_HD_AUDIO)
2628 MAKE_DBG_STR (\nAbmSupport , CFG_ABM_SUPPORT)
2629 MAKE_DBG_STR (\nDynamicRefreshRate , CFG_DYNAMIC_REFRESH_RATE)
2630 MAKE_DBG_STR (\nLcdBackLightControl , CFG_LCD_BACK_LIGHT_CONTROL)
2631 MAKE_DBG_STR (\nGnb3dStereoPinIndex , CFG_GNB_STEREO_3D_PINOUT)
2632 MAKE_DBG_STR (\nTempPcieMmioBaseAddress, CFG_TEMP_PCIE_MMIO_BASE_ADDRESS),
2633 MAKE_DBG_STR (\nCfgGnbIGPUSSID , CFG_GNB_IGPU_SSID),
2634 MAKE_DBG_STR (\nCfgGnbHDAudioSSID , CFG_GNB_HDAUDIO_SSID),
2635 MAKE_DBG_STR (\nCfgGnbPcieSSID , CFG_GNB_PCIE_SSID),
2636
2637 MAKE_DBG_STR (\nCfgLvdsSpreadSpectrum , CFG_GFX_LVDS_SPREAD_SPECTRUM),
2638 MAKE_DBG_STR (\nCfgLvdsSpreadSpectrumRate , CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE),
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]2639 MAKE_DBG_STR (\nCfgLvdsMiscControl.FpdiMode , CFG_LVDS_MISC_888_FPDI_MODE),
2640 MAKE_DBG_STR (\nCfgLvdsMiscControl.DlChSwap , CFG_LVDS_MISC_DL_CH_SWAP),
2641 MAKE_DBG_STR (\nCfgLvdsMiscControl.VsyncActiveLow , CFG_LVDS_MISC_VSYNC_ACTIVE_LOW),
2642 MAKE_DBG_STR (\nCfgLvdsMiscControl.HsyncActiveLow , CFG_LVDS_MISC_HSYNC_ACTIVE_LOW),
2643 MAKE_DBG_STR (\nCfgLvdsMiscControl.BLONActiveLow , CFG_LVDS_MISC_BLON_ACTIVE_LOW),
2644 MAKE_DBG_STR (\nCfgPcieRefClkSpreadSpectrum , CFG_PCIE_REFCLK_SPREAD_SPECTRUM),
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]2645 #endif
2646 NULL
2647 };
2648 #endif
2649 #endif
2650#endif