Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <console/usb.h> |
Elyes HAOUAS | c056729 | 2019-04-28 17:57:47 +0200 | [diff] [blame] | 5 | #include <cf9_reset.h> |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 6 | #include <string.h> |
Nico Huber | 47bf498 | 2019-11-17 02:58:00 +0100 | [diff] [blame] | 7 | #include <device/device.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 8 | #include <device/pci_ops.h> |
Patrick Rudolph | 5709e03 | 2019-03-25 10:12:14 +0100 | [diff] [blame] | 9 | #include <arch/cpu.h> |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 10 | #include <cbmem.h> |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 11 | #include <cbfs.h> |
| 12 | #include <ip_checksum.h> |
| 13 | #include <pc80/mc146818rtc.h> |
| 14 | #include <device/pci_def.h> |
Kyösti Mälkki | b697c90 | 2019-01-30 08:19:49 +0200 | [diff] [blame] | 15 | #include <lib.h> |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 16 | #include <mrc_cache.h> |
Elyes HAOUAS | 1d6484a | 2020-07-10 11:18:11 +0200 | [diff] [blame] | 17 | #include <stddef.h> |
| 18 | #include <stdint.h> |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 19 | #include <timestamp.h> |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 20 | #include "raminit.h" |
| 21 | #include "pei_data.h" |
| 22 | #include "sandybridge.h" |
Patrick Rudolph | 5709e03 | 2019-03-25 10:12:14 +0100 | [diff] [blame] | 23 | #include "chip.h" |
Philipp Deppenwiese | fea2429 | 2017-10-17 17:02:29 +0200 | [diff] [blame] | 24 | #include <security/vboot/vboot_common.h> |
Patrick Georgi | 27fbbcf | 2019-04-23 12:33:23 +0200 | [diff] [blame] | 25 | #include <southbridge/intel/bd82x6x/pch.h> |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 26 | |
| 27 | /* Management Engine is in the southbridge */ |
Elyes HAOUAS | 21b71ce6 | 2018-06-16 18:43:52 +0200 | [diff] [blame] | 28 | #include <southbridge/intel/bd82x6x/me.h> |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 29 | |
| 30 | /* |
| 31 | * MRC scrambler seed offsets should be reserved in |
| 32 | * mainboard cmos.layout and not covered by checksum. |
| 33 | */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 34 | #if CONFIG(USE_OPTION_TABLE) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 35 | #include "option_table.h" |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 36 | #define CMOS_OFFSET_MRC_SEED (CMOS_VSTART_mrc_scrambler_seed >> 3) |
| 37 | #define CMOS_OFFSET_MRC_SEED_S3 (CMOS_VSTART_mrc_scrambler_seed_s3 >> 3) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 38 | #define CMOS_OFFSET_MRC_SEED_CHK (CMOS_VSTART_mrc_scrambler_seed_chk >> 3) |
| 39 | #else |
| 40 | #define CMOS_OFFSET_MRC_SEED 152 |
| 41 | #define CMOS_OFFSET_MRC_SEED_S3 156 |
| 42 | #define CMOS_OFFSET_MRC_SEED_CHK 160 |
| 43 | #endif |
| 44 | |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 45 | #define MRC_CACHE_VERSION 0 |
| 46 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 47 | void save_mrc_data(struct pei_data *pei_data) |
| 48 | { |
| 49 | u16 c1, c2, checksum; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 50 | |
| 51 | /* Save the MRC S3 restore data to cbmem */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 52 | mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, pei_data->mrc_output, |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 53 | pei_data->mrc_output_len); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 54 | |
| 55 | /* Save the MRC seed values to CMOS */ |
Kyösti Mälkki | 2879107 | 2020-01-04 12:58:53 +0200 | [diff] [blame] | 56 | cmos_write32(pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 57 | printk(BIOS_DEBUG, "Save scrambler seed 0x%08x to CMOS 0x%02x\n", |
| 58 | pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); |
| 59 | |
Kyösti Mälkki | 2879107 | 2020-01-04 12:58:53 +0200 | [diff] [blame] | 60 | cmos_write32(pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 61 | printk(BIOS_DEBUG, "Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n", |
| 62 | pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); |
| 63 | |
| 64 | /* Save a simple checksum of the seed values */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 65 | c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed, sizeof(u32)); |
| 66 | c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3, sizeof(u32)); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 67 | checksum = add_ip_checksums(sizeof(u32), c1, c2); |
| 68 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 69 | cmos_write((checksum >> 0) & 0xff, CMOS_OFFSET_MRC_SEED_CHK); |
| 70 | cmos_write((checksum >> 8) & 0xff, CMOS_OFFSET_MRC_SEED_CHK + 1); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 71 | } |
| 72 | |
| 73 | static void prepare_mrc_cache(struct pei_data *pei_data) |
| 74 | { |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 75 | u16 c1, c2, checksum, seed_checksum; |
Shelley Chen | ad9cd68 | 2020-07-23 16:10:52 -0700 | [diff] [blame] | 76 | size_t mrc_size; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 77 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 78 | /* Preset just in case there is an error */ |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 79 | pei_data->mrc_input = NULL; |
| 80 | pei_data->mrc_input_len = 0; |
| 81 | |
| 82 | /* Read scrambler seeds from CMOS */ |
| 83 | pei_data->scrambler_seed = cmos_read32(CMOS_OFFSET_MRC_SEED); |
| 84 | printk(BIOS_DEBUG, "Read scrambler seed 0x%08x from CMOS 0x%02x\n", |
| 85 | pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); |
| 86 | |
| 87 | pei_data->scrambler_seed_s3 = cmos_read32(CMOS_OFFSET_MRC_SEED_S3); |
| 88 | printk(BIOS_DEBUG, "Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n", |
| 89 | pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); |
| 90 | |
| 91 | /* Compute seed checksum and compare */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 92 | c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed, sizeof(u32)); |
| 93 | c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3, sizeof(u32)); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 94 | checksum = add_ip_checksums(sizeof(u32), c1, c2); |
| 95 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 96 | seed_checksum = cmos_read(CMOS_OFFSET_MRC_SEED_CHK); |
| 97 | seed_checksum |= cmos_read(CMOS_OFFSET_MRC_SEED_CHK + 1) << 8; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 98 | |
| 99 | if (checksum != seed_checksum) { |
| 100 | printk(BIOS_ERR, "%s: invalid seed checksum\n", __func__); |
| 101 | pei_data->scrambler_seed = 0; |
| 102 | pei_data->scrambler_seed_s3 = 0; |
| 103 | return; |
| 104 | } |
| 105 | |
Shelley Chen | ad9cd68 | 2020-07-23 16:10:52 -0700 | [diff] [blame] | 106 | pei_data->mrc_input = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, |
| 107 | MRC_CACHE_VERSION, |
| 108 | &mrc_size); |
| 109 | if (pei_data->mrc_input == NULL) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 110 | /* Error message printed in find_current_mrc_cache */ |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 111 | return; |
| 112 | } |
| 113 | |
Shelley Chen | ad9cd68 | 2020-07-23 16:10:52 -0700 | [diff] [blame] | 114 | pei_data->mrc_input_len = mrc_size; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 115 | |
Shelley Chen | ad9cd68 | 2020-07-23 16:10:52 -0700 | [diff] [blame] | 116 | printk(BIOS_DEBUG, "%s: at %p, size %zx\n", __func__, |
| 117 | pei_data->mrc_input, mrc_size); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 118 | } |
| 119 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 120 | /** |
| 121 | * Find PEI executable in coreboot filesystem and execute it. |
| 122 | * |
| 123 | * @param pei_data: configuration data for UEFI PEI reference code |
| 124 | */ |
| 125 | void sdram_initialize(struct pei_data *pei_data) |
| 126 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 127 | int (*entry)(struct pei_data *pei_data) __attribute__((regparm(1))); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 128 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 129 | /* Wait for ME to be ready */ |
| 130 | intel_early_me_init(); |
| 131 | intel_early_me_uma_size(); |
| 132 | |
| 133 | printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n"); |
| 134 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 135 | /* |
Shelley Chen | 6615c6e | 2020-10-27 15:58:31 -0700 | [diff] [blame] | 136 | * Always pass in mrc_cache data. The driver will determine |
| 137 | * whether to use the data or not. |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 138 | */ |
Shelley Chen | 6615c6e | 2020-10-27 15:58:31 -0700 | [diff] [blame] | 139 | prepare_mrc_cache(pei_data); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 140 | |
| 141 | /* If MRC data is not found we cannot continue S3 resume. */ |
| 142 | if (pei_data->boot_mode == 2 && !pei_data->mrc_input) { |
Elyes HAOUAS | 3cd4327 | 2020-03-05 22:01:17 +0100 | [diff] [blame] | 143 | printk(BIOS_DEBUG, "Giving up in %s: No MRC data\n", __func__); |
Elyes HAOUAS | c056729 | 2019-04-28 17:57:47 +0200 | [diff] [blame] | 144 | system_reset(); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 145 | } |
| 146 | |
| 147 | /* Pass console handler in pei_data */ |
| 148 | pei_data->tx_byte = do_putchar; |
| 149 | |
| 150 | /* Locate and call UEFI System Agent binary. */ |
Julius Werner | 834b3ec | 2020-03-04 16:52:08 -0800 | [diff] [blame] | 151 | entry = cbfs_map("mrc.bin", NULL); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 152 | if (entry) { |
| 153 | int rv; |
| 154 | rv = entry (pei_data); |
| 155 | if (rv) { |
| 156 | switch (rv) { |
| 157 | case -1: |
| 158 | printk(BIOS_ERR, "PEI version mismatch.\n"); |
| 159 | break; |
| 160 | case -2: |
| 161 | printk(BIOS_ERR, "Invalid memory frequency.\n"); |
| 162 | break; |
| 163 | default: |
| 164 | printk(BIOS_ERR, "MRC returned %x.\n", rv); |
| 165 | } |
Keith Short | bb41aba | 2019-05-16 14:07:43 -0600 | [diff] [blame] | 166 | die_with_post_code(POST_INVALID_VENDOR_BINARY, |
| 167 | "Nonzero MRC return value.\n"); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 168 | } |
| 169 | } else { |
| 170 | die("UEFI PEI System Agent not found.\n"); |
| 171 | } |
| 172 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 173 | /* mrc.bin reconfigures USB, so reinit it to have debug */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 174 | if (CONFIG(USBDEBUG_IN_PRE_RAM)) |
Kyösti Mälkki | 63649d2 | 2018-12-29 09:40:40 +0200 | [diff] [blame] | 175 | usbdebug_hw_init(true); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 176 | |
Angel Pons | 9f3bc371 | 2020-10-13 23:57:10 +0200 | [diff] [blame] | 177 | /* Print the MRC version after executing the UEFI PEI stage */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 178 | u32 version = MCHBAR32(MRC_REVISION); |
Angel Pons | 9f3bc371 | 2020-10-13 23:57:10 +0200 | [diff] [blame] | 179 | printk(BIOS_DEBUG, "MRC Version %d.%d.%d Build %d\n", |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 180 | (version >> 24) & 0xff, (version >> 16) & 0xff, |
| 181 | (version >> 8) & 0xff, (version >> 0) & 0xff); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 182 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 183 | /* |
| 184 | * Send ME init done for SandyBridge here. |
| 185 | * This is done inside the SystemAgent binary on IvyBridge. |
| 186 | */ |
| 187 | if (BASE_REV_SNB == (pci_read_config16(PCI_CPU_DEVICE, PCI_DEVICE_ID) & BASE_REV_MASK)) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 188 | intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); |
| 189 | else |
| 190 | intel_early_me_status(); |
| 191 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 192 | report_memory_config(); |
| 193 | } |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 194 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 195 | /* |
| 196 | * These are the location and structure of MRC_VAR data in CAR. |
| 197 | * The CAR region looks like this: |
| 198 | * +------------------+ -> DCACHE_RAM_BASE |
| 199 | * | | |
| 200 | * | | |
| 201 | * | COREBOOT STACK | |
| 202 | * | | |
| 203 | * | | |
| 204 | * +------------------+ -> DCACHE_RAM_BASE + DCACHE_RAM_SIZE |
| 205 | * | | |
| 206 | * | MRC HEAP | |
| 207 | * | size = 0x5000 | |
| 208 | * | | |
| 209 | * +------------------+ |
| 210 | * | | |
| 211 | * | MRC VAR | |
| 212 | * | size = 0x4000 | |
| 213 | * | | |
| 214 | * +------------------+ -> DACHE_RAM_BASE + DACHE_RAM_SIZE |
| 215 | * + DCACHE_RAM_MRC_VAR_SIZE |
Arthur Heymans | 01c83a2 | 2019-06-05 13:36:55 +0200 | [diff] [blame] | 216 | */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 217 | #define DCACHE_RAM_MRC_VAR_BASE (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE \ |
| 218 | + CONFIG_DCACHE_RAM_MRC_VAR_SIZE - 0x4000) |
Kyösti Mälkki | b697c90 | 2019-01-30 08:19:49 +0200 | [diff] [blame] | 219 | |
| 220 | struct mrc_var_data { |
| 221 | u32 acpi_timer_flag; |
| 222 | u32 pool_used; |
| 223 | u32 pool_base; |
| 224 | u32 tx_byte; |
| 225 | u32 reserved[4]; |
| 226 | } __packed; |
| 227 | |
Patrick Rudolph | 5709e03 | 2019-03-25 10:12:14 +0100 | [diff] [blame] | 228 | static void northbridge_fill_pei_data(struct pei_data *pei_data) |
| 229 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 230 | pei_data->mchbar = (uintptr_t)DEFAULT_MCHBAR; |
| 231 | pei_data->dmibar = (uintptr_t)DEFAULT_DMIBAR; |
| 232 | pei_data->epbar = DEFAULT_EPBAR; |
| 233 | pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS; |
Patrick Rudolph | 5709e03 | 2019-03-25 10:12:14 +0100 | [diff] [blame] | 234 | pei_data->hpet_address = CONFIG_HPET_ADDRESS; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 235 | pei_data->thermalbase = 0xfed08000; |
| 236 | pei_data->system_type = !(get_platform_type() == PLATFORM_MOBILE); |
| 237 | pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE; |
Patrick Rudolph | 5709e03 | 2019-03-25 10:12:14 +0100 | [diff] [blame] | 238 | |
| 239 | if ((cpu_get_cpuid() & 0xffff0) == 0x306a0) { |
| 240 | const struct device *dev = pcidev_on_root(1, 0); |
| 241 | pei_data->pcie_init = dev && dev->enabled; |
| 242 | } else { |
| 243 | pei_data->pcie_init = 0; |
| 244 | } |
| 245 | } |
| 246 | |
| 247 | static void southbridge_fill_pei_data(struct pei_data *pei_data) |
| 248 | { |
| 249 | const struct device *dev = pcidev_on_root(0x19, 0); |
| 250 | |
Angel Pons | b21bffa | 2020-07-03 01:02:28 +0200 | [diff] [blame] | 251 | pei_data->smbusbar = CONFIG_FIXED_SMBUS_IO_BASE; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 252 | pei_data->wdbbar = 0x04000000; |
| 253 | pei_data->wdbsize = 0x1000; |
Angel Pons | 92717ff | 2020-09-14 16:22:22 +0200 | [diff] [blame] | 254 | pei_data->rcba = (uintptr_t)DEFAULT_RCBA; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 255 | pei_data->pmbase = DEFAULT_PMBASE; |
| 256 | pei_data->gpiobase = DEFAULT_GPIOBASE; |
Patrick Rudolph | 5709e03 | 2019-03-25 10:12:14 +0100 | [diff] [blame] | 257 | pei_data->gbe_enable = dev && dev->enabled; |
| 258 | } |
| 259 | |
| 260 | static void devicetree_fill_pei_data(struct pei_data *pei_data) |
| 261 | { |
| 262 | const struct northbridge_intel_sandybridge_config *cfg; |
| 263 | |
| 264 | const struct device *dev = pcidev_on_root(0, 0); |
| 265 | if (!dev || !dev->chip_info) |
| 266 | return; |
| 267 | |
| 268 | cfg = dev->chip_info; |
| 269 | |
| 270 | switch (cfg->max_mem_clock_mhz) { |
| 271 | /* MRC only supports fixed numbers of frequencies */ |
| 272 | default: |
| 273 | printk(BIOS_WARNING, "RAMINIT: Limiting DDR3 clock to 800 Mhz\n"); |
| 274 | /* fallthrough */ |
| 275 | case 400: |
| 276 | pei_data->max_ddr3_freq = 800; |
| 277 | break; |
| 278 | case 533: |
| 279 | pei_data->max_ddr3_freq = 1066; |
| 280 | break; |
| 281 | case 666: |
| 282 | pei_data->max_ddr3_freq = 1333; |
| 283 | break; |
| 284 | case 800: |
| 285 | pei_data->max_ddr3_freq = 1600; |
| 286 | break; |
| 287 | |
| 288 | } |
| 289 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 290 | memcpy(pei_data->spd_addresses, cfg->spd_addresses, sizeof(pei_data->spd_addresses)); |
| 291 | memcpy(pei_data->ts_addresses, cfg->ts_addresses, sizeof(pei_data->ts_addresses)); |
Patrick Rudolph | 5709e03 | 2019-03-25 10:12:14 +0100 | [diff] [blame] | 292 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 293 | pei_data->ec_present = cfg->ec_present; |
Patrick Rudolph | 5709e03 | 2019-03-25 10:12:14 +0100 | [diff] [blame] | 294 | pei_data->ddr3lv_support = cfg->ddr3lv_support; |
| 295 | |
| 296 | pei_data->nmode = cfg->nmode; |
| 297 | pei_data->ddr_refresh_rate_config = cfg->ddr_refresh_rate_config; |
| 298 | |
| 299 | memcpy(pei_data->usb_port_config, cfg->usb_port_config, |
| 300 | sizeof(pei_data->usb_port_config)); |
| 301 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 302 | pei_data->usb3.mode = cfg->usb3.mode; |
Patrick Rudolph | 5709e03 | 2019-03-25 10:12:14 +0100 | [diff] [blame] | 303 | pei_data->usb3.hs_port_switch_mask = cfg->usb3.hs_port_switch_mask; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 304 | pei_data->usb3.preboot_support = cfg->usb3.preboot_support; |
| 305 | pei_data->usb3.xhci_streams = cfg->usb3.xhci_streams; |
Patrick Rudolph | 5709e03 | 2019-03-25 10:12:14 +0100 | [diff] [blame] | 306 | } |
| 307 | |
Nico Huber | 47bf498 | 2019-11-17 02:58:00 +0100 | [diff] [blame] | 308 | static void disable_p2p(void) |
| 309 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 310 | /* Disable PCI-to-PCI bridge early to prevent probing by MRC */ |
Nico Huber | 47bf498 | 2019-11-17 02:58:00 +0100 | [diff] [blame] | 311 | const struct device *const p2p = pcidev_on_root(0x1e, 0); |
| 312 | if (p2p && p2p->enabled) |
| 313 | return; |
| 314 | |
| 315 | RCBA32(FD) |= PCH_DISABLE_P2P; |
| 316 | } |
| 317 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 318 | void perform_raminit(int s3resume) |
| 319 | { |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 320 | struct pei_data pei_data; |
Kyösti Mälkki | b697c90 | 2019-01-30 08:19:49 +0200 | [diff] [blame] | 321 | struct mrc_var_data *mrc_var; |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 322 | |
| 323 | /* Prepare USB controller early in S3 resume */ |
| 324 | if (!mainboard_should_reset_usb(s3resume)) |
| 325 | enable_usb_bar(); |
| 326 | |
Patrick Rudolph | 5709e03 | 2019-03-25 10:12:14 +0100 | [diff] [blame] | 327 | memset(&pei_data, 0, sizeof(pei_data)); |
| 328 | pei_data.pei_version = PEI_VERSION, |
| 329 | |
| 330 | northbridge_fill_pei_data(&pei_data); |
| 331 | southbridge_fill_pei_data(&pei_data); |
| 332 | devicetree_fill_pei_data(&pei_data); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 333 | mainboard_fill_pei_data(&pei_data); |
| 334 | |
| 335 | post_code(0x3a); |
Patrick Rudolph | 59b4255 | 2019-05-08 12:44:15 +0200 | [diff] [blame] | 336 | |
Patrick Rudolph | 5709e03 | 2019-03-25 10:12:14 +0100 | [diff] [blame] | 337 | /* Fill after mainboard_fill_pei_data as it might provide spd_data */ |
| 338 | pei_data.dimm_channel0_disabled = |
| 339 | (!pei_data.spd_addresses[0] && !pei_data.spd_data[0][0]) + |
| 340 | (!pei_data.spd_addresses[1] && !pei_data.spd_data[1][0]) * 2; |
| 341 | |
| 342 | pei_data.dimm_channel1_disabled = |
| 343 | (!pei_data.spd_addresses[2] && !pei_data.spd_data[2][0]) + |
| 344 | (!pei_data.spd_addresses[3] && !pei_data.spd_data[3][0]) * 2; |
| 345 | |
Patrick Rudolph | 59b4255 | 2019-05-08 12:44:15 +0200 | [diff] [blame] | 346 | /* Fix spd_data. MRC only uses spd_data[0] and ignores the other */ |
| 347 | for (size_t i = 1; i < ARRAY_SIZE(pei_data.spd_data); i++) { |
| 348 | if (pei_data.spd_data[i][0] && !pei_data.spd_data[0][0]) { |
| 349 | memcpy(pei_data.spd_data[0], pei_data.spd_data[i], |
| 350 | sizeof(pei_data.spd_data[0])); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 351 | |
Patrick Rudolph | 59b4255 | 2019-05-08 12:44:15 +0200 | [diff] [blame] | 352 | } else if (pei_data.spd_data[i][0] && pei_data.spd_data[0][0]) { |
| 353 | if (memcmp(pei_data.spd_data[i], pei_data.spd_data[0], |
| 354 | sizeof(pei_data.spd_data[0])) != 0) |
| 355 | die("Onboard SPDs must match each other"); |
| 356 | } |
| 357 | } |
| 358 | |
Nico Huber | 47bf498 | 2019-11-17 02:58:00 +0100 | [diff] [blame] | 359 | disable_p2p(); |
| 360 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 361 | pei_data.boot_mode = s3resume ? 2 : 0; |
| 362 | timestamp_add_now(TS_BEFORE_INITRAM); |
| 363 | sdram_initialize(&pei_data); |
Kyösti Mälkki | b697c90 | 2019-01-30 08:19:49 +0200 | [diff] [blame] | 364 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 365 | /* Sanity check mrc_var location by verifying a known field */ |
Kyösti Mälkki | b697c90 | 2019-01-30 08:19:49 +0200 | [diff] [blame] | 366 | mrc_var = (void *)DCACHE_RAM_MRC_VAR_BASE; |
Kyösti Mälkki | b697c90 | 2019-01-30 08:19:49 +0200 | [diff] [blame] | 367 | if (mrc_var->tx_byte == (uintptr_t)pei_data.tx_byte) { |
| 368 | printk(BIOS_DEBUG, "MRC_VAR pool occupied [%08x,%08x]\n", |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 369 | mrc_var->pool_base, mrc_var->pool_base + mrc_var->pool_used); |
| 370 | |
Kyösti Mälkki | b697c90 | 2019-01-30 08:19:49 +0200 | [diff] [blame] | 371 | } else { |
| 372 | printk(BIOS_ERR, "Could not parse MRC_VAR data\n"); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 373 | hexdump32(BIOS_ERR, mrc_var, sizeof(*mrc_var) / sizeof(u32)); |
Kyösti Mälkki | b697c90 | 2019-01-30 08:19:49 +0200 | [diff] [blame] | 374 | } |
| 375 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 376 | const int cbmem_was_initted = !cbmem_recovery(s3resume); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 377 | if (!s3resume) |
| 378 | save_mrc_data(&pei_data); |
| 379 | |
| 380 | if (s3resume && !cbmem_was_initted) { |
| 381 | /* Failed S3 resume, reset to come up cleanly */ |
Elyes HAOUAS | c056729 | 2019-04-28 17:57:47 +0200 | [diff] [blame] | 382 | system_reset(); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 383 | } |
| 384 | } |