Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Krystian Hebel | 0d2dbca | 2019-04-23 19:28:16 +0200 | [diff] [blame] | 2 | |
Kyösti Mälkki | 2446c1e | 2020-07-09 07:13:37 +0300 | [diff] [blame] | 3 | #include <amdblocks/biosram.h> |
| 4 | |
Krystian Hebel | 0d2dbca | 2019-04-23 19:28:16 +0200 | [diff] [blame] | 5 | #include "Porting.h" |
| 6 | #include "AGESA.h" |
| 7 | |
Michał Żygowski | 7c07110 | 2019-12-20 17:18:42 +0100 | [diff] [blame] | 8 | #include <device/device.h> |
Krystian Hebel | 0d2dbca | 2019-04-23 19:28:16 +0200 | [diff] [blame] | 9 | #include <northbridge/amd/agesa/state_machine.h> |
| 10 | #include <northbridge/amd/agesa/agesa_helper.h> |
Angel Pons | ec5cf15 | 2020-11-10 20:42:07 +0100 | [diff] [blame] | 11 | #include <northbridge/amd/nb_common.h> |
Krystian Hebel | 0d2dbca | 2019-04-23 19:28:16 +0200 | [diff] [blame] | 12 | |
| 13 | void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) |
| 14 | { |
| 15 | } |
| 16 | |
| 17 | void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) |
| 18 | { |
Michał Żygowski | 7c07110 | 2019-12-20 17:18:42 +0100 | [diff] [blame] | 19 | Early->GnbConfig.PsppPolicy = PsppDisabled; |
Krystian Hebel | 0d2dbca | 2019-04-23 19:28:16 +0200 | [diff] [blame] | 20 | } |
| 21 | |
| 22 | void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) |
| 23 | { |
Michał Żygowski | 7c07110 | 2019-12-20 17:18:42 +0100 | [diff] [blame] | 24 | Post->MemConfig.UmaMode = CONFIG(GFXUMA) ? UMA_AUTO : UMA_NONE; |
| 25 | Post->MemConfig.UmaSize = 0; |
| 26 | Post->MemConfig.BottomIo = (UINT16)(CONFIG_BOTTOMIO_POSITION >> 24); |
Krystian Hebel | 0d2dbca | 2019-04-23 19:28:16 +0200 | [diff] [blame] | 27 | } |
| 28 | |
| 29 | void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) |
| 30 | { |
| 31 | /* If UMA is enabled we currently have it below TOP_MEM as well. |
| 32 | * UMA may or may not be cacheable, so Sub4GCacheTop could be |
| 33 | * higher than UmaBase. With UMA_NONE we see UmaBase==0. */ |
| 34 | if (Post->MemConfig.UmaBase) |
| 35 | backup_top_of_low_cacheable(Post->MemConfig.UmaBase << 16); |
| 36 | else |
| 37 | backup_top_of_low_cacheable(Post->MemConfig.Sub4GCacheTop); |
| 38 | } |
| 39 | |
Krystian Hebel | 0d2dbca | 2019-04-23 19:28:16 +0200 | [diff] [blame] | 40 | void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) |
| 41 | { |
| 42 | EmptyHeap(); |
| 43 | } |
| 44 | |
| 45 | void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) |
| 46 | { |
| 47 | } |
| 48 | |
| 49 | void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) |
| 50 | { |
| 51 | amd_initcpuio(); |
Michał Żygowski | 7c07110 | 2019-12-20 17:18:42 +0100 | [diff] [blame] | 52 | |
| 53 | /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ |
| 54 | Mid->GnbMidConfiguration.iGpuVgaMode = 0; |
Michał Żygowski | 3fbd2af | 2020-03-19 15:39:12 +0100 | [diff] [blame] | 55 | Mid->GnbMidConfiguration.GnbIoapicAddress = IO_APIC2_ADDR; |
Krystian Hebel | 0d2dbca | 2019-04-23 19:28:16 +0200 | [diff] [blame] | 56 | } |
| 57 | |
Michał Żygowski | 506b9c1 | 2019-12-20 16:57:13 +0100 | [diff] [blame] | 58 | void platform_BeforeInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) |
Krystian Hebel | 0d2dbca | 2019-04-23 19:28:16 +0200 | [diff] [blame] | 59 | { |
Michał Żygowski | 7c07110 | 2019-12-20 17:18:42 +0100 | [diff] [blame] | 60 | const struct device *iommu_dev = pcidev_on_root(0, 2); |
| 61 | |
| 62 | if (iommu_dev && iommu_dev->enabled) { |
| 63 | /* According to AGESA headers these must be set to sane values |
| 64 | * when IOMMU build config is enabled otherwise AGESA will skip |
| 65 | * it during IOMMU init and IVRS generation. |
| 66 | */ |
| 67 | Late->GnbLateConfiguration.GnbIoapicId = CONFIG_MAX_CPUS + 1; |
| 68 | Late->GnbLateConfiguration.FchIoapicId = CONFIG_MAX_CPUS; |
| 69 | } |
| 70 | |
| 71 | /* Code for creating CDIT requires hop count table. If it is not |
| 72 | * present AGESA_ERROR is returned, which confuses users. CDIT is not |
| 73 | * written to the ACPI tables anyway. */ |
| 74 | Late->PlatformConfig.UserOptionCdit = 0; |
Krystian Hebel | 0d2dbca | 2019-04-23 19:28:16 +0200 | [diff] [blame] | 75 | } |
| 76 | |
Michał Żygowski | 506b9c1 | 2019-12-20 16:57:13 +0100 | [diff] [blame] | 77 | void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) |
| 78 | { |
| 79 | } |
Krystian Hebel | 0d2dbca | 2019-04-23 19:28:16 +0200 | [diff] [blame] | 80 | |
| 81 | void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) |
| 82 | { |
| 83 | } |
| 84 | |
| 85 | void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) |
| 86 | { |
| 87 | } |
| 88 | |
| 89 | void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) |
| 90 | { |
| 91 | } |
| 92 | |
| 93 | void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) |
| 94 | { |
| 95 | amd_initcpuio(); |
| 96 | } |
| 97 | |
| 98 | void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save) |
| 99 | { |
| 100 | } |