Krystian Hebel | 0d2dbca | 2019-04-23 19:28:16 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2016 Kyösti Mälkki |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include "Porting.h" |
| 17 | #include "AGESA.h" |
| 18 | |
| 19 | #include <cbmem.h> |
| 20 | #include <northbridge/amd/agesa/state_machine.h> |
| 21 | #include <northbridge/amd/agesa/agesa_helper.h> |
| 22 | |
| 23 | void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) |
| 24 | { |
| 25 | } |
| 26 | |
| 27 | void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) |
| 28 | { |
| 29 | } |
| 30 | |
| 31 | void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) |
| 32 | { |
| 33 | } |
| 34 | |
| 35 | void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) |
| 36 | { |
| 37 | /* If UMA is enabled we currently have it below TOP_MEM as well. |
| 38 | * UMA may or may not be cacheable, so Sub4GCacheTop could be |
| 39 | * higher than UmaBase. With UMA_NONE we see UmaBase==0. */ |
| 40 | if (Post->MemConfig.UmaBase) |
| 41 | backup_top_of_low_cacheable(Post->MemConfig.UmaBase << 16); |
| 42 | else |
| 43 | backup_top_of_low_cacheable(Post->MemConfig.Sub4GCacheTop); |
| 44 | } |
| 45 | |
| 46 | |
| 47 | void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) |
| 48 | { |
| 49 | EmptyHeap(); |
| 50 | } |
| 51 | |
| 52 | void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) |
| 53 | { |
| 54 | } |
| 55 | |
| 56 | void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) |
| 57 | { |
| 58 | amd_initcpuio(); |
| 59 | } |
| 60 | |
| 61 | void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) |
| 62 | { |
| 63 | } |
| 64 | |
| 65 | |
| 66 | |
| 67 | void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) |
| 68 | { |
| 69 | } |
| 70 | |
| 71 | void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) |
| 72 | { |
| 73 | } |
| 74 | |
| 75 | void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) |
| 76 | { |
| 77 | } |
| 78 | |
| 79 | void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) |
| 80 | { |
| 81 | amd_initcpuio(); |
| 82 | } |
| 83 | |
| 84 | void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save) |
| 85 | { |
| 86 | } |