Krystian Hebel | 0d2dbca | 2019-04-23 19:28:16 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Krystian Hebel | 0d2dbca | 2019-04-23 19:28:16 +0200 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; version 2 of the License. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | */ |
| 14 | |
| 15 | #include "Porting.h" |
| 16 | #include "AGESA.h" |
| 17 | |
| 18 | #include <cbmem.h> |
Michał Żygowski | 7c07110 | 2019-12-20 17:18:42 +0100 | [diff] [blame] | 19 | #include <device/device.h> |
Krystian Hebel | 0d2dbca | 2019-04-23 19:28:16 +0200 | [diff] [blame] | 20 | #include <northbridge/amd/agesa/state_machine.h> |
| 21 | #include <northbridge/amd/agesa/agesa_helper.h> |
Michał Żygowski | 3fbd2af | 2020-03-19 15:39:12 +0100 | [diff] [blame^] | 22 | #include <northbridge/amd/pi/nb_common.h> |
Krystian Hebel | 0d2dbca | 2019-04-23 19:28:16 +0200 | [diff] [blame] | 23 | |
| 24 | void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) |
| 25 | { |
| 26 | } |
| 27 | |
| 28 | void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) |
| 29 | { |
Michał Żygowski | 7c07110 | 2019-12-20 17:18:42 +0100 | [diff] [blame] | 30 | Early->GnbConfig.PsppPolicy = PsppDisabled; |
Krystian Hebel | 0d2dbca | 2019-04-23 19:28:16 +0200 | [diff] [blame] | 31 | } |
| 32 | |
| 33 | void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) |
| 34 | { |
Michał Żygowski | 7c07110 | 2019-12-20 17:18:42 +0100 | [diff] [blame] | 35 | Post->MemConfig.UmaMode = CONFIG(GFXUMA) ? UMA_AUTO : UMA_NONE; |
| 36 | Post->MemConfig.UmaSize = 0; |
| 37 | Post->MemConfig.BottomIo = (UINT16)(CONFIG_BOTTOMIO_POSITION >> 24); |
Krystian Hebel | 0d2dbca | 2019-04-23 19:28:16 +0200 | [diff] [blame] | 38 | } |
| 39 | |
| 40 | void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) |
| 41 | { |
| 42 | /* If UMA is enabled we currently have it below TOP_MEM as well. |
| 43 | * UMA may or may not be cacheable, so Sub4GCacheTop could be |
| 44 | * higher than UmaBase. With UMA_NONE we see UmaBase==0. */ |
| 45 | if (Post->MemConfig.UmaBase) |
| 46 | backup_top_of_low_cacheable(Post->MemConfig.UmaBase << 16); |
| 47 | else |
| 48 | backup_top_of_low_cacheable(Post->MemConfig.Sub4GCacheTop); |
| 49 | } |
| 50 | |
| 51 | |
| 52 | void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) |
| 53 | { |
| 54 | EmptyHeap(); |
| 55 | } |
| 56 | |
| 57 | void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) |
| 58 | { |
| 59 | } |
| 60 | |
| 61 | void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) |
| 62 | { |
| 63 | amd_initcpuio(); |
Michał Żygowski | 7c07110 | 2019-12-20 17:18:42 +0100 | [diff] [blame] | 64 | |
| 65 | /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ |
| 66 | Mid->GnbMidConfiguration.iGpuVgaMode = 0; |
Michał Żygowski | 3fbd2af | 2020-03-19 15:39:12 +0100 | [diff] [blame^] | 67 | Mid->GnbMidConfiguration.GnbIoapicAddress = IO_APIC2_ADDR; |
Krystian Hebel | 0d2dbca | 2019-04-23 19:28:16 +0200 | [diff] [blame] | 68 | } |
| 69 | |
Michał Żygowski | 506b9c1 | 2019-12-20 16:57:13 +0100 | [diff] [blame] | 70 | void platform_BeforeInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) |
Krystian Hebel | 0d2dbca | 2019-04-23 19:28:16 +0200 | [diff] [blame] | 71 | { |
Michał Żygowski | 7c07110 | 2019-12-20 17:18:42 +0100 | [diff] [blame] | 72 | const struct device *iommu_dev = pcidev_on_root(0, 2); |
| 73 | |
| 74 | if (iommu_dev && iommu_dev->enabled) { |
| 75 | /* According to AGESA headers these must be set to sane values |
| 76 | * when IOMMU build config is enabled otherwise AGESA will skip |
| 77 | * it during IOMMU init and IVRS generation. |
| 78 | */ |
| 79 | Late->GnbLateConfiguration.GnbIoapicId = CONFIG_MAX_CPUS + 1; |
| 80 | Late->GnbLateConfiguration.FchIoapicId = CONFIG_MAX_CPUS; |
| 81 | } |
| 82 | |
| 83 | /* Code for creating CDIT requires hop count table. If it is not |
| 84 | * present AGESA_ERROR is returned, which confuses users. CDIT is not |
| 85 | * written to the ACPI tables anyway. */ |
| 86 | Late->PlatformConfig.UserOptionCdit = 0; |
Krystian Hebel | 0d2dbca | 2019-04-23 19:28:16 +0200 | [diff] [blame] | 87 | } |
| 88 | |
Michał Żygowski | 506b9c1 | 2019-12-20 16:57:13 +0100 | [diff] [blame] | 89 | void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) |
| 90 | { |
| 91 | } |
Krystian Hebel | 0d2dbca | 2019-04-23 19:28:16 +0200 | [diff] [blame] | 92 | |
| 93 | void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) |
| 94 | { |
| 95 | } |
| 96 | |
| 97 | void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) |
| 98 | { |
| 99 | } |
| 100 | |
| 101 | void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) |
| 102 | { |
| 103 | } |
| 104 | |
| 105 | void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) |
| 106 | { |
| 107 | amd_initcpuio(); |
| 108 | } |
| 109 | |
| 110 | void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save) |
| 111 | { |
| 112 | } |