Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 4 | #include <commonlib/region.h> |
Elyes HAOUAS | c056729 | 2019-04-28 17:57:47 +0200 | [diff] [blame] | 5 | #include <cf9_reset.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 6 | #include <string.h> |
Subrata Banik | 53b08c3 | 2018-12-10 14:11:35 +0530 | [diff] [blame] | 7 | #include <arch/cpu.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 8 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 9 | #include <device/pci_ops.h> |
Kyösti Mälkki | 1cae454 | 2020-01-06 12:31:34 +0200 | [diff] [blame] | 10 | #include <device/smbus_host.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 11 | #include <cbmem.h> |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 12 | #include <timestamp.h> |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 13 | #include <mrc_cache.h> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 14 | #include <southbridge/intel/bd82x6x/me.h> |
Patrick Rudolph | da9302a | 2019-03-24 17:01:41 +0100 | [diff] [blame] | 15 | #include <southbridge/intel/bd82x6x/pch.h> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 16 | #include <cpu/x86/msr.h> |
Elyes HAOUAS | 51401c3 | 2019-05-15 21:09:30 +0200 | [diff] [blame] | 17 | #include <types.h> |
Elyes HAOUAS | bf0970e | 2019-03-21 11:10:03 +0100 | [diff] [blame] | 18 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 19 | #include "raminit_native.h" |
| 20 | #include "raminit_common.h" |
| 21 | #include "sandybridge.h" |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 22 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 23 | /* FIXME: no ECC support */ |
| 24 | /* FIXME: no support for 3-channel chipsets */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 25 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 26 | static void wait_txt_clear(void) |
| 27 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 28 | struct cpuid_result cp = cpuid_ext(1, 0); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 29 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 30 | /* Check if TXT is supported */ |
| 31 | if (!(cp.ecx & (1 << 6))) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 32 | return; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 33 | |
| 34 | /* Some TXT public bit */ |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 35 | if (!(read32((void *)0xfed30010) & 1)) |
| 36 | return; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 37 | |
| 38 | /* Wait for TXT clear */ |
| 39 | while (!(read8((void *)0xfed40000) & (1 << 7))) |
| 40 | ; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 41 | } |
| 42 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 43 | /* Disable a channel in ramctr_timing */ |
| 44 | static void disable_channel(ramctr_timing *ctrl, int channel) |
| 45 | { |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 46 | ctrl->rankmap[channel] = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 47 | |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 48 | memset(&ctrl->rank_mirror[channel][0], 0, sizeof(ctrl->rank_mirror[0])); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 49 | |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 50 | ctrl->channel_size_mb[channel] = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 51 | ctrl->cmd_stretch[channel] = 0; |
| 52 | ctrl->mad_dimm[channel] = 0; |
| 53 | memset(&ctrl->timings[channel][0], 0, sizeof(ctrl->timings[0])); |
Patrick Rudolph | 74163d6 | 2016-11-17 20:02:43 +0100 | [diff] [blame] | 54 | memset(&ctrl->info.dimm[channel][0], 0, sizeof(ctrl->info.dimm[0])); |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 55 | } |
| 56 | |
Patrick Rudolph | 42609d8 | 2020-07-27 16:23:36 +0200 | [diff] [blame] | 57 | static bool nb_supports_ecc(const uint32_t capid0_a) |
| 58 | { |
| 59 | return !(capid0_a & CAPID_ECCDIS); |
| 60 | } |
| 61 | |
| 62 | static uint16_t nb_slots_per_channel(const uint32_t capid0_a) |
| 63 | { |
| 64 | return !(capid0_a & CAPID_DDPCD) + 1; |
| 65 | } |
| 66 | |
| 67 | static uint16_t nb_number_of_channels(const uint32_t capid0_a) |
| 68 | { |
| 69 | return !(capid0_a & CAPID_PDCD) + 1; |
| 70 | } |
| 71 | |
| 72 | static uint32_t nb_max_chan_capacity_mib(const uint32_t capid0_a) |
| 73 | { |
| 74 | uint32_t ddrsz; |
| 75 | |
| 76 | /* Values from documentation, which assume two DIMMs per channel */ |
| 77 | switch (CAPID_DDRSZ(capid0_a)) { |
| 78 | case 1: |
| 79 | ddrsz = 8192; |
| 80 | break; |
| 81 | case 2: |
| 82 | ddrsz = 2048; |
| 83 | break; |
| 84 | case 3: |
| 85 | ddrsz = 512; |
| 86 | break; |
| 87 | default: |
| 88 | ddrsz = 16384; |
| 89 | break; |
| 90 | } |
| 91 | |
| 92 | /* Account for the maximum number of DIMMs per channel */ |
| 93 | return (ddrsz / 2) * nb_slots_per_channel(capid0_a); |
| 94 | } |
| 95 | |
| 96 | /* Fill cbmem with information for SMBIOS type 16 and type 17 */ |
| 97 | static void setup_sdram_meminfo(ramctr_timing *ctrl) |
Patrick Rudolph | b97009e | 2016-02-28 15:24:04 +0100 | [diff] [blame] | 98 | { |
Patrick Rudolph | b97009e | 2016-02-28 15:24:04 +0100 | [diff] [blame] | 99 | int channel, slot; |
Patrick Rudolph | 24efe73 | 2018-08-19 11:06:06 +0200 | [diff] [blame] | 100 | const u16 ddr_freq = (1000 << 8) / ctrl->tCK; |
Patrick Rudolph | b97009e | 2016-02-28 15:24:04 +0100 | [diff] [blame] | 101 | |
Elyes HAOUAS | 12df950 | 2016-08-23 21:29:48 +0200 | [diff] [blame] | 102 | FOR_ALL_CHANNELS for (slot = 0; slot < NUM_SLOTS; slot++) { |
Patrick Rudolph | 24efe73 | 2018-08-19 11:06:06 +0200 | [diff] [blame] | 103 | enum cb_err ret = spd_add_smbios17(channel, slot, ddr_freq, |
| 104 | &ctrl->info.dimm[channel][slot]); |
| 105 | if (ret != CB_SUCCESS) |
| 106 | printk(BIOS_ERR, "RAMINIT: Failed to add SMBIOS17\n"); |
Patrick Rudolph | b97009e | 2016-02-28 15:24:04 +0100 | [diff] [blame] | 107 | } |
Patrick Rudolph | 42609d8 | 2020-07-27 16:23:36 +0200 | [diff] [blame] | 108 | |
| 109 | /* The 'spd_add_smbios17' function allocates this CBMEM area */ |
| 110 | struct memory_info *m = cbmem_find(CBMEM_ID_MEMINFO); |
| 111 | if (m == NULL) |
| 112 | return; |
| 113 | |
| 114 | const uint32_t capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); |
| 115 | |
| 116 | const uint16_t channels = nb_number_of_channels(capid0_a); |
| 117 | |
| 118 | m->ecc_capable = nb_supports_ecc(capid0_a); |
| 119 | m->max_capacity_mib = channels * nb_max_chan_capacity_mib(capid0_a); |
| 120 | m->number_of_devices = channels * nb_slots_per_channel(capid0_a); |
Patrick Rudolph | b97009e | 2016-02-28 15:24:04 +0100 | [diff] [blame] | 121 | } |
| 122 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 123 | /* Return CRC16 match for all SPDs */ |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 124 | static int verify_crc16_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) |
| 125 | { |
| 126 | int channel, slot, spd_slot; |
| 127 | int match = 1; |
| 128 | |
| 129 | FOR_ALL_CHANNELS { |
| 130 | for (slot = 0; slot < NUM_SLOTS; slot++) { |
| 131 | spd_slot = 2 * channel + slot; |
| 132 | match &= ctrl->spd_crc[channel][slot] == |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 133 | spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data)); |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 134 | } |
| 135 | } |
| 136 | return match; |
| 137 | } |
| 138 | |
Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 139 | void read_spd(spd_raw_data * spd, u8 addr, bool id_only) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 140 | { |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 141 | int j; |
Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 142 | if (id_only) { |
| 143 | for (j = 117; j < 128; j++) |
Kyösti Mälkki | 1a1b04e | 2020-01-07 22:34:33 +0200 | [diff] [blame] | 144 | (*spd)[j] = smbus_read_byte(addr, j); |
Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 145 | } else { |
| 146 | for (j = 0; j < 256; j++) |
Kyösti Mälkki | 1a1b04e | 2020-01-07 22:34:33 +0200 | [diff] [blame] | 147 | (*spd)[j] = smbus_read_byte(addr, j); |
Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 148 | } |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 149 | } |
| 150 | |
Patrick Rudolph | 735ecce | 2016-03-26 10:42:27 +0100 | [diff] [blame] | 151 | static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 152 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 153 | int dimms = 0, ch_dimms; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 154 | int channel, slot, spd_slot; |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 155 | bool can_use_ecc = ctrl->ecc_supported; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 156 | |
Elyes HAOUAS | 0d4b11a | 2016-10-03 21:57:21 +0200 | [diff] [blame] | 157 | memset (ctrl->rankmap, 0, sizeof(ctrl->rankmap)); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 158 | |
| 159 | ctrl->extended_temperature_range = 1; |
| 160 | ctrl->auto_self_refresh = 1; |
| 161 | |
| 162 | FOR_ALL_CHANNELS { |
| 163 | ctrl->channel_size_mb[channel] = 0; |
| 164 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 165 | ch_dimms = 0; |
| 166 | /* Count dimms on channel */ |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 167 | for (slot = 0; slot < NUM_SLOTS; slot++) { |
| 168 | spd_slot = 2 * channel + slot; |
Patrick Rudolph | 5a06185 | 2017-09-22 15:19:26 +0200 | [diff] [blame] | 169 | |
Angel Pons | 035096c | 2020-09-17 22:31:19 +0200 | [diff] [blame] | 170 | if (spd[spd_slot][SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR3) |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 171 | ch_dimms++; |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 172 | } |
| 173 | |
| 174 | for (slot = 0; slot < NUM_SLOTS; slot++) { |
| 175 | spd_slot = 2 * channel + slot; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 176 | printk(BIOS_DEBUG, "SPD probe channel%d, slot%d\n", channel, slot); |
Patrick Rudolph | 5a06185 | 2017-09-22 15:19:26 +0200 | [diff] [blame] | 177 | |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame^] | 178 | dimm_attr *const dimm = &ctrl->info.dimm[channel][slot]; |
| 179 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 180 | /* Search for XMP profile */ |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame^] | 181 | spd_xmp_decode_ddr3(dimm, spd[spd_slot], |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 182 | DDR3_XMP_PROFILE_1); |
| 183 | |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame^] | 184 | if (dimm->dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) { |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 185 | printram("No valid XMP profile found.\n"); |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame^] | 186 | spd_decode_ddr3(dimm, spd[spd_slot]); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 187 | |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame^] | 188 | } else if (ch_dimms > dimm->dimms_per_channel) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 189 | printram( |
| 190 | "XMP profile supports %u DIMMs, but %u DIMMs are installed.\n", |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame^] | 191 | dimm->dimms_per_channel, ch_dimms); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 192 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 193 | if (CONFIG(NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS)) |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 194 | printk(BIOS_WARNING, |
| 195 | "XMP maximum DIMMs will be ignored.\n"); |
Vagiz Trakhanov | 771be48 | 2017-10-02 10:02:35 +0000 | [diff] [blame] | 196 | else |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame^] | 197 | spd_decode_ddr3(dimm, spd[spd_slot]); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 198 | |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame^] | 199 | } else if (dimm->voltage != 1500) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 200 | /* TODO: Support DDR3 voltages other than 1500mV */ |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 201 | printram("XMP profile's requested %u mV is unsupported.\n", |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame^] | 202 | dimm->voltage); |
| 203 | spd_decode_ddr3(dimm, spd[spd_slot]); |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 204 | } |
| 205 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 206 | /* Fill in CRC16 for MRC cache */ |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 207 | ctrl->spd_crc[channel][slot] = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 208 | spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data)); |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 209 | |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame^] | 210 | if (dimm->dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 211 | /* Mark DIMM as invalid */ |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame^] | 212 | dimm->ranks = 0; |
| 213 | dimm->size_mb = 0; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 214 | continue; |
| 215 | } |
| 216 | |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame^] | 217 | dram_print_spd_ddr3(dimm); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 218 | dimms++; |
| 219 | ctrl->rank_mirror[channel][slot * 2] = 0; |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame^] | 220 | ctrl->rank_mirror[channel][slot * 2 + 1] = dimm->flags.pins_mirrored; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 221 | |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame^] | 222 | ctrl->channel_size_mb[channel] += dimm->size_mb; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 223 | |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame^] | 224 | if (!dimm->flags.is_ecc) |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 225 | can_use_ecc = false; |
| 226 | |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame^] | 227 | ctrl->auto_self_refresh &= dimm->flags.asr; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 228 | |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame^] | 229 | ctrl->extended_temperature_range &= dimm->flags.ext_temp_refresh; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 230 | |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame^] | 231 | ctrl->rankmap[channel] |= ((1 << dimm->ranks) - 1) << (2 * slot); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 232 | |
| 233 | printk(BIOS_DEBUG, "channel[%d] rankmap = 0x%x\n", channel, |
| 234 | ctrl->rankmap[channel]); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 235 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 236 | if ((ctrl->rankmap[channel] & 0x03) && (ctrl->rankmap[channel] & 0x0c) |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame^] | 237 | && ctrl->info.dimm[channel][0].reference_card <= 5 |
| 238 | && ctrl->info.dimm[channel][1].reference_card <= 5) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 239 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 240 | const int ref_card_offset_table[6][6] = { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 241 | { 0, 0, 0, 0, 2, 2 }, |
| 242 | { 0, 0, 0, 0, 2, 2 }, |
| 243 | { 0, 0, 0, 0, 2, 2 }, |
| 244 | { 0, 0, 0, 0, 1, 1 }, |
| 245 | { 2, 2, 2, 1, 0, 0 }, |
| 246 | { 2, 2, 2, 1, 0, 0 }, |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 247 | }; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 248 | ctrl->ref_card_offset[channel] = ref_card_offset_table |
Angel Pons | 323c0ae | 2020-12-12 16:57:37 +0100 | [diff] [blame^] | 249 | [ctrl->info.dimm[channel][0].reference_card] |
| 250 | [ctrl->info.dimm[channel][1].reference_card]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 251 | } else { |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 252 | ctrl->ref_card_offset[channel] = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 253 | } |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 254 | } |
| 255 | |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 256 | if (ctrl->ecc_forced || CONFIG(RAMINIT_ENABLE_ECC)) |
| 257 | ctrl->ecc_enabled = can_use_ecc; |
| 258 | if (ctrl->ecc_forced && !ctrl->ecc_enabled) |
| 259 | die("ECC mode forced but non-ECC DIMM installed!"); |
| 260 | printk(BIOS_DEBUG, "ECC is %s\n", ctrl->ecc_enabled ? "enabled" : "disabled"); |
| 261 | |
| 262 | ctrl->lanes = ctrl->ecc_enabled ? 9 : 8; |
| 263 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 264 | if (!dimms) |
| 265 | die("No DIMMs were found"); |
| 266 | } |
| 267 | |
Patrick Rudolph | bb9c90a | 2016-05-29 17:05:06 +0200 | [diff] [blame] | 268 | static void save_timings(ramctr_timing *ctrl) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 269 | { |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 270 | /* Save the MRC S3 restore data to cbmem */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 271 | mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, ctrl, sizeof(*ctrl)); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 272 | } |
| 273 | |
Angel Pons | fc93024 | 2020-03-24 11:12:09 +0100 | [diff] [blame] | 274 | static void reinit_ctrl(ramctr_timing *ctrl, const u32 cpuid) |
Patrick Rudolph | 05d4bf7e | 2017-10-28 16:36:09 +0200 | [diff] [blame] | 275 | { |
| 276 | /* Reset internal state */ |
| 277 | memset(ctrl, 0, sizeof(*ctrl)); |
Patrick Rudolph | 05d4bf7e | 2017-10-28 16:36:09 +0200 | [diff] [blame] | 278 | |
| 279 | /* Get architecture */ |
| 280 | ctrl->cpu = cpuid; |
| 281 | |
| 282 | /* Get ECC support and mode */ |
| 283 | ctrl->ecc_forced = get_host_ecc_forced(); |
| 284 | ctrl->ecc_supported = ctrl->ecc_forced || get_host_ecc_cap(); |
| 285 | printk(BIOS_DEBUG, "ECC supported: %s ECC forced: %s\n", |
| 286 | ctrl->ecc_supported ? "yes" : "no", |
| 287 | ctrl->ecc_forced ? "yes" : "no"); |
| 288 | } |
| 289 | |
Angel Pons | fc93024 | 2020-03-24 11:12:09 +0100 | [diff] [blame] | 290 | static void init_dram_ddr3(int s3resume, const u32 cpuid) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 291 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 292 | int me_uma_size, cbmem_was_inited, fast_boot, err; |
Patrick Rudolph | 735ecce | 2016-03-26 10:42:27 +0100 | [diff] [blame] | 293 | ramctr_timing ctrl; |
Kyösti Mälkki | 4cb44e5 | 2016-11-18 19:11:24 +0200 | [diff] [blame] | 294 | spd_raw_data spds[4]; |
Shelley Chen | ad9cd68 | 2020-07-23 16:10:52 -0700 | [diff] [blame] | 295 | size_t mrc_size; |
Angel Pons | a6a6418 | 2020-03-21 18:06:03 +0100 | [diff] [blame] | 296 | ramctr_timing *ctrl_cached = NULL; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 297 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 298 | MCHBAR32(SAPMCTL) |= 1; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 299 | |
| 300 | /* Wait for ME to be ready */ |
| 301 | intel_early_me_init(); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 302 | me_uma_size = intel_early_me_uma_size(); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 303 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 304 | printk(BIOS_DEBUG, "Starting native Platform init\n"); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 305 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 306 | wait_txt_clear(); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 307 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 308 | wrmsr(0x000002e6, (msr_t) { .lo = 0, .hi = 0 }); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 309 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 310 | const u32 sskpd = MCHBAR32(SSKPD); // !!! = 0x00000000 |
| 311 | if ((pci_read_config16(SOUTHBRIDGE, 0xa2) & 0xa0) == 0x20 && sskpd && !s3resume) { |
| 312 | MCHBAR32(SSKPD) = 0; |
| 313 | /* Need reset */ |
Elyes HAOUAS | c056729 | 2019-04-28 17:57:47 +0200 | [diff] [blame] | 314 | system_reset(); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 315 | } |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 316 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 317 | early_pch_init_native(); |
Patrick Rudolph | 6aca7e6 | 2019-03-26 18:22:36 +0100 | [diff] [blame] | 318 | early_init_dmi(); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 319 | early_thermal_init(); |
| 320 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 321 | /* Try to find timings in MRC cache */ |
Shelley Chen | ad9cd68 | 2020-07-23 16:10:52 -0700 | [diff] [blame] | 322 | ctrl_cached = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, |
| 323 | MRC_CACHE_VERSION, |
| 324 | &mrc_size); |
| 325 | if (mrc_size < sizeof(ctrl)) |
| 326 | ctrl_cached = NULL; |
Angel Pons | a6a6418 | 2020-03-21 18:06:03 +0100 | [diff] [blame] | 327 | |
| 328 | /* Before reusing training data, assert that the CPU has not been replaced */ |
| 329 | if (ctrl_cached && cpuid != ctrl_cached->cpu) { |
| 330 | |
| 331 | /* It is not really worrying on a cold boot, but fatal when resuming from S3 */ |
| 332 | printk(s3resume ? BIOS_ALERT : BIOS_NOTICE, |
| 333 | "CPUID %x differs from stored CPUID %x, CPU was replaced!\n", |
| 334 | cpuid, ctrl_cached->cpu); |
| 335 | |
| 336 | /* Invalidate the stored data, it likely does not apply to the current CPU */ |
| 337 | ctrl_cached = NULL; |
| 338 | } |
| 339 | |
| 340 | if (s3resume && !ctrl_cached) { |
| 341 | /* S3 resume is impossible, reset to come up cleanly */ |
| 342 | system_reset(); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 343 | } |
| 344 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 345 | /* Verify MRC cache for fast boot */ |
Kyösti Mälkki | 38cb822 | 2016-11-18 19:25:52 +0200 | [diff] [blame] | 346 | if (!s3resume && ctrl_cached) { |
Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 347 | /* Load SPD unique information data. */ |
| 348 | memset(spds, 0, sizeof(spds)); |
| 349 | mainboard_get_spd(spds, 1); |
| 350 | |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 351 | /* check SPD CRC16 to make sure the DIMMs haven't been replaced */ |
| 352 | fast_boot = verify_crc16_spds_ddr3(spds, ctrl_cached); |
| 353 | if (!fast_boot) |
| 354 | printk(BIOS_DEBUG, "Stored timings CRC16 mismatch.\n"); |
Kyösti Mälkki | 38cb822 | 2016-11-18 19:25:52 +0200 | [diff] [blame] | 355 | } else { |
| 356 | fast_boot = s3resume; |
| 357 | } |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 358 | |
| 359 | if (fast_boot) { |
| 360 | printk(BIOS_DEBUG, "Trying stored timings.\n"); |
| 361 | memcpy(&ctrl, ctrl_cached, sizeof(ctrl)); |
| 362 | |
Patrick Rudolph | 588ccaa | 2016-04-20 18:00:27 +0200 | [diff] [blame] | 363 | err = try_init_dram_ddr3(&ctrl, fast_boot, s3resume, me_uma_size); |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 364 | if (err) { |
Patrick Rudolph | 588ccaa | 2016-04-20 18:00:27 +0200 | [diff] [blame] | 365 | if (s3resume) { |
| 366 | /* Failed S3 resume, reset to come up cleanly */ |
Elyes HAOUAS | c056729 | 2019-04-28 17:57:47 +0200 | [diff] [blame] | 367 | system_reset(); |
Patrick Rudolph | 588ccaa | 2016-04-20 18:00:27 +0200 | [diff] [blame] | 368 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 369 | /* No need to erase bad MRC cache here, it gets overwritten on a |
| 370 | successful boot */ |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 371 | printk(BIOS_ERR, "Stored timings are invalid !\n"); |
| 372 | fast_boot = 0; |
| 373 | } |
| 374 | } |
| 375 | if (!fast_boot) { |
Patrick Rudolph | e74ad21 | 2016-11-16 18:06:50 +0100 | [diff] [blame] | 376 | /* Reset internal state */ |
Angel Pons | fc93024 | 2020-03-24 11:12:09 +0100 | [diff] [blame] | 377 | reinit_ctrl(&ctrl, cpuid); |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 378 | |
Patrick Rudolph | 05d4bf7e | 2017-10-28 16:36:09 +0200 | [diff] [blame] | 379 | printk(BIOS_INFO, "ECC RAM %s.\n", ctrl.ecc_forced ? "required" : |
| 380 | ctrl.ecc_supported ? "supported" : "unsupported"); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 381 | |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 382 | /* Get DDR3 SPD data */ |
Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 383 | memset(spds, 0, sizeof(spds)); |
| 384 | mainboard_get_spd(spds, 0); |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 385 | dram_find_spds_ddr3(spds, &ctrl); |
| 386 | |
Patrick Rudolph | 588ccaa | 2016-04-20 18:00:27 +0200 | [diff] [blame] | 387 | err = try_init_dram_ddr3(&ctrl, fast_boot, s3resume, me_uma_size); |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 388 | } |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 389 | |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 390 | if (err) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 391 | /* Fallback: disable failing channel */ |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 392 | printk(BIOS_ERR, "RAM training failed, trying fallback.\n"); |
| 393 | printram("Disable failing channel.\n"); |
| 394 | |
Patrick Rudolph | e74ad21 | 2016-11-16 18:06:50 +0100 | [diff] [blame] | 395 | /* Reset internal state */ |
Angel Pons | fc93024 | 2020-03-24 11:12:09 +0100 | [diff] [blame] | 396 | reinit_ctrl(&ctrl, cpuid); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 397 | |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 398 | /* Reset DDR3 frequency */ |
| 399 | dram_find_spds_ddr3(spds, &ctrl); |
| 400 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 401 | /* Disable failing channel */ |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 402 | disable_channel(&ctrl, GET_ERR_CHANNEL(err)); |
| 403 | |
| 404 | err = try_init_dram_ddr3(&ctrl, fast_boot, s3resume, me_uma_size); |
| 405 | } |
| 406 | |
Patrick Rudolph | 31d1959 | 2016-03-26 12:22:34 +0100 | [diff] [blame] | 407 | if (err) |
| 408 | die("raminit failed"); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 409 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 410 | /* FIXME: should be hardware revision-dependent. The register only exists on IVB. */ |
| 411 | MCHBAR32(CHANNEL_HASH) = 0x00a030ce; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 412 | |
| 413 | set_scrambling_seed(&ctrl); |
| 414 | |
Patrick Rudolph | d058131 | 2020-05-01 18:31:48 +0200 | [diff] [blame] | 415 | if (!s3resume && ctrl.ecc_enabled) |
| 416 | channel_scrub(&ctrl); |
| 417 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 418 | set_normal_operation(&ctrl); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 419 | |
| 420 | final_registers(&ctrl); |
| 421 | |
Patrick Rudolph | d058131 | 2020-05-01 18:31:48 +0200 | [diff] [blame] | 422 | /* can't do this earlier because it needs to be done in normal operation */ |
| 423 | if (CONFIG(DEBUG_RAM_SETUP) && !s3resume && ctrl.ecc_enabled) { |
| 424 | uint32_t i, tseg = pci_read_config32(HOST_BRIDGE, TSEGMB); |
| 425 | |
| 426 | printk(BIOS_INFO, "RAMINIT: ECC scrub test on first channel up to 0x%x\n", |
| 427 | tseg); |
| 428 | |
| 429 | /* |
| 430 | * This test helps to debug the ECC scrubbing. |
| 431 | * It likely tests every channel/rank, as rank interleave and enhanced |
| 432 | * interleave are enabled, but there's no guarantee for it. |
| 433 | */ |
| 434 | |
| 435 | /* Skip first MB to avoid special case for A-seg and test up to TSEG */ |
| 436 | for (i = 1; i < tseg >> 20; i++) { |
| 437 | for (int j = 0; j < 1 * MiB; j += 4096) { |
| 438 | uintptr_t addr = i * MiB + j; |
| 439 | if (read32((u32 *)addr) == 0) |
| 440 | continue; |
| 441 | |
| 442 | printk(BIOS_ERR, "RAMINIT: ECC scrub: DRAM not cleared at" |
| 443 | " addr 0x%lx\n", addr); |
| 444 | break; |
| 445 | } |
| 446 | } |
| 447 | printk(BIOS_INFO, "RAMINIT: ECC scrub test done.\n"); |
| 448 | } |
| 449 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 450 | /* Zone config */ |
| 451 | dram_zones(&ctrl, 0); |
| 452 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 453 | intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); |
| 454 | intel_early_me_status(); |
| 455 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 456 | report_memory_config(); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 457 | |
| 458 | cbmem_was_inited = !cbmem_recovery(s3resume); |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 459 | if (!fast_boot) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 460 | save_timings(&ctrl); |
| 461 | if (s3resume && !cbmem_was_inited) { |
| 462 | /* Failed S3 resume, reset to come up cleanly */ |
Elyes HAOUAS | c056729 | 2019-04-28 17:57:47 +0200 | [diff] [blame] | 463 | system_reset(); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 464 | } |
Patrick Rudolph | b97009e | 2016-02-28 15:24:04 +0100 | [diff] [blame] | 465 | |
Nico Huber | 9ce5974 | 2018-09-13 10:52:44 +0200 | [diff] [blame] | 466 | if (!s3resume) |
Patrick Rudolph | 42609d8 | 2020-07-27 16:23:36 +0200 | [diff] [blame] | 467 | setup_sdram_meminfo(&ctrl); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 468 | } |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 469 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 470 | void perform_raminit(int s3resume) |
| 471 | { |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 472 | post_code(0x3a); |
| 473 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 474 | timestamp_add_now(TS_BEFORE_INITRAM); |
| 475 | |
Angel Pons | fc93024 | 2020-03-24 11:12:09 +0100 | [diff] [blame] | 476 | init_dram_ddr3(s3resume, cpu_get_cpuid()); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 477 | } |