Keith Hui | 11bce20 | 2020-04-17 12:49:49 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 2 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 3 | #include <spd.h> |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 4 | #include <delay.h> |
Uwe Hermann | 115c5b9 | 2010-10-09 17:00:18 +0000 | [diff] [blame] | 5 | #include <stdint.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 6 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 7 | #include <device/pci_ops.h> |
Uwe Hermann | 115c5b9 | 2010-10-09 17:00:18 +0000 | [diff] [blame] | 8 | #include <device/pci_def.h> |
Kyösti Mälkki | 1a1b04e | 2020-01-07 22:34:33 +0200 | [diff] [blame] | 9 | #include <device/smbus_host.h> |
Uwe Hermann | 115c5b9 | 2010-10-09 17:00:18 +0000 | [diff] [blame] | 10 | #include <console/console.h> |
Keith Hui | 9492788 | 2023-03-13 09:42:15 -0400 | [diff] [blame] | 11 | #include <commonlib/console/post_codes.h> |
Keith Hui | d6f259e | 2020-01-12 18:38:28 -0500 | [diff] [blame] | 12 | #include <timestamp.h> |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 13 | #include "i440bx.h" |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 14 | #include "raminit.h" |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 15 | |
Keith Hui | 9aa45e6 | 2017-07-20 21:00:56 -0400 | [diff] [blame] | 16 | /* |
| 17 | * Macros and definitions |
| 18 | */ |
Keith Hui | df35cdc | 2010-09-20 23:41:37 +0000 | [diff] [blame] | 19 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 20 | /* Debugging macros. */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 21 | #if CONFIG(DEBUG_RAM_SETUP) |
Keith Hui | 09f5a74 | 2010-12-23 17:12:03 +0000 | [diff] [blame] | 22 | #define PRINT_DEBUG(x...) printk(BIOS_DEBUG, x) |
Keith Hui | df35cdc | 2010-09-20 23:41:37 +0000 | [diff] [blame] | 23 | #define DUMPNORTH() dump_pci_device(NB) |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 24 | #else |
Keith Hui | 09f5a74 | 2010-12-23 17:12:03 +0000 | [diff] [blame] | 25 | #define PRINT_DEBUG(x...) |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 26 | #define DUMPNORTH() |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 27 | #endif |
| 28 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 29 | /* SDRAMC[7:5] - SDRAM Mode Select (SMS). */ |
| 30 | #define RAM_COMMAND_NORMAL 0x0 |
| 31 | #define RAM_COMMAND_NOP 0x1 |
| 32 | #define RAM_COMMAND_PRECHARGE 0x2 |
| 33 | #define RAM_COMMAND_MRS 0x3 |
| 34 | #define RAM_COMMAND_CBR 0x4 |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 35 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 36 | /* Map the JEDEC SPD refresh rates (array index) to 440BX refresh rates as |
| 37 | * defined in DRAMC[2:0]. |
| 38 | * |
| 39 | * [0] == Normal 15.625 us -> 15.6 us |
| 40 | * [1] == Reduced(.25X) 3.9 us -> 7.8 ns |
| 41 | * [2] == Reduced(.5X) 7.8 us -> 7.8 us |
| 42 | * [3] == Extended(2x) 31.3 us -> 31.2 us |
| 43 | * [4] == Extended(4x) 62.5 us -> 62.4 us |
| 44 | * [5] == Extended(8x) 125 us -> 124.8 us |
| 45 | */ |
| 46 | static const uint32_t refresh_rate_map[] = { |
| 47 | 1, 5, 5, 2, 3, 4 |
| 48 | }; |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 49 | |
Keith Hui | 8bd784e | 2020-04-05 14:54:22 -0400 | [diff] [blame] | 50 | /* Table format: register, value. */ |
Keith Hui | df35cdc | 2010-09-20 23:41:37 +0000 | [diff] [blame] | 51 | static const u8 register_values[] = { |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 52 | /* NBXCFG - NBX Configuration Register |
Uwe Hermann | f5a6fd2 | 2007-05-27 23:31:31 +0000 | [diff] [blame] | 53 | * 0x50 - 0x53 |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 54 | * |
| 55 | * [31:24] SDRAM Row Without ECC |
| 56 | * 0 = ECC components are populated in this row |
| 57 | * 1 = ECC components are not populated in this row |
| 58 | * [23:19] Reserved |
| 59 | * [18:18] Host Bus Fast Data Ready Enable (HBFDRE) |
| 60 | * Assertion of DRAM data on host bus occurs... |
| 61 | * 0 = ...one clock after sampling snoop results (default) |
| 62 | * 1 = ...on the same clock the snoop result is being sampled |
| 63 | * (this mode is faster by one clock cycle) |
| 64 | * [17:17] ECC - EDO static Drive mode |
| 65 | * 0 = Normal mode (default) |
| 66 | * 1 = ECC signals are always driven |
| 67 | * [16:16] IDSEL_REDIRECT |
| 68 | * 0 = IDSEL1 is allocated to this bridge (default) |
| 69 | * 1 = IDSEL7 is allocated to this bridge |
| 70 | * [15:15] WSC# Handshake Disable |
| 71 | * 1 = Uni-processor mode |
| 72 | * 0 = Dual-processor mode with external IOAPIC (default) |
| 73 | * [14:14] Intel Reserved |
| 74 | * [13:12] Host/DRAM Frequency |
| 75 | * 00 = 100 MHz |
| 76 | * 01 = Reserved |
| 77 | * 10 = 66 MHz |
| 78 | * 11 = Reserved |
| 79 | * [11:11] AGP to PCI Access Enable |
| 80 | * 1 = Enable |
| 81 | * 0 = Disable |
| 82 | * [10:10] PCI Agent to Aperture Access Disable |
| 83 | * 1 = Disable |
| 84 | * 0 = Enable (default) |
| 85 | * [09:09] Aperture Access Global Enable |
| 86 | * 1 = Enable |
| 87 | * 0 = Disable |
| 88 | * [08:07] DRAM Data Integrity Mode (DDIM) |
| 89 | * 00 = Non-ECC |
| 90 | * 01 = EC-only |
| 91 | * 10 = ECC Mode |
| 92 | * 11 = ECC Mode with hardware scrubbing enabled |
| 93 | * [06:06] ECC Diagnostic Mode Enable (EDME) |
| 94 | * 1 = Enable |
| 95 | * 0 = Normal operation mode (default) |
| 96 | * [05:05] MDA Present (MDAP) |
| 97 | * Works in conjunction with the VGA_EN bit. |
| 98 | * VGA_EN MDAP |
| 99 | * 0 x All VGA cycles are sent to PCI |
| 100 | * 1 0 All VGA cycles are sent to AGP |
| 101 | * 1 1 All VGA cycles are sent to AGP, except for |
| 102 | * cycles in the MDA range. |
| 103 | * [04:04] Reserved |
| 104 | * [03:03] USWC Write Post During I/O Bridge Access Enable (UWPIO) |
| 105 | * 1 = Enable |
| 106 | * 0 = Disable |
| 107 | * [02:02] In-Order Queue Depth (IOQD) |
| 108 | * 1 = In-order queue = maximum |
| 109 | * 0 = A7# is sampled asserted (i.e., 0) |
| 110 | * [01:00] Reserved |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 111 | */ |
Keith Hui | 8bd784e | 2020-04-05 14:54:22 -0400 | [diff] [blame] | 112 | NBXCFG + 0, 0x0c, |
Keith Hui | 67c7311 | 2020-04-16 20:45:30 -0400 | [diff] [blame] | 113 | #if CONFIG(SMP) |
| 114 | NBXCFG + 1, 0x00, |
| 115 | #else |
Keith Hui | 8bd784e | 2020-04-05 14:54:22 -0400 | [diff] [blame] | 116 | NBXCFG + 1, 0x80, |
Keith Hui | 67c7311 | 2020-04-16 20:45:30 -0400 | [diff] [blame] | 117 | #endif |
Keith Hui | 8bd784e | 2020-04-05 14:54:22 -0400 | [diff] [blame] | 118 | NBXCFG + 2, 0x00, |
| 119 | NBXCFG + 3, 0xff, |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 120 | |
| 121 | /* DRAMC - DRAM Control Register |
| 122 | * 0x57 |
| 123 | * |
| 124 | * [7:6] Reserved |
| 125 | * [5:5] Module Mode Configuration (MMCONFIG) |
Keith Hui | a8380fc | 2017-12-04 00:05:56 -0500 | [diff] [blame] | 126 | * The combination of SDRAMPWR and this bit (set by an |
Keith Hui | df35cdc | 2010-09-20 23:41:37 +0000 | [diff] [blame] | 127 | * external strapping option) determine how CKE works. |
| 128 | * SDRAMPWR MMCONFIG |
Keith Hui | a8380fc | 2017-12-04 00:05:56 -0500 | [diff] [blame] | 129 | * 0 0 = 3 DIMM, CKE[5:0] driven |
| 130 | * X 1 = 3 DIMM, CKE0 only |
| 131 | * 1 0 = 4 DIMM, GCKE only |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 132 | * [4:3] DRAM Type (DT) |
| 133 | * 00 = EDO |
| 134 | * 01 = SDRAM |
| 135 | * 10 = Registered SDRAM |
| 136 | * 11 = Reserved |
| 137 | * Note: EDO, SDRAM and Registered SDRAM cannot be mixed. |
| 138 | * [2:0] DRAM Refresh Rate (DRR) |
| 139 | * 000 = Refresh disabled |
| 140 | * 001 = 15.6 us |
| 141 | * 010 = 31.2 us |
| 142 | * 011 = 62.4 us |
| 143 | * 100 = 124.8 us |
| 144 | * 101 = 249.6 us |
| 145 | * 110 = Reserved |
| 146 | * 111 = Reserved |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 147 | */ |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 148 | /* Choose SDRAM (not registered), and disable refresh for now. */ |
Keith Hui | 8bd784e | 2020-04-05 14:54:22 -0400 | [diff] [blame] | 149 | DRAMC, 0x08, |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 150 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 151 | /* |
| 152 | * PAM[6:0] - Programmable Attribute Map Registers |
Uwe Hermann | f5a6fd2 | 2007-05-27 23:31:31 +0000 | [diff] [blame] | 153 | * 0x59 - 0x5f |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 154 | * |
| 155 | * 0x59 [3:0] Reserved |
| 156 | * 0x59 [5:4] 0xF0000 - 0xFFFFF BIOS area |
| 157 | * 0x5a [1:0] 0xC0000 - 0xC3FFF ISA add-on BIOS |
| 158 | * 0x5a [5:4] 0xC4000 - 0xC7FFF ISA add-on BIOS |
| 159 | * 0x5b [1:0] 0xC8000 - 0xCBFFF ISA add-on BIOS |
| 160 | * 0x5b [5:4] 0xCC000 - 0xCFFFF ISA add-on BIOS |
| 161 | * 0x5c [1:0] 0xD0000 - 0xD3FFF ISA add-on BIOS |
| 162 | * 0x5c [5:4] 0xD4000 - 0xD7FFF ISA add-on BIOS |
| 163 | * 0x5d [1:0] 0xD8000 - 0xDBFFF ISA add-on BIOS |
| 164 | * 0x5d [5:4] 0xDC000 - 0xDFFFF ISA add-on BIOS |
Martin Roth | 128c104 | 2016-11-18 09:29:03 -0700 | [diff] [blame] | 165 | * 0x5e [1:0] 0xE0000 - 0xE3FFF BIOS extension |
| 166 | * 0x5e [5:4] 0xE4000 - 0xE7FFF BIOS extension |
| 167 | * 0x5f [1:0] 0xE8000 - 0xEBFFF BIOS extension |
| 168 | * 0x5f [5:4] 0xEC000 - 0xEFFFF BIOS extension |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 169 | * |
| 170 | * Bit assignment: |
| 171 | * 00 = DRAM Disabled (all access goes to memory mapped I/O space) |
| 172 | * 01 = Read Only (Reads to DRAM, writes to memory mapped I/O space) |
| 173 | * 10 = Write Only (Writes to DRAM, reads to memory mapped I/O space) |
| 174 | * 11 = Read/Write (all access goes to DRAM) |
| 175 | */ |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 176 | |
| 177 | /* |
| 178 | * Map all legacy regions to RAM (read/write). This is required if |
| 179 | * you want to use the RAM area from 768 KB - 1 MB. If the PAM |
| 180 | * registers are not set here appropriately, the RAM in that region |
| 181 | * will not be accessible, thus a RAM check of it will also fail. |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 182 | */ |
Keith Hui | 8bd784e | 2020-04-05 14:54:22 -0400 | [diff] [blame] | 183 | PAM0, 0x30, |
| 184 | PAM1, 0x33, |
| 185 | PAM2, 0x33, |
| 186 | PAM3, 0x33, |
| 187 | PAM4, 0x33, |
| 188 | PAM5, 0x33, |
| 189 | PAM6, 0x33, |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 190 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 191 | /* DRB[0:7] - DRAM Row Boundary Registers |
| 192 | * 0x60 - 0x67 |
| 193 | * |
| 194 | * An array of 8 byte registers, which hold the ending memory address |
Anders Jenbo | 0e1e806 | 2010-04-27 06:35:31 +0000 | [diff] [blame] | 195 | * assigned to each pair of DIMMs, in 8MB granularity. |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 196 | * |
| 197 | * 0x60 DRB0 = Total memory in row0 (in 8 MB) |
| 198 | * 0x61 DRB1 = Total memory in row0+1 (in 8 MB) |
| 199 | * 0x62 DRB2 = Total memory in row0+1+2 (in 8 MB) |
| 200 | * 0x63 DRB3 = Total memory in row0+1+2+3 (in 8 MB) |
| 201 | * 0x64 DRB4 = Total memory in row0+1+2+3+4 (in 8 MB) |
| 202 | * 0x65 DRB5 = Total memory in row0+1+2+3+4+5 (in 8 MB) |
| 203 | * 0x66 DRB6 = Total memory in row0+1+2+3+4+5+6 (in 8 MB) |
| 204 | * 0x67 DRB7 = Total memory in row0+1+2+3+4+5+6+7 (in 8 MB) |
| 205 | */ |
Keith Hui | a8380fc | 2017-12-04 00:05:56 -0500 | [diff] [blame] | 206 | /* DRBs will be set later. */ |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 207 | |
| 208 | /* FDHC - Fixed DRAM Hole Control Register |
| 209 | * 0x68 |
| 210 | * |
| 211 | * Controls two fixed DRAM holes: 512 KB - 640 KB and 15 MB - 16 MB. |
| 212 | * |
| 213 | * [7:6] Hole Enable (HEN) |
| 214 | * 00 = None |
| 215 | * 01 = 512 KB - 640 KB (128 KB) |
| 216 | * 10 = 15 MB - 16 MB (1 MB) |
| 217 | * 11 = Reserved |
| 218 | * [5:0] Reserved |
| 219 | */ |
| 220 | /* No memory holes. */ |
Keith Hui | 8bd784e | 2020-04-05 14:54:22 -0400 | [diff] [blame] | 221 | FDHC, 0x00, |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 222 | |
| 223 | /* RPS - SDRAM Row Page Size Register |
| 224 | * 0x74 - 0x75 |
| 225 | * |
| 226 | * Sets the row page size for SDRAM. For EDO memory, the page |
| 227 | * size is fixed at 2 KB. |
| 228 | * |
Keith Hui | df35cdc | 2010-09-20 23:41:37 +0000 | [diff] [blame] | 229 | * Bits[1:0] Page Size |
| 230 | * 00 2 KB |
| 231 | * 01 4 KB |
| 232 | * 10 8 KB |
| 233 | * 11 Reserved |
Keith Hui | e089a3f | 2011-08-02 22:28:14 -0400 | [diff] [blame] | 234 | * |
Keith Hui | df35cdc | 2010-09-20 23:41:37 +0000 | [diff] [blame] | 235 | * RPS bits Corresponding DRB register |
| 236 | * [01:00] DRB[0], row 0 |
| 237 | * [03:02] DRB[1], row 1 |
| 238 | * [05:04] DRB[2], row 2 |
| 239 | * [07:06] DRB[3], row 3 |
| 240 | * [09:08] DRB[4], row 4 |
| 241 | * [11:10] DRB[5], row 5 |
| 242 | * [13:12] DRB[6], row 6 |
| 243 | * [15:14] DRB[7], row 7 |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 244 | */ |
Keith Hui | df35cdc | 2010-09-20 23:41:37 +0000 | [diff] [blame] | 245 | /* Power on defaults to 2KB. Will be set later. */ |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 246 | |
| 247 | /* SDRAMC - SDRAM Control Register |
Uwe Hermann | 7ea18cf | 2007-05-04 00:51:17 +0000 | [diff] [blame] | 248 | * 0x76 - 0x77 |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 249 | * |
| 250 | * [15:10] Reserved |
| 251 | * [09:08] Idle/Pipeline DRAM Leadoff Timing (IPDLT) |
| 252 | * 00 = Illegal |
| 253 | * 01 = Add a clock delay to the lead-off clock count |
Keith Hui | df35cdc | 2010-09-20 23:41:37 +0000 | [diff] [blame] | 254 | * 1x = Illegal |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 255 | * [07:05] SDRAM Mode Select (SMS) |
| 256 | * 000 = Normal SDRAM Operation (default) |
| 257 | * 001 = NOP Command Enable |
| 258 | * 010 = All Banks Precharge Enable |
| 259 | * 011 = Mode Register Set Enable |
| 260 | * 100 = CBR Enable |
| 261 | * 101 = Reserved |
| 262 | * 110 = Reserved |
| 263 | * 111 = Reserved |
| 264 | * [04:04] SDRAMPWR |
| 265 | * 0 = 3 DIMM configuration |
| 266 | * 1 = 4 DIMM configuration |
| 267 | * [03:03] Leadoff Command Timing (LCT) |
| 268 | * 0 = 4 CS# Clock |
| 269 | * 1 = 3 CS# Clock |
| 270 | * [02:02] CAS# Latency (CL) |
| 271 | * 0 = 3 DCLK CAS# latency |
| 272 | * 1 = 2 DCLK CAS# latency |
| 273 | * [01:01] SDRAM RAS# to CAS# Delay (SRCD) |
| 274 | * 0 = 3 clocks between a row activate and a read or write cmd. |
| 275 | * 1 = 2 clocks between a row activate and a read or write cmd. |
| 276 | * [00:00] SDRAM RAS# Precharge (SRP) |
| 277 | * 0 = 3 clocks of RAS# precharge |
| 278 | * 1 = 2 clocks of RAS# precharge |
| 279 | */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 280 | #if CONFIG(SDRAMPWR_4DIMM) |
Keith Hui | 8bd784e | 2020-04-05 14:54:22 -0400 | [diff] [blame] | 281 | SDRAMC, 0x10, /* The board has 4 DIMM slots. */ |
Keith Hui | 9c1e1f0 | 2010-03-13 20:16:48 +0000 | [diff] [blame] | 282 | #else |
Keith Hui | 8bd784e | 2020-04-05 14:54:22 -0400 | [diff] [blame] | 283 | SDRAMC, 0x00, /* The board has 3 DIMM slots. */ |
Keith Hui | 9c1e1f0 | 2010-03-13 20:16:48 +0000 | [diff] [blame] | 284 | #endif |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 285 | |
| 286 | /* PGPOL - Paging Policy Register |
| 287 | * 0x78 - 0x79 |
| 288 | * |
| 289 | * [15:08] Banks per Row (BPR) |
Keith Hui | df35cdc | 2010-09-20 23:41:37 +0000 | [diff] [blame] | 290 | * Each bit in this field corresponds to one row of the memory |
| 291 | * array. Bit 15 corresponds to row 7 while bit 8 corresponds |
| 292 | * to row 0. Bits for empty rows are "don't care". |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 293 | * 0 = 2 banks |
| 294 | * 1 = 4 banks |
| 295 | * [07:05] Reserved |
| 296 | * [04:04] Intel Reserved |
| 297 | * [03:00] DRAM Idle Timer (DIT) |
| 298 | * 0000 = 0 clocks |
| 299 | * 0001 = 2 clocks |
| 300 | * 0010 = 4 clocks |
| 301 | * 0011 = 8 clocks |
| 302 | * 0100 = 10 clocks |
| 303 | * 0101 = 12 clocks |
| 304 | * 0110 = 16 clocks |
| 305 | * 0111 = 32 clocks |
| 306 | * 1xxx = Infinite (pages are not closed for idle condition) |
| 307 | */ |
Keith Hui | 8bd784e | 2020-04-05 14:54:22 -0400 | [diff] [blame] | 308 | /* PGPOL will be set later. */ |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 309 | |
| 310 | /* PMCR - Power Management Control Register |
| 311 | * 0x7a |
| 312 | * |
Keith Hui | 8bd784e | 2020-04-05 14:54:22 -0400 | [diff] [blame] | 313 | * [7] Power Down SDRAM Enable (PDSE) |
| 314 | * 1 = Enable |
| 315 | * 0 = Disable |
| 316 | * [6] ACPI Control Register Enable (SCRE) |
| 317 | * 1 = Enable |
| 318 | * 0 = Disable (default) |
| 319 | * [5] Suspend Refresh Type (SRT) |
| 320 | * 1 = Self refresh mode |
| 321 | * 0 = CBR fresh mode |
| 322 | * [4] Normal Refresh Enable (NREF_EN) |
| 323 | * 1 = Enable |
| 324 | * 0 = Disable |
| 325 | * [3] Quick Start Mode (QSTART) |
| 326 | * 1 = Quick start mode for the processor is enabled |
| 327 | * [2] Gated Clock Enable (GCLKEN) |
| 328 | * 1 = Enable |
| 329 | * 0 = Disable |
| 330 | * [1] AGP Disable (AGP_DIS) |
| 331 | * 1 = AGP disabled (Hardware strap) |
| 332 | * [0] CPU reset without PCIRST enable (CRst_En) |
| 333 | * 1 = Enable |
| 334 | * 0 = Disable |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 335 | */ |
Keith Hui | e9b3fd1 | 2020-01-12 18:41:26 -0500 | [diff] [blame] | 336 | /* PMCR will be set later. */ |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 337 | |
| 338 | /* Enable SCRR.SRRAEN and let BX choose the SRR. */ |
Keith Hui | 8bd784e | 2020-04-05 14:54:22 -0400 | [diff] [blame] | 339 | SCRR + 1, 0x10, |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 340 | }; |
| 341 | |
| 342 | /*----------------------------------------------------------------------------- |
| 343 | SDRAM configuration functions. |
| 344 | -----------------------------------------------------------------------------*/ |
| 345 | |
| 346 | /** |
| 347 | * Send the specified RAM command to all DIMMs. |
| 348 | * |
Uwe Hermann | 8b643cea | 2008-12-09 16:36:12 +0000 | [diff] [blame] | 349 | * @param command The RAM command to send to the DIMM(s). |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 350 | */ |
Uwe Hermann | 8b643cea | 2008-12-09 16:36:12 +0000 | [diff] [blame] | 351 | static void do_ram_command(u32 command) |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 352 | { |
Uwe Hermann | 8b643cea | 2008-12-09 16:36:12 +0000 | [diff] [blame] | 353 | int i, caslatency; |
| 354 | u8 dimm_start, dimm_end; |
| 355 | u16 reg16; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 356 | void *addr; |
| 357 | u32 addr_offset; |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 358 | |
| 359 | /* Configure the RAM command. */ |
Uwe Hermann | 8b643cea | 2008-12-09 16:36:12 +0000 | [diff] [blame] | 360 | reg16 = pci_read_config16(NB, SDRAMC); |
| 361 | reg16 &= 0xff1f; /* Clear bits 7-5. */ |
Elyes Haouas | 3a99807 | 2022-11-18 15:11:02 +0100 | [diff] [blame] | 362 | reg16 |= (u16)(command << 5); /* Write command into bits 7-5. */ |
Uwe Hermann | 8b643cea | 2008-12-09 16:36:12 +0000 | [diff] [blame] | 363 | pci_write_config16(NB, SDRAMC, reg16); |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 364 | |
Uwe Hermann | 8b643cea | 2008-12-09 16:36:12 +0000 | [diff] [blame] | 365 | /* |
| 366 | * RAM_COMMAND_NORMAL affects only the memory controller and |
| 367 | * doesn't need to be "sent" to the DIMMs. |
| 368 | */ |
| 369 | if (command == RAM_COMMAND_NORMAL) |
| 370 | return; |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 371 | |
Uwe Hermann | 8b643cea | 2008-12-09 16:36:12 +0000 | [diff] [blame] | 372 | /* Send the RAM command to each row of memory. */ |
| 373 | dimm_start = 0; |
| 374 | for (i = 0; i < (DIMM_SOCKETS * 2); i++) { |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 375 | addr_offset = 0; |
| 376 | caslatency = 3; /* TODO: Dynamically get CAS latency later. */ |
Uwe Hermann | 8b643cea | 2008-12-09 16:36:12 +0000 | [diff] [blame] | 377 | if (command == RAM_COMMAND_MRS) { |
| 378 | /* |
| 379 | * MAA[12:11,9:0] must be inverted when sent to DIMM |
| 380 | * 2 or 3 (no inversion if sent to DIMM 0 or 1). |
| 381 | */ |
| 382 | if ((i >= 0 && i <= 3) && caslatency == 3) |
| 383 | addr_offset = 0x1d0; |
| 384 | if ((i >= 4 && i <= 7) && caslatency == 3) |
| 385 | addr_offset = 0x1e28; |
| 386 | if ((i >= 0 && i <= 3) && caslatency == 2) |
| 387 | addr_offset = 0x150; |
| 388 | if ((i >= 4 && i <= 7) && caslatency == 2) |
| 389 | addr_offset = 0x1ea8; |
| 390 | } |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 391 | |
Uwe Hermann | 8b643cea | 2008-12-09 16:36:12 +0000 | [diff] [blame] | 392 | dimm_end = pci_read_config8(NB, DRB + i); |
| 393 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 394 | addr = (void *)((dimm_start * 8 * 1024 * 1024) + addr_offset); |
Uwe Hermann | 8b643cea | 2008-12-09 16:36:12 +0000 | [diff] [blame] | 395 | if (dimm_end > dimm_start) { |
Uwe Hermann | 8b643cea | 2008-12-09 16:36:12 +0000 | [diff] [blame] | 396 | read32(addr); |
| 397 | } |
| 398 | |
| 399 | /* Set the start of the next DIMM. */ |
| 400 | dimm_start = dimm_end; |
| 401 | } |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 402 | } |
| 403 | |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 404 | static void set_dram_buffer_strength(void) |
| 405 | { |
Keith Hui | a8380fc | 2017-12-04 00:05:56 -0500 | [diff] [blame] | 406 | /* |
| 407 | * Program MBSC[39:0] and MBFS[23:0]. |
| 408 | * |
| 409 | * The 440BX datasheet says buffer frequency is independent from bus |
| 410 | * frequency and mismatch both ways are possible. |
| 411 | * |
| 412 | * MBSC[47:40] and MBFS[23] are reserved. |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 413 | */ |
| 414 | |
Keith Hui | a8380fc | 2017-12-04 00:05:56 -0500 | [diff] [blame] | 415 | unsigned int i, reg, drb; |
| 416 | uint8_t mbsc0, mbfs0, mbfs1, mbfs2; |
| 417 | uint16_t mbsc1, mbsc3; |
| 418 | |
| 419 | /* |
| 420 | * Tally how many rows between rows 0-3 and rows 4-7 are populated. |
Keith Hui | b48ba66 | 2010-03-17 02:15:07 +0000 | [diff] [blame] | 421 | * This determines how to program MBFS and MBSC. |
| 422 | */ |
| 423 | uint8_t dimm03 = 0; |
| 424 | uint8_t dimm47 = 0; |
| 425 | |
Keith Hui | a8380fc | 2017-12-04 00:05:56 -0500 | [diff] [blame] | 426 | for (drb = 0, i = DRB0; i <= DRB7; i++) { |
| 427 | reg = pci_read_config8(NB, i); |
| 428 | if (drb != reg) { |
| 429 | if (i <= DRB3) |
Keith Hui | b48ba66 | 2010-03-17 02:15:07 +0000 | [diff] [blame] | 430 | dimm03++; |
Keith Hui | a8380fc | 2017-12-04 00:05:56 -0500 | [diff] [blame] | 431 | else |
Keith Hui | b48ba66 | 2010-03-17 02:15:07 +0000 | [diff] [blame] | 432 | dimm47++; |
Keith Hui | a8380fc | 2017-12-04 00:05:56 -0500 | [diff] [blame] | 433 | |
| 434 | drb = reg; |
Keith Hui | b48ba66 | 2010-03-17 02:15:07 +0000 | [diff] [blame] | 435 | } |
| 436 | } |
| 437 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 438 | if (CONFIG(SDRAMPWR_4DIMM)) { |
Keith Hui | a8380fc | 2017-12-04 00:05:56 -0500 | [diff] [blame] | 439 | /* |
| 440 | * For a 4 DIMM board, based on ASUS P2B-LS mainboard. |
Keith Hui | b48ba66 | 2010-03-17 02:15:07 +0000 | [diff] [blame] | 441 | * |
Keith Hui | a8380fc | 2017-12-04 00:05:56 -0500 | [diff] [blame] | 442 | * There are four main conditions to check when programming |
| 443 | * DRAM buffer frequency and strength: |
Keith Hui | b48ba66 | 2010-03-17 02:15:07 +0000 | [diff] [blame] | 444 | * |
| 445 | * a: >2 rows populated across DIMM0,1 |
| 446 | * b: >2 rows populated across DIMM2,3 |
| 447 | * c: >4 rows populated across all DIMM slots |
| 448 | * and either one of: |
| 449 | * 1: NBXCFG[13] strapped as 100MHz, or |
| 450 | * 6: NBXCFG[13] strapped as 66MHz |
| 451 | * |
| 452 | * CKE0/FENA ----------------------------------------------------------+ |
Keith Hui | a8380fc | 2017-12-04 00:05:56 -0500 | [diff] [blame] | 453 | * CKE1/GCKE ----------------------[ MBFS ]---------------------+| |
| 454 | * DQMA/CASA[764320]# -------------[ 0 = 66MHz ]--------------------+|| |
| 455 | * DQMB1/CASB1# (Fixed for 66MHz) -[ 1 = 100MHz ]-------------------+||| |
| 456 | * DQMB5/CASB5# (Fixed for 66MHz) ---------------------------------+|||| |
| 457 | * DQMA1/CASA1# (Fixed for 66MHz) --------------------------------+||||| |
| 458 | * DQMA5/CASA5# (Fixed for 66MHz) -------------------------------+|||||| |
| 459 | * CSA[5:0]#,CSB[5:0]# ------------------------------------++++++||||||| |
| 460 | * CS[B7,A7,B6,A6]#/CKE[5342] -------------------------++++||||||||||||| |
| 461 | * MECC[7:0] #2/#1 ----------------------------------++||||||||||||||||| |
| 462 | * MD[63:0] #2/#1 ---------------------------------++||||||||||||||||||| |
| 463 | * MAB[12:11,9:0]#,MAB[13,10],WEB#,SRASB#,SCASB# -+||||||||||||||||||||| |
| 464 | * MAA[13:0],WEA#,SRASA#,SCASA# -----------------+|||||||||||||||||||||| |
| 465 | * Reserved ------------------------------------+||||||||||||||||||||||| |
| 466 | * |||||||||||||||||||||||| |
| 467 | * 3 32 21 10 0 * 2 21 10 0 |
| 468 | * 9876543210987654321098765432109876543210 * 321098765432109876543210 |
| 469 | * 10------------------------1010---------- a -1---------------11----- |
| 470 | * 11------------------------1111---------- !a -0---------------00----- |
| 471 | * --10--------------------------1010------ b --1----------------11--- |
| 472 | * --11--------------------------1111------ !b --0----------------00--- |
| 473 | * ----------------------------------1100-- c ----------------------1- |
| 474 | * ----------------------------------1011-- !c ----------------------0- |
| 475 | * ----1010101000000000000000------------00 1 ---11111111111111----1-0 |
| 476 | * ----000000000000000000000010101010----00 6 ---1111111111111100000-0 |
| 477 | * | | | | | | | | | | ||||||| | | | | | | |
| 478 | * | | | | | | | | | | ||||||| | | | | | +- CKE0/FENA |
| 479 | * | | | | | | | | | | ||||||| | | | | +--- CKE1/GCKE |
| 480 | * | | | | | | | | | | ||||||| | | | +----- DQMA/CASA[764320]# |
| 481 | * | | | | | | | | | | ||||||| | | +------- DQMB1/CASB1# (66MHz: 2x) |
| 482 | * | | | | | | | | | | ||||||| | +--------- DQMB5/CASB5# (66MHz: 2x) |
| 483 | * | | | | | | | | | | ||||||| +----------- DQMA1/CASA1# (66MHz: 2x) |
| 484 | * | | | | | | | | | | ||||||+------------- DQMA5/CASA5# (66MHz: 2x) |
| 485 | * | | | | | | | | | | ++++++-------------- CSA0-5#,CSB0-5# (1x) |
| 486 | * | | | | | | | | | +--------------------- CSA6#/CKE2 |
| 487 | * | | | | | | | | +---[ MBSC ]------ CSB6#/CKE4 |
| 488 | * | | | | | | | +-----[ 00 = 1x ]------ CSA7#/CKE3 |
| 489 | * | | | | | | +-------[ 01 invalid ]------ CSB7#/CKE5 |
| 490 | * | | | | | +---------[ 10 = 2x ]------ MECC[7:0] #1 |
| 491 | * | | | | +-----------[ 11 = 3x ]------ MECC[7:0] #2 |
| 492 | * | | | +--------------------------------- MD[63:0] #1 |
| 493 | * | | +----------------------------------- MD[63:0] #2 |
| 494 | * | +------------------ MAB[12:11,9:0]#,MAB[13,10],WEB#,SRASB#,SCASB# |
| 495 | * +------------------------------------- MAA[13:0],WEA#,SRASA#,SCASA# |
| 496 | */ |
| 497 | unsigned int fsb; |
| 498 | |
| 499 | mbsc0 = 0xa0; |
| 500 | mbsc1 = 0x002a; |
| 501 | mbfs1 = 0xff; |
| 502 | mbfs2 = 0x1f; |
| 503 | if (pci_read_config8(NB, NBXCFG + 1) & 0x30) { |
| 504 | fsb = 66; |
| 505 | mbsc3 = 0xa000; |
| 506 | mbfs0 = 0x80; |
| 507 | } else { |
| 508 | fsb = 100; |
| 509 | mbsc3 = 0xaaa0; |
| 510 | mbfs0 = 0x84; |
| 511 | } |
| 512 | if (dimm03 > 2) { |
| 513 | mbfs2 |= 0x40; |
| 514 | if (fsb == 100) |
| 515 | mbfs0 |= 0x60; |
| 516 | } else { |
| 517 | mbsc3 |= 0xc000; |
| 518 | if (fsb == 100) |
| 519 | mbsc1 |= 0x003c; |
| 520 | } |
| 521 | if (dimm47 > 2) { |
| 522 | mbfs2 |= 0x20; |
| 523 | if (fsb == 100) |
| 524 | mbfs0 |= 0x18; |
| 525 | } else { |
| 526 | mbsc3 |= 0x3000; |
| 527 | if (fsb == 100) { |
| 528 | mbsc1 |= 0x0003; |
| 529 | mbsc0 |= 0xc0; |
| 530 | } |
| 531 | } |
| 532 | if ((dimm03 + dimm47) > 4) { |
| 533 | mbsc0 |= 0x30; |
| 534 | mbfs0 |= 0x02; |
| 535 | } else { |
| 536 | mbsc0 |= 0x2c; |
| 537 | } |
| 538 | } else { |
| 539 | /* |
| 540 | * For a 3 DIMM board, based on ASUS P2B mainboard. |
| 541 | * |
| 542 | * There are two main conditions to check when programming DRAM buffer |
| 543 | * frequency and strength: |
| 544 | * |
| 545 | * a: >2 rows populated across DIMM0,1 |
| 546 | * c: >4 rows populated across all DIMM slots |
| 547 | * |
| 548 | * CKE0 ---------------------------------------------------------------+ |
| 549 | * CKE1 ------------------------[ MBFS ]------------------------+| |
Keith Hui | b48ba66 | 2010-03-17 02:15:07 +0000 | [diff] [blame] | 550 | * DQMA/CASA[764320]# ----------[ 0 = 66MHz ]-----------------------+|| |
| 551 | * DQMB1/CASB1# ----------------[ 1 = 100MHz ]----------------------+||| |
| 552 | * DQMB5/CASB5# ---------------------------------------------------+|||| |
| 553 | * DQMA1/CASA1# --------------------------------------------------+||||| |
| 554 | * DQMA5/CASA5# -------------------------------------------------+|||||| |
| 555 | * CSA0-5#,CSB0-5# ----------------------------------------++++++||||||| |
Keith Hui | a8380fc | 2017-12-04 00:05:56 -0500 | [diff] [blame] | 556 | * CS[B7,A7,B6,A6]#/CKE[5342] -------------------------++++||||||||||||| |
Keith Hui | b48ba66 | 2010-03-17 02:15:07 +0000 | [diff] [blame] | 557 | * MECC[7:0] #2/#1 (100MHz) -------------------------++||||||||||||||||| |
| 558 | * MD[63:0] #2/#1 (100MHz) ------------------------++||||||||||||||||||| |
| 559 | * MAB[12:11,9:0]#,MAB[13,10],WEB#,SRASB#,SCASB# -+||||||||||||||||||||| |
| 560 | * MAA[13:0],WEA#,SRASA#,SCASA# -----------------+|||||||||||||||||||||| |
| 561 | * Reserved ------------------------------------+||||||||||||||||||||||| |
| 562 | * |||||||||||||||||||||||| |
Keith Hui | a8380fc | 2017-12-04 00:05:56 -0500 | [diff] [blame] | 563 | * 3 32 21 10 0 * 2 21 10 0 |
| 564 | * 9876543210987654321098765432109876543210 * 321098765432109876543210 |
| 565 | * 10------------------------1111---------- a -1---------------------- |
| 566 | * 11------------------------1010---------- !a -0---------------------- |
| 567 | * --110000000010101010111111----1010--1010 * --01111000000000000000-0 |
| 568 | * ----------------------------------11---- c ----------------------1- |
| 569 | * ----------------------------------10---- !c ----------------------0- |
| 570 | * | | | | | | | | | | ||||||| | | | | | | |
| 571 | * | | | | | | | | | | ||||||| | | | | | +- CKE0 |
| 572 | * | | | | | | | | | | ||||||| | | | | +--- CKE1 |
| 573 | * | | | | | | | | | | ||||||| | | | +----- DQMA/CASA[764320]# |
| 574 | * | | | | | | | | | | ||||||| | | +------- DQMB1/CASB1# |
| 575 | * | | | | | | | | | | ||||||| | +--------- DQMB5/CASB5# |
| 576 | * | | | | | | | | | | ||||||| +----------- DQMA1/CASA1# |
| 577 | * | | | | | | | | | | ||||||+------------- DQMA5/CASA5# |
| 578 | * | | | | | | | | | | ++++++-------------- CSA0-5#,CSB0-5# (2x) |
| 579 | * | | | | | | | | | +--------------------- CSA6#/CKE2 |
| 580 | * | | | | | | | | +---[ MBSC ]------ CSB6#/CKE4 |
| 581 | * | | | | | | | +-----[ 00 = 1x ]------ CSA7#/CKE3 |
| 582 | * | | | | | | +-------[ 01 invalid ]------ CSB7#/CKE5 |
| 583 | * | | | | | +---------[ 10 = 2x ]------ MECC[7:0] #1 (1x) |
| 584 | * | | | | +-----------[ 11 = 3x ]------ MECC[7:0] #2 (1x) |
| 585 | * | | | +--------------------------------- MD[63:0] #1 (1x) |
| 586 | * | | +----------------------------------- MD[63:0] #2 (1x) |
| 587 | * | +------------------ MAB[12:11,9:0]#,MAB[13,10],WEB#,SRASB#,SCASB# |
| 588 | * +------------------------------------- MAA[13:0],WEA#,SRASA#,SCASA# |
Keith Hui | b48ba66 | 2010-03-17 02:15:07 +0000 | [diff] [blame] | 589 | */ |
Anders Jenbo | 0e1e806 | 2010-04-27 06:35:31 +0000 | [diff] [blame] | 590 | |
Keith Hui | a8380fc | 2017-12-04 00:05:56 -0500 | [diff] [blame] | 591 | mbsc0 = 0xaa; |
| 592 | mbsc1 = 0xafea; |
| 593 | mbsc3 = 0xb00a; |
| 594 | mbfs0 = 0x00; |
| 595 | mbfs1 = 0x00; |
| 596 | mbfs2 = 0x1e; |
Anders Jenbo | 0e1e806 | 2010-04-27 06:35:31 +0000 | [diff] [blame] | 597 | |
Keith Hui | a8380fc | 2017-12-04 00:05:56 -0500 | [diff] [blame] | 598 | if (dimm03 > 2) { |
| 599 | mbsc1 |= 0x003c; |
| 600 | mbfs2 |= 0x40; |
| 601 | } else { |
| 602 | mbsc3 |= 0xc000; |
Keith Hui | b48ba66 | 2010-03-17 02:15:07 +0000 | [diff] [blame] | 603 | } |
Keith Hui | a8380fc | 2017-12-04 00:05:56 -0500 | [diff] [blame] | 604 | if ((dimm03 + dimm47) > 4) { |
| 605 | mbsc0 |= 0x30; |
| 606 | mbfs0 |= 0x02; |
Keith Hui | b48ba66 | 2010-03-17 02:15:07 +0000 | [diff] [blame] | 607 | } |
| 608 | } |
Keith Hui | b48ba66 | 2010-03-17 02:15:07 +0000 | [diff] [blame] | 609 | |
| 610 | pci_write_config8(NB, MBSC + 0, mbsc0); |
Keith Hui | a8380fc | 2017-12-04 00:05:56 -0500 | [diff] [blame] | 611 | pci_write_config16(NB, MBSC + 1, mbsc1); |
| 612 | pci_write_config16(NB, MBSC + 3, mbsc3); |
| 613 | pci_write_config16(NB, MBFS + 0, mbfs1 << 8 | mbfs0); |
Keith Hui | b48ba66 | 2010-03-17 02:15:07 +0000 | [diff] [blame] | 614 | pci_write_config8(NB, MBFS + 2, mbfs2); |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 615 | } |
| 616 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 617 | /*----------------------------------------------------------------------------- |
Martin Roth | 128c104 | 2016-11-18 09:29:03 -0700 | [diff] [blame] | 618 | DIMM-independent configuration functions. |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 619 | -----------------------------------------------------------------------------*/ |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 620 | |
Uwe Hermann | 1683cef | 2008-11-27 00:47:07 +0000 | [diff] [blame] | 621 | static void spd_enable_refresh(void) |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 622 | { |
| 623 | int i, value; |
| 624 | uint8_t reg; |
| 625 | |
Uwe Hermann | 1683cef | 2008-11-27 00:47:07 +0000 | [diff] [blame] | 626 | reg = pci_read_config8(NB, DRAMC); |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 627 | |
| 628 | for (i = 0; i < DIMM_SOCKETS; i++) { |
Kyösti Mälkki | 3f882faf | 2020-01-07 12:10:02 +0200 | [diff] [blame] | 629 | value = smbus_read_byte(DIMM0 + i, SPD_REFRESH); |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 630 | if (value < 0) |
| 631 | continue; |
| 632 | reg = (reg & 0xf8) | refresh_rate_map[(value & 0x7f)]; |
| 633 | |
Keith Hui | 09f5a74 | 2010-12-23 17:12:03 +0000 | [diff] [blame] | 634 | PRINT_DEBUG(" Enabling refresh (DRAMC = 0x%02x) for DIMM %02x\n", reg, i); |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 635 | } |
| 636 | |
Uwe Hermann | 1683cef | 2008-11-27 00:47:07 +0000 | [diff] [blame] | 637 | pci_write_config8(NB, DRAMC, reg); |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 638 | } |
| 639 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 640 | /*----------------------------------------------------------------------------- |
| 641 | Public interface. |
| 642 | -----------------------------------------------------------------------------*/ |
| 643 | |
Kyösti Mälkki | 7a95575 | 2020-01-07 12:18:24 +0200 | [diff] [blame] | 644 | static void sdram_set_registers(void) |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 645 | { |
| 646 | int i, max; |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 647 | |
Keith Hui | d118b8e | 2023-03-23 15:45:37 -0400 | [diff] [blame^] | 648 | PRINT_DEBUG("Northbridge %s SDRAM init:\n", "prior to"); |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 649 | DUMPNORTH(); |
| 650 | |
Carl-Daniel Hailfinger | 2ee6779 | 2008-10-01 12:52:52 +0000 | [diff] [blame] | 651 | max = ARRAY_SIZE(register_values); |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 652 | |
Uwe Hermann | f5a6fd2 | 2007-05-27 23:31:31 +0000 | [diff] [blame] | 653 | /* Set registers as specified in the register_values[] array. */ |
Keith Hui | 8bd784e | 2020-04-05 14:54:22 -0400 | [diff] [blame] | 654 | for (i = 0; i < max; i += 2) |
| 655 | pci_write_config8(NB, register_values[i], register_values[i + 1]); |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 656 | } |
| 657 | |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 658 | struct dimm_size { |
Keith Hui | 09f5a74 | 2010-12-23 17:12:03 +0000 | [diff] [blame] | 659 | u32 side1; |
| 660 | u32 side2; |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 661 | }; |
| 662 | |
| 663 | static struct dimm_size spd_get_dimm_size(unsigned int device) |
| 664 | { |
| 665 | struct dimm_size sz; |
| 666 | int i, module_density, dimm_banks; |
| 667 | sz.side1 = 0; |
Kyösti Mälkki | 3f882faf | 2020-01-07 12:10:02 +0200 | [diff] [blame] | 668 | module_density = smbus_read_byte(device, SPD_DENSITY_OF_EACH_ROW_ON_MODULE); |
| 669 | dimm_banks = smbus_read_byte(device, SPD_NUM_DIMM_BANKS); |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 670 | |
| 671 | /* Find the size of side1. */ |
| 672 | /* Find the larger value. The larger value is always side1. */ |
| 673 | for (i = 512; i >= 0; i >>= 1) { |
| 674 | if ((module_density & i) == i) { |
| 675 | sz.side1 = i; |
| 676 | break; |
| 677 | } |
| 678 | } |
| 679 | |
| 680 | /* Set to 0 in case it's single sided. */ |
| 681 | sz.side2 = 0; |
| 682 | |
| 683 | /* Test if it's a dual-sided DIMM. */ |
| 684 | if (dimm_banks > 1) { |
| 685 | /* Test if there's a second value. If so it's asymmetrical. */ |
| 686 | if (module_density != i) { |
| 687 | /* |
| 688 | * Find second value, picking up where we left off. |
| 689 | * i >>= 1 done initially to make sure we don't get |
| 690 | * the same value again. |
| 691 | */ |
| 692 | for (i >>= 1; i >= 0; i >>= 1) { |
| 693 | if (module_density == (sz.side1 | i)) { |
| 694 | sz.side2 = i; |
| 695 | break; |
| 696 | } |
| 697 | } |
| 698 | /* If not, it's symmetrical. */ |
| 699 | } else { |
| 700 | sz.side2 = sz.side1; |
| 701 | } |
| 702 | } |
| 703 | |
| 704 | /* |
| 705 | * SPD byte 31 is the memory size divided by 4 so we |
Martin Roth | 128c104 | 2016-11-18 09:29:03 -0700 | [diff] [blame] | 706 | * need to multiply by 4 to get the total size. |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 707 | */ |
| 708 | sz.side1 *= 4; |
| 709 | sz.side2 *= 4; |
| 710 | |
Keith Hui | a8380fc | 2017-12-04 00:05:56 -0500 | [diff] [blame] | 711 | /* |
| 712 | * It is possible to partially use larger than supported |
Anders Jenbo | 771b0e4 | 2010-04-27 08:45:30 +0000 | [diff] [blame] | 713 | * modules by setting them to a supported size. |
| 714 | */ |
Elyes HAOUAS | 12df950 | 2016-08-23 21:29:48 +0200 | [diff] [blame] | 715 | if (sz.side1 > 128) { |
Keith Hui | d118b8e | 2023-03-23 15:45:37 -0400 | [diff] [blame^] | 716 | PRINT_DEBUG("Side%d was %dMB but only 128MB will be used.\n", |
| 717 | 1, sz.side1); |
Anders Jenbo | 771b0e4 | 2010-04-27 08:45:30 +0000 | [diff] [blame] | 718 | sz.side1 = 128; |
| 719 | |
Elyes HAOUAS | 12df950 | 2016-08-23 21:29:48 +0200 | [diff] [blame] | 720 | if (sz.side2 > 128) { |
Keith Hui | d118b8e | 2023-03-23 15:45:37 -0400 | [diff] [blame^] | 721 | PRINT_DEBUG("Side%d was %dMB but only 128MB will be used.\n", |
| 722 | 2, sz.side2); |
Anders Jenbo | 771b0e4 | 2010-04-27 08:45:30 +0000 | [diff] [blame] | 723 | sz.side2 = 128; |
| 724 | } |
| 725 | } |
| 726 | |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 727 | return sz; |
| 728 | } |
| 729 | /* |
| 730 | * Sets DRAM attributes one DIMM at a time, based on SPD data. |
| 731 | * Northbridge settings that are set: NBXCFG[31:24], DRB0-DRB7, RPS, DRAMC. |
| 732 | */ |
| 733 | static void set_dram_row_attributes(void) |
| 734 | { |
Keith Hui | e089a3f | 2011-08-02 22:28:14 -0400 | [diff] [blame] | 735 | int i, dra, drb, col, width, value, rps; |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 736 | u8 bpr; /* Top 8 bits of PGPOL */ |
Keith Hui | e089a3f | 2011-08-02 22:28:14 -0400 | [diff] [blame] | 737 | u8 nbxecc = 0; /* NBXCFG[31:24] */ |
| 738 | u8 edo, sd, regsd; /* EDO, SDRAM, registered SDRAM */ |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 739 | |
Keith Hui | e089a3f | 2011-08-02 22:28:14 -0400 | [diff] [blame] | 740 | edo = 0; |
| 741 | sd = 0; |
| 742 | regsd = 1; |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 743 | rps = 0; |
| 744 | drb = 0; |
| 745 | bpr = 0; |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 746 | |
| 747 | for (i = 0; i < DIMM_SOCKETS; i++) { |
| 748 | unsigned int device; |
Uwe Hermann | d773fd3 | 2010-11-20 20:23:08 +0000 | [diff] [blame] | 749 | device = DIMM0 + i; |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 750 | bpr >>= 2; |
Keith Hui | e089a3f | 2011-08-02 22:28:14 -0400 | [diff] [blame] | 751 | nbxecc >>= 2; |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 752 | |
| 753 | /* First check if a DIMM is actually present. */ |
Kyösti Mälkki | 3f882faf | 2020-01-07 12:10:02 +0200 | [diff] [blame] | 754 | value = smbus_read_byte(device, SPD_MEMORY_TYPE); |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 755 | /* This is 440BX! We do EDO too! */ |
| 756 | if (value == SPD_MEMORY_TYPE_EDO |
| 757 | || value == SPD_MEMORY_TYPE_SDRAM) { |
| 758 | |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 759 | if (value == SPD_MEMORY_TYPE_EDO) { |
Keith Hui | e089a3f | 2011-08-02 22:28:14 -0400 | [diff] [blame] | 760 | edo = 1; |
Anders Jenbo | 0e1e806 | 2010-04-27 06:35:31 +0000 | [diff] [blame] | 761 | } else if (value == SPD_MEMORY_TYPE_SDRAM) { |
Keith Hui | e089a3f | 2011-08-02 22:28:14 -0400 | [diff] [blame] | 762 | sd = 1; |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 763 | } |
Keith Hui | 09f5a74 | 2010-12-23 17:12:03 +0000 | [diff] [blame] | 764 | PRINT_DEBUG("Found DIMM in slot %d\n", i); |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 765 | |
Keith Hui | e089a3f | 2011-08-02 22:28:14 -0400 | [diff] [blame] | 766 | if (edo && sd) { |
Keith Hui | 9492788 | 2023-03-13 09:42:15 -0400 | [diff] [blame] | 767 | die_with_post_code(POST_RAM_FAILURE, |
| 768 | "Mixing EDO/SDRAM unsupported!\n"); |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 769 | } |
| 770 | |
| 771 | /* "DRA" is our RPS for the two rows on this DIMM. */ |
| 772 | dra = 0; |
| 773 | |
| 774 | /* Columns */ |
Kyösti Mälkki | 3f882faf | 2020-01-07 12:10:02 +0200 | [diff] [blame] | 775 | col = smbus_read_byte(device, SPD_NUM_COLUMNS); |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 776 | |
| 777 | /* |
| 778 | * Is this an ECC DIMM? Actually will be a 2 if so. |
| 779 | * TODO: Other register than NBXCFG also needs this |
| 780 | * ECC information. |
| 781 | */ |
Kyösti Mälkki | 3f882faf | 2020-01-07 12:10:02 +0200 | [diff] [blame] | 782 | value = smbus_read_byte(device, SPD_DIMM_CONFIG_TYPE); |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 783 | |
| 784 | /* Data width */ |
Kyösti Mälkki | 3f882faf | 2020-01-07 12:10:02 +0200 | [diff] [blame] | 785 | width = smbus_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB); |
Anders Jenbo | 0e1e806 | 2010-04-27 06:35:31 +0000 | [diff] [blame] | 786 | |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 787 | /* Exclude error checking data width from page size calculations */ |
Keith Hui | e089a3f | 2011-08-02 22:28:14 -0400 | [diff] [blame] | 788 | if (value) { |
Kyösti Mälkki | 3f882faf | 2020-01-07 12:10:02 +0200 | [diff] [blame] | 789 | value = smbus_read_byte(device, |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 790 | SPD_ERROR_CHECKING_SDRAM_WIDTH); |
| 791 | width -= value; |
| 792 | /* ### ECC */ |
| 793 | /* Clear top 2 bits to help set up NBXCFG. */ |
Keith Hui | e089a3f | 2011-08-02 22:28:14 -0400 | [diff] [blame] | 794 | nbxecc &= 0x3f; |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 795 | } else { |
| 796 | /* Without ECC, top 2 bits should be 11. */ |
Keith Hui | e089a3f | 2011-08-02 22:28:14 -0400 | [diff] [blame] | 797 | nbxecc |= 0xc0; |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 798 | } |
| 799 | |
Keith Hui | e089a3f | 2011-08-02 22:28:14 -0400 | [diff] [blame] | 800 | /* If any installed DIMM is *not* registered, this system cannot be |
| 801 | * configured for registered SDRAM. |
| 802 | * By registered, only the address and control lines need to be, which |
| 803 | * we can tell by reading SPD byte 21, bit 1. |
| 804 | */ |
Kyösti Mälkki | 3f882faf | 2020-01-07 12:10:02 +0200 | [diff] [blame] | 805 | value = smbus_read_byte(device, SPD_MODULE_ATTRIBUTES); |
Keith Hui | e089a3f | 2011-08-02 22:28:14 -0400 | [diff] [blame] | 806 | |
| 807 | PRINT_DEBUG("DIMM is "); |
| 808 | if ((value & MODULE_REGISTERED) == 0) { |
| 809 | regsd = 0; |
| 810 | PRINT_DEBUG("not "); |
| 811 | } |
| 812 | PRINT_DEBUG("registered\n"); |
| 813 | |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 814 | /* Calculate page size in bits. */ |
| 815 | value = ((1 << col) * width); |
| 816 | |
| 817 | /* Convert to KB. */ |
| 818 | dra = (value >> 13); |
| 819 | |
| 820 | /* Number of banks of DIMM (single or double sided). */ |
Kyösti Mälkki | 3f882faf | 2020-01-07 12:10:02 +0200 | [diff] [blame] | 821 | value = smbus_read_byte(device, SPD_NUM_DIMM_BANKS); |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 822 | |
| 823 | /* Once we have dra, col is done and can be reused. |
| 824 | * So it's reused for number of banks. |
| 825 | */ |
Kyösti Mälkki | 3f882faf | 2020-01-07 12:10:02 +0200 | [diff] [blame] | 826 | col = smbus_read_byte(device, SPD_NUM_BANKS_PER_SDRAM); |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 827 | |
| 828 | if (value == 1) { |
| 829 | /* |
| 830 | * Second bank of 1-bank DIMMs "doesn't have |
| 831 | * ECC" - or anything. |
| 832 | */ |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 833 | if (dra == 2) { |
| 834 | dra = 0x0; /* 2KB */ |
| 835 | } else if (dra == 4) { |
| 836 | dra = 0x1; /* 4KB */ |
| 837 | } else if (dra == 8) { |
| 838 | dra = 0x2; /* 8KB */ |
Anders Jenbo | 771b0e4 | 2010-04-27 08:45:30 +0000 | [diff] [blame] | 839 | } else if (dra >= 16) { |
| 840 | /* Page sizes larger than supported are |
| 841 | * set to 8KB to use module partially. |
| 842 | */ |
| 843 | PRINT_DEBUG("Page size forced to 8KB.\n"); |
| 844 | dra = 0x2; /* 8KB */ |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 845 | } else { |
| 846 | dra = -1; |
| 847 | } |
| 848 | /* |
| 849 | * Sets a flag in PGPOL[BPR] if this DIMM has |
| 850 | * 4 banks per row. |
| 851 | */ |
| 852 | if (col == 4) |
| 853 | bpr |= 0x40; |
| 854 | } else if (value == 2) { |
| 855 | if (dra == 2) { |
| 856 | dra = 0x0; /* 2KB */ |
| 857 | } else if (dra == 4) { |
| 858 | dra = 0x05; /* 4KB */ |
| 859 | } else if (dra == 8) { |
| 860 | dra = 0x0a; /* 8KB */ |
Anders Jenbo | 771b0e4 | 2010-04-27 08:45:30 +0000 | [diff] [blame] | 861 | } else if (dra >= 16) { |
| 862 | /* Ditto */ |
| 863 | PRINT_DEBUG("Page size forced to 8KB.\n"); |
| 864 | dra = 0x0a; /* 8KB */ |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 865 | } else { |
| 866 | dra = -1; |
| 867 | } |
| 868 | /* Ditto */ |
| 869 | if (col == 4) |
| 870 | bpr |= 0xc0; |
| 871 | } else { |
Keith Hui | 9492788 | 2023-03-13 09:42:15 -0400 | [diff] [blame] | 872 | die_with_post_code(POST_RAM_FAILURE, |
| 873 | "# of banks of DIMM unsupported!\n"); |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 874 | } |
| 875 | if (dra == -1) { |
Keith Hui | 9492788 | 2023-03-13 09:42:15 -0400 | [diff] [blame] | 876 | die_with_post_code(POST_RAM_FAILURE, |
| 877 | "Page size not supported!\n"); |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 878 | } |
| 879 | |
| 880 | /* |
| 881 | * 440BX supports asymmetrical dual-sided DIMMs, |
| 882 | * but can't handle DIMMs smaller than 8MB per |
Anders Jenbo | 771b0e4 | 2010-04-27 08:45:30 +0000 | [diff] [blame] | 883 | * side. |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 884 | */ |
| 885 | struct dimm_size sz = spd_get_dimm_size(device); |
| 886 | if ((sz.side1 < 8)) { |
Keith Hui | 9492788 | 2023-03-13 09:42:15 -0400 | [diff] [blame] | 887 | die_with_post_code(POST_RAM_FAILURE, |
| 888 | "DIMMs smaller than 8MB per side " |
| 889 | "are not supported!\n"); |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 890 | } |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 891 | |
| 892 | /* Divide size by 8 to set up the DRB registers. */ |
| 893 | drb += (sz.side1 / 8); |
| 894 | |
| 895 | /* |
| 896 | * Build the DRB for the next row in MSB so it gets |
| 897 | * placed in DRB[n+1] where it belongs when written |
| 898 | * as a 16-bit word. |
| 899 | */ |
| 900 | drb &= 0xff; |
| 901 | drb |= (drb + (sz.side2 / 8)) << 8; |
| 902 | } else { |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 903 | /* If there's no DIMM in the slot, set dra to 0x00. */ |
| 904 | dra = 0x00; |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 905 | /* Still have to propagate DRB over. */ |
| 906 | drb &= 0xff; |
| 907 | drb |= (drb << 8); |
| 908 | } |
| 909 | |
| 910 | pci_write_config16(NB, DRB + (2 * i), drb); |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 911 | |
| 912 | /* Brings the upper DRB back down to be base for |
| 913 | * DRB calculations for the next two rows. |
| 914 | */ |
| 915 | drb >>= 8; |
| 916 | |
| 917 | rps |= (dra & 0x0f) << (i * 4); |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 918 | } |
| 919 | |
| 920 | /* Set paging policy register. */ |
| 921 | pci_write_config8(NB, PGPOL + 1, bpr); |
Keith Hui | d118b8e | 2023-03-23 15:45:37 -0400 | [diff] [blame^] | 922 | PRINT_DEBUG("%s has been set to 0x%02x\n", "PGPOL[BPR]", bpr); |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 923 | |
| 924 | /* Set DRAM row page size register. */ |
| 925 | pci_write_config16(NB, RPS, rps); |
Keith Hui | 09f5a74 | 2010-12-23 17:12:03 +0000 | [diff] [blame] | 926 | PRINT_DEBUG("RPS has been set to 0x%04x\n", rps); |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 927 | |
| 928 | /* ### ECC */ |
| 929 | pci_write_config8(NB, NBXCFG + 3, nbxecc); |
Keith Hui | d118b8e | 2023-03-23 15:45:37 -0400 | [diff] [blame^] | 930 | PRINT_DEBUG("%s has been set to 0x%02x\n", "NBXCFG[31:24]", nbxecc); |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 931 | |
Keith Hui | e089a3f | 2011-08-02 22:28:14 -0400 | [diff] [blame] | 932 | /* Set DRAMC[4:3] to proper memory type (EDO/SDRAM/Registered SDRAM). */ |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 933 | |
Keith Hui | e089a3f | 2011-08-02 22:28:14 -0400 | [diff] [blame] | 934 | /* i will be used to set DRAMC[4:3]. */ |
| 935 | if (regsd && sd) { |
| 936 | i = 0x10; // Registered SDRAM |
| 937 | } else if (sd) { |
| 938 | i = 0x08; // SDRAM |
| 939 | } else { |
| 940 | i = 0; // EDO |
| 941 | } |
| 942 | |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 943 | value = pci_read_config8(NB, DRAMC) & 0xe7; |
Keith Hui | e089a3f | 2011-08-02 22:28:14 -0400 | [diff] [blame] | 944 | value |= i; |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 945 | pci_write_config8(NB, DRAMC, value); |
Keith Hui | d118b8e | 2023-03-23 15:45:37 -0400 | [diff] [blame^] | 946 | PRINT_DEBUG("%s has been set to 0x%02x\n", "DRAMC", value); |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 947 | } |
| 948 | |
Kyösti Mälkki | 7a95575 | 2020-01-07 12:18:24 +0200 | [diff] [blame] | 949 | static void sdram_set_spd_registers(void) |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 950 | { |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 951 | /* Setup DRAM row boundary registers and other attributes. */ |
| 952 | set_dram_row_attributes(); |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 953 | |
Keith Hui | df35cdc | 2010-09-20 23:41:37 +0000 | [diff] [blame] | 954 | /* Setup DRAM buffer strength. */ |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 955 | set_dram_buffer_strength(); |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 956 | } |
| 957 | |
Kyösti Mälkki | 7a95575 | 2020-01-07 12:18:24 +0200 | [diff] [blame] | 958 | static void sdram_enable(void) |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 959 | { |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 960 | int i; |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 961 | |
Uwe Hermann | 861f964 | 2007-05-28 14:37:06 +0000 | [diff] [blame] | 962 | /* 0. Wait until power/voltages and clocks are stable (200us). */ |
| 963 | udelay(200); |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 964 | |
Uwe Hermann | 861f964 | 2007-05-28 14:37:06 +0000 | [diff] [blame] | 965 | /* 1. Apply NOP. Wait 200 clock cycles (200us should do). */ |
Keith Hui | d118b8e | 2023-03-23 15:45:37 -0400 | [diff] [blame^] | 966 | PRINT_DEBUG("RAM Enable %d: %s\n", 1, "Apply NOP"); |
Uwe Hermann | 8b643cea | 2008-12-09 16:36:12 +0000 | [diff] [blame] | 967 | do_ram_command(RAM_COMMAND_NOP); |
Uwe Hermann | 861f964 | 2007-05-28 14:37:06 +0000 | [diff] [blame] | 968 | udelay(200); |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 969 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 970 | /* 2. Precharge all. Wait tRP. */ |
Keith Hui | d118b8e | 2023-03-23 15:45:37 -0400 | [diff] [blame^] | 971 | PRINT_DEBUG("RAM Enable %d: %s\n", 2, "Precharge all"); |
Uwe Hermann | 8b643cea | 2008-12-09 16:36:12 +0000 | [diff] [blame] | 972 | do_ram_command(RAM_COMMAND_PRECHARGE); |
Uwe Hermann | 861f964 | 2007-05-28 14:37:06 +0000 | [diff] [blame] | 973 | udelay(1); |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 974 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 975 | /* 3. Perform 8 refresh cycles. Wait tRC each time. */ |
Keith Hui | d118b8e | 2023-03-23 15:45:37 -0400 | [diff] [blame^] | 976 | PRINT_DEBUG("RAM Enable %d: %s\n", 3, "CBR"); |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 977 | for (i = 0; i < 8; i++) { |
Uwe Hermann | 8b643cea | 2008-12-09 16:36:12 +0000 | [diff] [blame] | 978 | do_ram_command(RAM_COMMAND_CBR); |
Uwe Hermann | 861f964 | 2007-05-28 14:37:06 +0000 | [diff] [blame] | 979 | udelay(1); |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 980 | } |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 981 | |
| 982 | /* 4. Mode register set. Wait two memory cycles. */ |
Keith Hui | d118b8e | 2023-03-23 15:45:37 -0400 | [diff] [blame^] | 983 | PRINT_DEBUG("RAM Enable %d: %s\n", 4, "Mode register set"); |
Uwe Hermann | 8b643cea | 2008-12-09 16:36:12 +0000 | [diff] [blame] | 984 | do_ram_command(RAM_COMMAND_MRS); |
Uwe Hermann | 861f964 | 2007-05-28 14:37:06 +0000 | [diff] [blame] | 985 | udelay(2); |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 986 | |
| 987 | /* 5. Normal operation. */ |
Keith Hui | d118b8e | 2023-03-23 15:45:37 -0400 | [diff] [blame^] | 988 | PRINT_DEBUG("RAM Enable %d: %s\n", 5, "Normal operation"); |
Uwe Hermann | 8b643cea | 2008-12-09 16:36:12 +0000 | [diff] [blame] | 989 | do_ram_command(RAM_COMMAND_NORMAL); |
Uwe Hermann | 861f964 | 2007-05-28 14:37:06 +0000 | [diff] [blame] | 990 | udelay(1); |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 991 | |
| 992 | /* 6. Finally enable refresh. */ |
Keith Hui | d118b8e | 2023-03-23 15:45:37 -0400 | [diff] [blame^] | 993 | PRINT_DEBUG("RAM Enable %d: %s\n", 6, "Enable refresh"); |
Keith Hui | e9b3fd1 | 2020-01-12 18:41:26 -0500 | [diff] [blame] | 994 | pci_write_config8(NB, PMCR, 0x10); |
Uwe Hermann | 1683cef | 2008-11-27 00:47:07 +0000 | [diff] [blame] | 995 | spd_enable_refresh(); |
Uwe Hermann | 861f964 | 2007-05-28 14:37:06 +0000 | [diff] [blame] | 996 | udelay(1); |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 997 | |
Keith Hui | d118b8e | 2023-03-23 15:45:37 -0400 | [diff] [blame^] | 998 | PRINT_DEBUG("Northbridge %s SDRAM init:\n", "following"); |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 999 | DUMPNORTH(); |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 1000 | } |
Keith Hui | 078e324 | 2017-07-20 21:14:21 -0400 | [diff] [blame] | 1001 | |
Kyösti Mälkki | 93e08c7 | 2020-01-07 15:17:48 +0200 | [diff] [blame] | 1002 | /* Implemented under mainboard. */ |
| 1003 | void __weak enable_spd(void) { } |
Kyösti Mälkki | 93e08c7 | 2020-01-07 15:17:48 +0200 | [diff] [blame] | 1004 | |
Keith Hui | 0e0fdbe | 2020-04-29 12:47:41 -0400 | [diff] [blame] | 1005 | void sdram_initialize(int s3resume) |
Keith Hui | 078e324 | 2017-07-20 21:14:21 -0400 | [diff] [blame] | 1006 | { |
Jakub Czapiga | ad6157e | 2022-02-15 11:50:31 +0100 | [diff] [blame] | 1007 | timestamp_add_now(TS_INITRAM_START); |
Kyösti Mälkki | 93e08c7 | 2020-01-07 15:17:48 +0200 | [diff] [blame] | 1008 | enable_spd(); |
| 1009 | |
Keith Hui | 078e324 | 2017-07-20 21:14:21 -0400 | [diff] [blame] | 1010 | dump_spd_registers(); |
| 1011 | sdram_set_registers(); |
| 1012 | sdram_set_spd_registers(); |
| 1013 | sdram_enable(); |
Kyösti Mälkki | 93e08c7 | 2020-01-07 15:17:48 +0200 | [diff] [blame] | 1014 | |
Keith Hui | 6554873 | 2023-03-23 01:14:58 -0400 | [diff] [blame] | 1015 | /* Clear any errors reported during raminit. */ |
| 1016 | pci_write_config32(NB, EAP, 0x3); |
| 1017 | pci_write_config8(NB, ERRSTS, 0x11); |
| 1018 | pci_write_config8(NB, ERRSTS + 1, 0x1f); |
| 1019 | |
Jakub Czapiga | ad6157e | 2022-02-15 11:50:31 +0100 | [diff] [blame] | 1020 | timestamp_add_now(TS_INITRAM_END); |
Martin Roth | e1695e2 | 2017-07-24 11:28:50 -0600 | [diff] [blame] | 1021 | } |