blob: ee1e75902ee82e09b3cdeaf3d717b259ae4ef84f [file] [log] [blame]
Richard Smithcb8eab42006-07-24 04:25:47 +00001/*
Stefan Reinauer7e61e452008-01-18 10:35:56 +00002 * This file is part of the coreboot project.
Uwe Hermann1a9c8922007-04-01 17:24:03 +00003 *
Uwe Hermann1a9c8922007-04-01 17:24:03 +00004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Richard Smithcb8eab42006-07-24 04:25:47 +000014 */
15
Uwe Hermann1a9c8922007-04-01 17:24:03 +000016#include <spd.h>
Uwe Hermann1a9c8922007-04-01 17:24:03 +000017#include <delay.h>
Uwe Hermann115c5b92010-10-09 17:00:18 +000018#include <stdint.h>
Kyösti Mälkki13f66502019-03-03 08:01:05 +020019#include <device/mmio.h>
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +020020#include <device/pci_ops.h>
Uwe Hermann115c5b92010-10-09 17:00:18 +000021#include <device/pci_def.h>
22#include <console/console.h>
Keith Huid6f259e2020-01-12 18:38:28 -050023#include <timestamp.h>
Uwe Hermann1a9c8922007-04-01 17:24:03 +000024#include "i440bx.h"
Keith Hui59356ca2010-03-06 18:16:25 +000025#include "raminit.h"
Richard Smithcb8eab42006-07-24 04:25:47 +000026
Kyösti Mälkki3f882faf2020-01-07 12:10:02 +020027#include <southbridge/intel/i82371eb/i82371eb.h>
28
Keith Hui9aa45e62017-07-20 21:00:56 -040029/*
30 * Macros and definitions
31 */
Keith Huidf35cdc2010-09-20 23:41:37 +000032
Uwe Hermann1a9c8922007-04-01 17:24:03 +000033/* Debugging macros. */
Julius Wernercd49cce2019-03-05 16:53:33 -080034#if CONFIG(DEBUG_RAM_SETUP)
Keith Hui09f5a742010-12-23 17:12:03 +000035#define PRINT_DEBUG(x...) printk(BIOS_DEBUG, x)
Keith Huidf35cdc2010-09-20 23:41:37 +000036#define DUMPNORTH() dump_pci_device(NB)
Richard Smithcb8eab42006-07-24 04:25:47 +000037#else
Keith Hui09f5a742010-12-23 17:12:03 +000038#define PRINT_DEBUG(x...)
Uwe Hermann1a9c8922007-04-01 17:24:03 +000039#define DUMPNORTH()
Richard Smithcb8eab42006-07-24 04:25:47 +000040#endif
41
Uwe Hermann1a9c8922007-04-01 17:24:03 +000042/* SDRAMC[7:5] - SDRAM Mode Select (SMS). */
43#define RAM_COMMAND_NORMAL 0x0
44#define RAM_COMMAND_NOP 0x1
45#define RAM_COMMAND_PRECHARGE 0x2
46#define RAM_COMMAND_MRS 0x3
47#define RAM_COMMAND_CBR 0x4
Richard Smithcb8eab42006-07-24 04:25:47 +000048
Uwe Hermann1a9c8922007-04-01 17:24:03 +000049/* Map the JEDEC SPD refresh rates (array index) to 440BX refresh rates as
50 * defined in DRAMC[2:0].
51 *
52 * [0] == Normal 15.625 us -> 15.6 us
53 * [1] == Reduced(.25X) 3.9 us -> 7.8 ns
54 * [2] == Reduced(.5X) 7.8 us -> 7.8 us
55 * [3] == Extended(2x) 31.3 us -> 31.2 us
56 * [4] == Extended(4x) 62.5 us -> 62.4 us
57 * [5] == Extended(8x) 125 us -> 124.8 us
58 */
59static const uint32_t refresh_rate_map[] = {
60 1, 5, 5, 2, 3, 4
61};
Richard Smithcb8eab42006-07-24 04:25:47 +000062
Keith Hui8bd784e2020-04-05 14:54:22 -040063/* Table format: register, value. */
Keith Huidf35cdc2010-09-20 23:41:37 +000064static const u8 register_values[] = {
Uwe Hermann1a9c8922007-04-01 17:24:03 +000065 /* NBXCFG - NBX Configuration Register
Uwe Hermannf5a6fd22007-05-27 23:31:31 +000066 * 0x50 - 0x53
Uwe Hermann1a9c8922007-04-01 17:24:03 +000067 *
68 * [31:24] SDRAM Row Without ECC
69 * 0 = ECC components are populated in this row
70 * 1 = ECC components are not populated in this row
71 * [23:19] Reserved
72 * [18:18] Host Bus Fast Data Ready Enable (HBFDRE)
73 * Assertion of DRAM data on host bus occurs...
74 * 0 = ...one clock after sampling snoop results (default)
75 * 1 = ...on the same clock the snoop result is being sampled
76 * (this mode is faster by one clock cycle)
77 * [17:17] ECC - EDO static Drive mode
78 * 0 = Normal mode (default)
79 * 1 = ECC signals are always driven
80 * [16:16] IDSEL_REDIRECT
81 * 0 = IDSEL1 is allocated to this bridge (default)
82 * 1 = IDSEL7 is allocated to this bridge
83 * [15:15] WSC# Handshake Disable
84 * 1 = Uni-processor mode
85 * 0 = Dual-processor mode with external IOAPIC (default)
86 * [14:14] Intel Reserved
87 * [13:12] Host/DRAM Frequency
88 * 00 = 100 MHz
89 * 01 = Reserved
90 * 10 = 66 MHz
91 * 11 = Reserved
92 * [11:11] AGP to PCI Access Enable
93 * 1 = Enable
94 * 0 = Disable
95 * [10:10] PCI Agent to Aperture Access Disable
96 * 1 = Disable
97 * 0 = Enable (default)
98 * [09:09] Aperture Access Global Enable
99 * 1 = Enable
100 * 0 = Disable
101 * [08:07] DRAM Data Integrity Mode (DDIM)
102 * 00 = Non-ECC
103 * 01 = EC-only
104 * 10 = ECC Mode
105 * 11 = ECC Mode with hardware scrubbing enabled
106 * [06:06] ECC Diagnostic Mode Enable (EDME)
107 * 1 = Enable
108 * 0 = Normal operation mode (default)
109 * [05:05] MDA Present (MDAP)
110 * Works in conjunction with the VGA_EN bit.
111 * VGA_EN MDAP
112 * 0 x All VGA cycles are sent to PCI
113 * 1 0 All VGA cycles are sent to AGP
114 * 1 1 All VGA cycles are sent to AGP, except for
115 * cycles in the MDA range.
116 * [04:04] Reserved
117 * [03:03] USWC Write Post During I/O Bridge Access Enable (UWPIO)
118 * 1 = Enable
119 * 0 = Disable
120 * [02:02] In-Order Queue Depth (IOQD)
121 * 1 = In-order queue = maximum
122 * 0 = A7# is sampled asserted (i.e., 0)
123 * [01:00] Reserved
Richard Smithcb8eab42006-07-24 04:25:47 +0000124 */
Keith Hui8bd784e2020-04-05 14:54:22 -0400125 NBXCFG + 0, 0x0c,
Keith Hui67c73112020-04-16 20:45:30 -0400126#if CONFIG(SMP)
127 NBXCFG + 1, 0x00,
128#else
Keith Hui8bd784e2020-04-05 14:54:22 -0400129 NBXCFG + 1, 0x80,
Keith Hui67c73112020-04-16 20:45:30 -0400130#endif
Keith Hui8bd784e2020-04-05 14:54:22 -0400131 NBXCFG + 2, 0x00,
132 NBXCFG + 3, 0xff,
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000133
134 /* DRAMC - DRAM Control Register
135 * 0x57
136 *
137 * [7:6] Reserved
138 * [5:5] Module Mode Configuration (MMCONFIG)
Keith Huia8380fc2017-12-04 00:05:56 -0500139 * The combination of SDRAMPWR and this bit (set by an
Keith Huidf35cdc2010-09-20 23:41:37 +0000140 * external strapping option) determine how CKE works.
141 * SDRAMPWR MMCONFIG
Keith Huia8380fc2017-12-04 00:05:56 -0500142 * 0 0 = 3 DIMM, CKE[5:0] driven
143 * X 1 = 3 DIMM, CKE0 only
144 * 1 0 = 4 DIMM, GCKE only
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000145 * [4:3] DRAM Type (DT)
146 * 00 = EDO
147 * 01 = SDRAM
148 * 10 = Registered SDRAM
149 * 11 = Reserved
150 * Note: EDO, SDRAM and Registered SDRAM cannot be mixed.
151 * [2:0] DRAM Refresh Rate (DRR)
152 * 000 = Refresh disabled
153 * 001 = 15.6 us
154 * 010 = 31.2 us
155 * 011 = 62.4 us
156 * 100 = 124.8 us
157 * 101 = 249.6 us
158 * 110 = Reserved
159 * 111 = Reserved
Richard Smithcb8eab42006-07-24 04:25:47 +0000160 */
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000161 /* Choose SDRAM (not registered), and disable refresh for now. */
Keith Hui8bd784e2020-04-05 14:54:22 -0400162 DRAMC, 0x08,
Richard Smithcb8eab42006-07-24 04:25:47 +0000163
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000164 /*
165 * PAM[6:0] - Programmable Attribute Map Registers
Uwe Hermannf5a6fd22007-05-27 23:31:31 +0000166 * 0x59 - 0x5f
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000167 *
168 * 0x59 [3:0] Reserved
169 * 0x59 [5:4] 0xF0000 - 0xFFFFF BIOS area
170 * 0x5a [1:0] 0xC0000 - 0xC3FFF ISA add-on BIOS
171 * 0x5a [5:4] 0xC4000 - 0xC7FFF ISA add-on BIOS
172 * 0x5b [1:0] 0xC8000 - 0xCBFFF ISA add-on BIOS
173 * 0x5b [5:4] 0xCC000 - 0xCFFFF ISA add-on BIOS
174 * 0x5c [1:0] 0xD0000 - 0xD3FFF ISA add-on BIOS
175 * 0x5c [5:4] 0xD4000 - 0xD7FFF ISA add-on BIOS
176 * 0x5d [1:0] 0xD8000 - 0xDBFFF ISA add-on BIOS
177 * 0x5d [5:4] 0xDC000 - 0xDFFFF ISA add-on BIOS
Martin Roth128c1042016-11-18 09:29:03 -0700178 * 0x5e [1:0] 0xE0000 - 0xE3FFF BIOS extension
179 * 0x5e [5:4] 0xE4000 - 0xE7FFF BIOS extension
180 * 0x5f [1:0] 0xE8000 - 0xEBFFF BIOS extension
181 * 0x5f [5:4] 0xEC000 - 0xEFFFF BIOS extension
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000182 *
183 * Bit assignment:
184 * 00 = DRAM Disabled (all access goes to memory mapped I/O space)
185 * 01 = Read Only (Reads to DRAM, writes to memory mapped I/O space)
186 * 10 = Write Only (Writes to DRAM, reads to memory mapped I/O space)
187 * 11 = Read/Write (all access goes to DRAM)
188 */
Keith Hui59356ca2010-03-06 18:16:25 +0000189
190 /*
191 * Map all legacy regions to RAM (read/write). This is required if
192 * you want to use the RAM area from 768 KB - 1 MB. If the PAM
193 * registers are not set here appropriately, the RAM in that region
194 * will not be accessible, thus a RAM check of it will also fail.
Keith Hui59356ca2010-03-06 18:16:25 +0000195 */
Keith Hui8bd784e2020-04-05 14:54:22 -0400196 PAM0, 0x30,
197 PAM1, 0x33,
198 PAM2, 0x33,
199 PAM3, 0x33,
200 PAM4, 0x33,
201 PAM5, 0x33,
202 PAM6, 0x33,
Richard Smithcb8eab42006-07-24 04:25:47 +0000203
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000204 /* DRB[0:7] - DRAM Row Boundary Registers
205 * 0x60 - 0x67
206 *
207 * An array of 8 byte registers, which hold the ending memory address
Anders Jenbo0e1e8062010-04-27 06:35:31 +0000208 * assigned to each pair of DIMMs, in 8MB granularity.
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000209 *
210 * 0x60 DRB0 = Total memory in row0 (in 8 MB)
211 * 0x61 DRB1 = Total memory in row0+1 (in 8 MB)
212 * 0x62 DRB2 = Total memory in row0+1+2 (in 8 MB)
213 * 0x63 DRB3 = Total memory in row0+1+2+3 (in 8 MB)
214 * 0x64 DRB4 = Total memory in row0+1+2+3+4 (in 8 MB)
215 * 0x65 DRB5 = Total memory in row0+1+2+3+4+5 (in 8 MB)
216 * 0x66 DRB6 = Total memory in row0+1+2+3+4+5+6 (in 8 MB)
217 * 0x67 DRB7 = Total memory in row0+1+2+3+4+5+6+7 (in 8 MB)
218 */
Keith Huia8380fc2017-12-04 00:05:56 -0500219 /* DRBs will be set later. */
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000220
221 /* FDHC - Fixed DRAM Hole Control Register
222 * 0x68
223 *
224 * Controls two fixed DRAM holes: 512 KB - 640 KB and 15 MB - 16 MB.
225 *
226 * [7:6] Hole Enable (HEN)
227 * 00 = None
228 * 01 = 512 KB - 640 KB (128 KB)
229 * 10 = 15 MB - 16 MB (1 MB)
230 * 11 = Reserved
231 * [5:0] Reserved
232 */
233 /* No memory holes. */
Keith Hui8bd784e2020-04-05 14:54:22 -0400234 FDHC, 0x00,
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000235
236 /* RPS - SDRAM Row Page Size Register
237 * 0x74 - 0x75
238 *
239 * Sets the row page size for SDRAM. For EDO memory, the page
240 * size is fixed at 2 KB.
241 *
Keith Huidf35cdc2010-09-20 23:41:37 +0000242 * Bits[1:0] Page Size
243 * 00 2 KB
244 * 01 4 KB
245 * 10 8 KB
246 * 11 Reserved
Keith Huie089a3f2011-08-02 22:28:14 -0400247 *
Keith Huidf35cdc2010-09-20 23:41:37 +0000248 * RPS bits Corresponding DRB register
249 * [01:00] DRB[0], row 0
250 * [03:02] DRB[1], row 1
251 * [05:04] DRB[2], row 2
252 * [07:06] DRB[3], row 3
253 * [09:08] DRB[4], row 4
254 * [11:10] DRB[5], row 5
255 * [13:12] DRB[6], row 6
256 * [15:14] DRB[7], row 7
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000257 */
Keith Huidf35cdc2010-09-20 23:41:37 +0000258 /* Power on defaults to 2KB. Will be set later. */
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000259
260 /* SDRAMC - SDRAM Control Register
Uwe Hermann7ea18cf2007-05-04 00:51:17 +0000261 * 0x76 - 0x77
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000262 *
263 * [15:10] Reserved
264 * [09:08] Idle/Pipeline DRAM Leadoff Timing (IPDLT)
265 * 00 = Illegal
266 * 01 = Add a clock delay to the lead-off clock count
Keith Huidf35cdc2010-09-20 23:41:37 +0000267 * 1x = Illegal
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000268 * [07:05] SDRAM Mode Select (SMS)
269 * 000 = Normal SDRAM Operation (default)
270 * 001 = NOP Command Enable
271 * 010 = All Banks Precharge Enable
272 * 011 = Mode Register Set Enable
273 * 100 = CBR Enable
274 * 101 = Reserved
275 * 110 = Reserved
276 * 111 = Reserved
277 * [04:04] SDRAMPWR
278 * 0 = 3 DIMM configuration
279 * 1 = 4 DIMM configuration
280 * [03:03] Leadoff Command Timing (LCT)
281 * 0 = 4 CS# Clock
282 * 1 = 3 CS# Clock
283 * [02:02] CAS# Latency (CL)
284 * 0 = 3 DCLK CAS# latency
285 * 1 = 2 DCLK CAS# latency
286 * [01:01] SDRAM RAS# to CAS# Delay (SRCD)
287 * 0 = 3 clocks between a row activate and a read or write cmd.
288 * 1 = 2 clocks between a row activate and a read or write cmd.
289 * [00:00] SDRAM RAS# Precharge (SRP)
290 * 0 = 3 clocks of RAS# precharge
291 * 1 = 2 clocks of RAS# precharge
292 */
Julius Wernercd49cce2019-03-05 16:53:33 -0800293#if CONFIG(SDRAMPWR_4DIMM)
Keith Hui8bd784e2020-04-05 14:54:22 -0400294 SDRAMC, 0x10, /* The board has 4 DIMM slots. */
Keith Hui9c1e1f02010-03-13 20:16:48 +0000295#else
Keith Hui8bd784e2020-04-05 14:54:22 -0400296 SDRAMC, 0x00, /* The board has 3 DIMM slots. */
Keith Hui9c1e1f02010-03-13 20:16:48 +0000297#endif
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000298
299 /* PGPOL - Paging Policy Register
300 * 0x78 - 0x79
301 *
302 * [15:08] Banks per Row (BPR)
Keith Huidf35cdc2010-09-20 23:41:37 +0000303 * Each bit in this field corresponds to one row of the memory
304 * array. Bit 15 corresponds to row 7 while bit 8 corresponds
305 * to row 0. Bits for empty rows are "don't care".
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000306 * 0 = 2 banks
307 * 1 = 4 banks
308 * [07:05] Reserved
309 * [04:04] Intel Reserved
310 * [03:00] DRAM Idle Timer (DIT)
311 * 0000 = 0 clocks
312 * 0001 = 2 clocks
313 * 0010 = 4 clocks
314 * 0011 = 8 clocks
315 * 0100 = 10 clocks
316 * 0101 = 12 clocks
317 * 0110 = 16 clocks
318 * 0111 = 32 clocks
319 * 1xxx = Infinite (pages are not closed for idle condition)
320 */
Keith Hui8bd784e2020-04-05 14:54:22 -0400321 /* PGPOL will be set later. */
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000322
323 /* PMCR - Power Management Control Register
324 * 0x7a
325 *
Keith Hui8bd784e2020-04-05 14:54:22 -0400326 * [7] Power Down SDRAM Enable (PDSE)
327 * 1 = Enable
328 * 0 = Disable
329 * [6] ACPI Control Register Enable (SCRE)
330 * 1 = Enable
331 * 0 = Disable (default)
332 * [5] Suspend Refresh Type (SRT)
333 * 1 = Self refresh mode
334 * 0 = CBR fresh mode
335 * [4] Normal Refresh Enable (NREF_EN)
336 * 1 = Enable
337 * 0 = Disable
338 * [3] Quick Start Mode (QSTART)
339 * 1 = Quick start mode for the processor is enabled
340 * [2] Gated Clock Enable (GCLKEN)
341 * 1 = Enable
342 * 0 = Disable
343 * [1] AGP Disable (AGP_DIS)
344 * 1 = AGP disabled (Hardware strap)
345 * [0] CPU reset without PCIRST enable (CRst_En)
346 * 1 = Enable
347 * 0 = Disable
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000348 */
Keith Huie9b3fd12020-01-12 18:41:26 -0500349 /* PMCR will be set later. */
Keith Hui59356ca2010-03-06 18:16:25 +0000350
351 /* Enable SCRR.SRRAEN and let BX choose the SRR. */
Keith Hui8bd784e2020-04-05 14:54:22 -0400352 SCRR + 1, 0x10,
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000353};
354
355/*-----------------------------------------------------------------------------
356SDRAM configuration functions.
357-----------------------------------------------------------------------------*/
358
359/**
360 * Send the specified RAM command to all DIMMs.
361 *
Uwe Hermann8b643cea2008-12-09 16:36:12 +0000362 * @param command The RAM command to send to the DIMM(s).
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000363 */
Uwe Hermann8b643cea2008-12-09 16:36:12 +0000364static void do_ram_command(u32 command)
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000365{
Uwe Hermann8b643cea2008-12-09 16:36:12 +0000366 int i, caslatency;
367 u8 dimm_start, dimm_end;
368 u16 reg16;
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800369 void *addr;
370 u32 addr_offset;
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000371
372 /* Configure the RAM command. */
Uwe Hermann8b643cea2008-12-09 16:36:12 +0000373 reg16 = pci_read_config16(NB, SDRAMC);
374 reg16 &= 0xff1f; /* Clear bits 7-5. */
375 reg16 |= (u16) (command << 5); /* Write command into bits 7-5. */
376 pci_write_config16(NB, SDRAMC, reg16);
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000377
Uwe Hermann8b643cea2008-12-09 16:36:12 +0000378 /*
379 * RAM_COMMAND_NORMAL affects only the memory controller and
380 * doesn't need to be "sent" to the DIMMs.
381 */
382 if (command == RAM_COMMAND_NORMAL)
383 return;
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000384
Uwe Hermann8b643cea2008-12-09 16:36:12 +0000385 /* Send the RAM command to each row of memory. */
386 dimm_start = 0;
387 for (i = 0; i < (DIMM_SOCKETS * 2); i++) {
Keith Hui59356ca2010-03-06 18:16:25 +0000388 addr_offset = 0;
389 caslatency = 3; /* TODO: Dynamically get CAS latency later. */
Uwe Hermann8b643cea2008-12-09 16:36:12 +0000390 if (command == RAM_COMMAND_MRS) {
391 /*
392 * MAA[12:11,9:0] must be inverted when sent to DIMM
393 * 2 or 3 (no inversion if sent to DIMM 0 or 1).
394 */
395 if ((i >= 0 && i <= 3) && caslatency == 3)
396 addr_offset = 0x1d0;
397 if ((i >= 4 && i <= 7) && caslatency == 3)
398 addr_offset = 0x1e28;
399 if ((i >= 0 && i <= 3) && caslatency == 2)
400 addr_offset = 0x150;
401 if ((i >= 4 && i <= 7) && caslatency == 2)
402 addr_offset = 0x1ea8;
403 }
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000404
Uwe Hermann8b643cea2008-12-09 16:36:12 +0000405 dimm_end = pci_read_config8(NB, DRB + i);
406
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800407 addr = (void *)((dimm_start * 8 * 1024 * 1024) + addr_offset);
Uwe Hermann8b643cea2008-12-09 16:36:12 +0000408 if (dimm_end > dimm_start) {
Uwe Hermann8b643cea2008-12-09 16:36:12 +0000409 read32(addr);
410 }
411
412 /* Set the start of the next DIMM. */
413 dimm_start = dimm_end;
414 }
Richard Smithcb8eab42006-07-24 04:25:47 +0000415}
416
Keith Hui59356ca2010-03-06 18:16:25 +0000417static void set_dram_buffer_strength(void)
418{
Keith Huia8380fc2017-12-04 00:05:56 -0500419 /*
420 * Program MBSC[39:0] and MBFS[23:0].
421 *
422 * The 440BX datasheet says buffer frequency is independent from bus
423 * frequency and mismatch both ways are possible.
424 *
425 * MBSC[47:40] and MBFS[23] are reserved.
Keith Hui59356ca2010-03-06 18:16:25 +0000426 */
427
Keith Huia8380fc2017-12-04 00:05:56 -0500428 unsigned int i, reg, drb;
429 uint8_t mbsc0, mbfs0, mbfs1, mbfs2;
430 uint16_t mbsc1, mbsc3;
431
432 /*
433 * Tally how many rows between rows 0-3 and rows 4-7 are populated.
Keith Huib48ba662010-03-17 02:15:07 +0000434 * This determines how to program MBFS and MBSC.
435 */
436 uint8_t dimm03 = 0;
437 uint8_t dimm47 = 0;
438
Keith Huia8380fc2017-12-04 00:05:56 -0500439 for (drb = 0, i = DRB0; i <= DRB7; i++) {
440 reg = pci_read_config8(NB, i);
441 if (drb != reg) {
442 if (i <= DRB3)
Keith Huib48ba662010-03-17 02:15:07 +0000443 dimm03++;
Keith Huia8380fc2017-12-04 00:05:56 -0500444 else
Keith Huib48ba662010-03-17 02:15:07 +0000445 dimm47++;
Keith Huia8380fc2017-12-04 00:05:56 -0500446
447 drb = reg;
Keith Huib48ba662010-03-17 02:15:07 +0000448 }
449 }
450
Julius Wernercd49cce2019-03-05 16:53:33 -0800451 if (CONFIG(SDRAMPWR_4DIMM)) {
Keith Huia8380fc2017-12-04 00:05:56 -0500452 /*
453 * For a 4 DIMM board, based on ASUS P2B-LS mainboard.
Keith Huib48ba662010-03-17 02:15:07 +0000454 *
Keith Huia8380fc2017-12-04 00:05:56 -0500455 * There are four main conditions to check when programming
456 * DRAM buffer frequency and strength:
Keith Huib48ba662010-03-17 02:15:07 +0000457 *
458 * a: >2 rows populated across DIMM0,1
459 * b: >2 rows populated across DIMM2,3
460 * c: >4 rows populated across all DIMM slots
461 * and either one of:
462 * 1: NBXCFG[13] strapped as 100MHz, or
463 * 6: NBXCFG[13] strapped as 66MHz
464 *
465 * CKE0/FENA ----------------------------------------------------------+
Keith Huia8380fc2017-12-04 00:05:56 -0500466 * CKE1/GCKE ----------------------[ MBFS ]---------------------+|
467 * DQMA/CASA[764320]# -------------[ 0 = 66MHz ]--------------------+||
468 * DQMB1/CASB1# (Fixed for 66MHz) -[ 1 = 100MHz ]-------------------+|||
469 * DQMB5/CASB5# (Fixed for 66MHz) ---------------------------------+||||
470 * DQMA1/CASA1# (Fixed for 66MHz) --------------------------------+|||||
471 * DQMA5/CASA5# (Fixed for 66MHz) -------------------------------+||||||
472 * CSA[5:0]#,CSB[5:0]# ------------------------------------++++++|||||||
473 * CS[B7,A7,B6,A6]#/CKE[5342] -------------------------++++|||||||||||||
474 * MECC[7:0] #2/#1 ----------------------------------++|||||||||||||||||
475 * MD[63:0] #2/#1 ---------------------------------++|||||||||||||||||||
476 * MAB[12:11,9:0]#,MAB[13,10],WEB#,SRASB#,SCASB# -+|||||||||||||||||||||
477 * MAA[13:0],WEA#,SRASA#,SCASA# -----------------+||||||||||||||||||||||
478 * Reserved ------------------------------------+|||||||||||||||||||||||
479 * ||||||||||||||||||||||||
480 * 3 32 21 10 0 * 2 21 10 0
481 * 9876543210987654321098765432109876543210 * 321098765432109876543210
482 * 10------------------------1010---------- a -1---------------11-----
483 * 11------------------------1111---------- !a -0---------------00-----
484 * --10--------------------------1010------ b --1----------------11---
485 * --11--------------------------1111------ !b --0----------------00---
486 * ----------------------------------1100-- c ----------------------1-
487 * ----------------------------------1011-- !c ----------------------0-
488 * ----1010101000000000000000------------00 1 ---11111111111111----1-0
489 * ----000000000000000000000010101010----00 6 ---1111111111111100000-0
490 * | | | | | | | | | | ||||||| | | | | | |
491 * | | | | | | | | | | ||||||| | | | | | +- CKE0/FENA
492 * | | | | | | | | | | ||||||| | | | | +--- CKE1/GCKE
493 * | | | | | | | | | | ||||||| | | | +----- DQMA/CASA[764320]#
494 * | | | | | | | | | | ||||||| | | +------- DQMB1/CASB1# (66MHz: 2x)
495 * | | | | | | | | | | ||||||| | +--------- DQMB5/CASB5# (66MHz: 2x)
496 * | | | | | | | | | | ||||||| +----------- DQMA1/CASA1# (66MHz: 2x)
497 * | | | | | | | | | | ||||||+------------- DQMA5/CASA5# (66MHz: 2x)
498 * | | | | | | | | | | ++++++-------------- CSA0-5#,CSB0-5# (1x)
499 * | | | | | | | | | +--------------------- CSA6#/CKE2
500 * | | | | | | | | +---[ MBSC ]------ CSB6#/CKE4
501 * | | | | | | | +-----[ 00 = 1x ]------ CSA7#/CKE3
502 * | | | | | | +-------[ 01 invalid ]------ CSB7#/CKE5
503 * | | | | | +---------[ 10 = 2x ]------ MECC[7:0] #1
504 * | | | | +-----------[ 11 = 3x ]------ MECC[7:0] #2
505 * | | | +--------------------------------- MD[63:0] #1
506 * | | +----------------------------------- MD[63:0] #2
507 * | +------------------ MAB[12:11,9:0]#,MAB[13,10],WEB#,SRASB#,SCASB#
508 * +------------------------------------- MAA[13:0],WEA#,SRASA#,SCASA#
509 */
510 unsigned int fsb;
511
512 mbsc0 = 0xa0;
513 mbsc1 = 0x002a;
514 mbfs1 = 0xff;
515 mbfs2 = 0x1f;
516 if (pci_read_config8(NB, NBXCFG + 1) & 0x30) {
517 fsb = 66;
518 mbsc3 = 0xa000;
519 mbfs0 = 0x80;
520 } else {
521 fsb = 100;
522 mbsc3 = 0xaaa0;
523 mbfs0 = 0x84;
524 }
525 if (dimm03 > 2) {
526 mbfs2 |= 0x40;
527 if (fsb == 100)
528 mbfs0 |= 0x60;
529 } else {
530 mbsc3 |= 0xc000;
531 if (fsb == 100)
532 mbsc1 |= 0x003c;
533 }
534 if (dimm47 > 2) {
535 mbfs2 |= 0x20;
536 if (fsb == 100)
537 mbfs0 |= 0x18;
538 } else {
539 mbsc3 |= 0x3000;
540 if (fsb == 100) {
541 mbsc1 |= 0x0003;
542 mbsc0 |= 0xc0;
543 }
544 }
545 if ((dimm03 + dimm47) > 4) {
546 mbsc0 |= 0x30;
547 mbfs0 |= 0x02;
548 } else {
549 mbsc0 |= 0x2c;
550 }
551 } else {
552 /*
553 * For a 3 DIMM board, based on ASUS P2B mainboard.
554 *
555 * There are two main conditions to check when programming DRAM buffer
556 * frequency and strength:
557 *
558 * a: >2 rows populated across DIMM0,1
559 * c: >4 rows populated across all DIMM slots
560 *
561 * CKE0 ---------------------------------------------------------------+
562 * CKE1 ------------------------[ MBFS ]------------------------+|
Keith Huib48ba662010-03-17 02:15:07 +0000563 * DQMA/CASA[764320]# ----------[ 0 = 66MHz ]-----------------------+||
564 * DQMB1/CASB1# ----------------[ 1 = 100MHz ]----------------------+|||
565 * DQMB5/CASB5# ---------------------------------------------------+||||
566 * DQMA1/CASA1# --------------------------------------------------+|||||
567 * DQMA5/CASA5# -------------------------------------------------+||||||
568 * CSA0-5#,CSB0-5# ----------------------------------------++++++|||||||
Keith Huia8380fc2017-12-04 00:05:56 -0500569 * CS[B7,A7,B6,A6]#/CKE[5342] -------------------------++++|||||||||||||
Keith Huib48ba662010-03-17 02:15:07 +0000570 * MECC[7:0] #2/#1 (100MHz) -------------------------++|||||||||||||||||
571 * MD[63:0] #2/#1 (100MHz) ------------------------++|||||||||||||||||||
572 * MAB[12:11,9:0]#,MAB[13,10],WEB#,SRASB#,SCASB# -+|||||||||||||||||||||
573 * MAA[13:0],WEA#,SRASA#,SCASA# -----------------+||||||||||||||||||||||
574 * Reserved ------------------------------------+|||||||||||||||||||||||
575 * ||||||||||||||||||||||||
Keith Huia8380fc2017-12-04 00:05:56 -0500576 * 3 32 21 10 0 * 2 21 10 0
577 * 9876543210987654321098765432109876543210 * 321098765432109876543210
578 * 10------------------------1111---------- a -1----------------------
579 * 11------------------------1010---------- !a -0----------------------
580 * --110000000010101010111111----1010--1010 * --01111000000000000000-0
581 * ----------------------------------11---- c ----------------------1-
582 * ----------------------------------10---- !c ----------------------0-
583 * | | | | | | | | | | ||||||| | | | | | |
584 * | | | | | | | | | | ||||||| | | | | | +- CKE0
585 * | | | | | | | | | | ||||||| | | | | +--- CKE1
586 * | | | | | | | | | | ||||||| | | | +----- DQMA/CASA[764320]#
587 * | | | | | | | | | | ||||||| | | +------- DQMB1/CASB1#
588 * | | | | | | | | | | ||||||| | +--------- DQMB5/CASB5#
589 * | | | | | | | | | | ||||||| +----------- DQMA1/CASA1#
590 * | | | | | | | | | | ||||||+------------- DQMA5/CASA5#
591 * | | | | | | | | | | ++++++-------------- CSA0-5#,CSB0-5# (2x)
592 * | | | | | | | | | +--------------------- CSA6#/CKE2
593 * | | | | | | | | +---[ MBSC ]------ CSB6#/CKE4
594 * | | | | | | | +-----[ 00 = 1x ]------ CSA7#/CKE3
595 * | | | | | | +-------[ 01 invalid ]------ CSB7#/CKE5
596 * | | | | | +---------[ 10 = 2x ]------ MECC[7:0] #1 (1x)
597 * | | | | +-----------[ 11 = 3x ]------ MECC[7:0] #2 (1x)
598 * | | | +--------------------------------- MD[63:0] #1 (1x)
599 * | | +----------------------------------- MD[63:0] #2 (1x)
600 * | +------------------ MAB[12:11,9:0]#,MAB[13,10],WEB#,SRASB#,SCASB#
601 * +------------------------------------- MAA[13:0],WEA#,SRASA#,SCASA#
Keith Huib48ba662010-03-17 02:15:07 +0000602 */
Anders Jenbo0e1e8062010-04-27 06:35:31 +0000603
Keith Huia8380fc2017-12-04 00:05:56 -0500604 mbsc0 = 0xaa;
605 mbsc1 = 0xafea;
606 mbsc3 = 0xb00a;
607 mbfs0 = 0x00;
608 mbfs1 = 0x00;
609 mbfs2 = 0x1e;
Anders Jenbo0e1e8062010-04-27 06:35:31 +0000610
Keith Huia8380fc2017-12-04 00:05:56 -0500611 if (dimm03 > 2) {
612 mbsc1 |= 0x003c;
613 mbfs2 |= 0x40;
614 } else {
615 mbsc3 |= 0xc000;
Keith Huib48ba662010-03-17 02:15:07 +0000616 }
Keith Huia8380fc2017-12-04 00:05:56 -0500617 if ((dimm03 + dimm47) > 4) {
618 mbsc0 |= 0x30;
619 mbfs0 |= 0x02;
Keith Huib48ba662010-03-17 02:15:07 +0000620 }
621 }
Keith Huib48ba662010-03-17 02:15:07 +0000622
623 pci_write_config8(NB, MBSC + 0, mbsc0);
Keith Huia8380fc2017-12-04 00:05:56 -0500624 pci_write_config16(NB, MBSC + 1, mbsc1);
625 pci_write_config16(NB, MBSC + 3, mbsc3);
626 pci_write_config16(NB, MBFS + 0, mbfs1 << 8 | mbfs0);
Keith Huib48ba662010-03-17 02:15:07 +0000627 pci_write_config8(NB, MBFS + 2, mbfs2);
Keith Hui59356ca2010-03-06 18:16:25 +0000628}
629
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000630/*-----------------------------------------------------------------------------
Martin Roth128c1042016-11-18 09:29:03 -0700631DIMM-independent configuration functions.
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000632-----------------------------------------------------------------------------*/
Richard Smithcb8eab42006-07-24 04:25:47 +0000633
Uwe Hermann1683cef2008-11-27 00:47:07 +0000634static void spd_enable_refresh(void)
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000635{
636 int i, value;
637 uint8_t reg;
638
Uwe Hermann1683cef2008-11-27 00:47:07 +0000639 reg = pci_read_config8(NB, DRAMC);
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000640
641 for (i = 0; i < DIMM_SOCKETS; i++) {
Kyösti Mälkki3f882faf2020-01-07 12:10:02 +0200642 value = smbus_read_byte(DIMM0 + i, SPD_REFRESH);
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000643 if (value < 0)
644 continue;
645 reg = (reg & 0xf8) | refresh_rate_map[(value & 0x7f)];
646
Keith Hui09f5a742010-12-23 17:12:03 +0000647 PRINT_DEBUG(" Enabling refresh (DRAMC = 0x%02x) for DIMM %02x\n", reg, i);
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000648 }
649
Uwe Hermann1683cef2008-11-27 00:47:07 +0000650 pci_write_config8(NB, DRAMC, reg);
Richard Smithcb8eab42006-07-24 04:25:47 +0000651}
652
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000653/*-----------------------------------------------------------------------------
654Public interface.
655-----------------------------------------------------------------------------*/
656
Kyösti Mälkki7a955752020-01-07 12:18:24 +0200657static void sdram_set_registers(void)
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000658{
659 int i, max;
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000660
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000661 PRINT_DEBUG("Northbridge prior to SDRAM init:\n");
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000662 DUMPNORTH();
663
Carl-Daniel Hailfinger2ee67792008-10-01 12:52:52 +0000664 max = ARRAY_SIZE(register_values);
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000665
Uwe Hermannf5a6fd22007-05-27 23:31:31 +0000666 /* Set registers as specified in the register_values[] array. */
Keith Hui8bd784e2020-04-05 14:54:22 -0400667 for (i = 0; i < max; i += 2)
668 pci_write_config8(NB, register_values[i], register_values[i + 1]);
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000669}
670
Keith Hui59356ca2010-03-06 18:16:25 +0000671struct dimm_size {
Keith Hui09f5a742010-12-23 17:12:03 +0000672 u32 side1;
673 u32 side2;
Keith Hui59356ca2010-03-06 18:16:25 +0000674};
675
676static struct dimm_size spd_get_dimm_size(unsigned int device)
677{
678 struct dimm_size sz;
679 int i, module_density, dimm_banks;
680 sz.side1 = 0;
Kyösti Mälkki3f882faf2020-01-07 12:10:02 +0200681 module_density = smbus_read_byte(device, SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
682 dimm_banks = smbus_read_byte(device, SPD_NUM_DIMM_BANKS);
Keith Hui59356ca2010-03-06 18:16:25 +0000683
684 /* Find the size of side1. */
685 /* Find the larger value. The larger value is always side1. */
686 for (i = 512; i >= 0; i >>= 1) {
687 if ((module_density & i) == i) {
688 sz.side1 = i;
689 break;
690 }
691 }
692
693 /* Set to 0 in case it's single sided. */
694 sz.side2 = 0;
695
696 /* Test if it's a dual-sided DIMM. */
697 if (dimm_banks > 1) {
698 /* Test if there's a second value. If so it's asymmetrical. */
699 if (module_density != i) {
700 /*
701 * Find second value, picking up where we left off.
702 * i >>= 1 done initially to make sure we don't get
703 * the same value again.
704 */
705 for (i >>= 1; i >= 0; i >>= 1) {
706 if (module_density == (sz.side1 | i)) {
707 sz.side2 = i;
708 break;
709 }
710 }
711 /* If not, it's symmetrical. */
712 } else {
713 sz.side2 = sz.side1;
714 }
715 }
716
717 /*
718 * SPD byte 31 is the memory size divided by 4 so we
Martin Roth128c1042016-11-18 09:29:03 -0700719 * need to multiply by 4 to get the total size.
Keith Hui59356ca2010-03-06 18:16:25 +0000720 */
721 sz.side1 *= 4;
722 sz.side2 *= 4;
723
Keith Huia8380fc2017-12-04 00:05:56 -0500724 /*
725 * It is possible to partially use larger than supported
Anders Jenbo771b0e42010-04-27 08:45:30 +0000726 * modules by setting them to a supported size.
727 */
Elyes HAOUAS12df9502016-08-23 21:29:48 +0200728 if (sz.side1 > 128) {
Keith Hui09f5a742010-12-23 17:12:03 +0000729 PRINT_DEBUG("Side1 was %dMB but only 128MB will be used.\n",
730 sz.side1);
Anders Jenbo771b0e42010-04-27 08:45:30 +0000731 sz.side1 = 128;
732
Elyes HAOUAS12df9502016-08-23 21:29:48 +0200733 if (sz.side2 > 128) {
Keith Hui09f5a742010-12-23 17:12:03 +0000734 PRINT_DEBUG("Side2 was %dMB but only 128MB will be used.\n",
735 sz.side2);
Anders Jenbo771b0e42010-04-27 08:45:30 +0000736 sz.side2 = 128;
737 }
738 }
739
Keith Hui59356ca2010-03-06 18:16:25 +0000740 return sz;
741}
742/*
743 * Sets DRAM attributes one DIMM at a time, based on SPD data.
744 * Northbridge settings that are set: NBXCFG[31:24], DRB0-DRB7, RPS, DRAMC.
745 */
746static void set_dram_row_attributes(void)
747{
Keith Huie089a3f2011-08-02 22:28:14 -0400748 int i, dra, drb, col, width, value, rps;
Keith Hui59356ca2010-03-06 18:16:25 +0000749 u8 bpr; /* Top 8 bits of PGPOL */
Keith Huie089a3f2011-08-02 22:28:14 -0400750 u8 nbxecc = 0; /* NBXCFG[31:24] */
751 u8 edo, sd, regsd; /* EDO, SDRAM, registered SDRAM */
Keith Hui59356ca2010-03-06 18:16:25 +0000752
Keith Huie089a3f2011-08-02 22:28:14 -0400753 edo = 0;
754 sd = 0;
755 regsd = 1;
Keith Hui59356ca2010-03-06 18:16:25 +0000756 rps = 0;
757 drb = 0;
758 bpr = 0;
Keith Hui59356ca2010-03-06 18:16:25 +0000759
760 for (i = 0; i < DIMM_SOCKETS; i++) {
761 unsigned int device;
Uwe Hermannd773fd32010-11-20 20:23:08 +0000762 device = DIMM0 + i;
Keith Hui59356ca2010-03-06 18:16:25 +0000763 bpr >>= 2;
Keith Huie089a3f2011-08-02 22:28:14 -0400764 nbxecc >>= 2;
Keith Hui59356ca2010-03-06 18:16:25 +0000765
766 /* First check if a DIMM is actually present. */
Kyösti Mälkki3f882faf2020-01-07 12:10:02 +0200767 value = smbus_read_byte(device, SPD_MEMORY_TYPE);
Keith Hui59356ca2010-03-06 18:16:25 +0000768 /* This is 440BX! We do EDO too! */
769 if (value == SPD_MEMORY_TYPE_EDO
770 || value == SPD_MEMORY_TYPE_SDRAM) {
771
Keith Hui59356ca2010-03-06 18:16:25 +0000772 if (value == SPD_MEMORY_TYPE_EDO) {
Keith Huie089a3f2011-08-02 22:28:14 -0400773 edo = 1;
Anders Jenbo0e1e8062010-04-27 06:35:31 +0000774 } else if (value == SPD_MEMORY_TYPE_SDRAM) {
Keith Huie089a3f2011-08-02 22:28:14 -0400775 sd = 1;
Keith Hui59356ca2010-03-06 18:16:25 +0000776 }
Keith Hui09f5a742010-12-23 17:12:03 +0000777 PRINT_DEBUG("Found DIMM in slot %d\n", i);
Keith Hui59356ca2010-03-06 18:16:25 +0000778
Keith Huie089a3f2011-08-02 22:28:14 -0400779 if (edo && sd) {
Stefan Reinauer65b72ab2015-01-05 12:59:54 -0800780 printk(BIOS_ERR, "Mixing EDO/SDRAM unsupported!\n");
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000781 die("HALT\n");
Keith Hui59356ca2010-03-06 18:16:25 +0000782 }
783
784 /* "DRA" is our RPS for the two rows on this DIMM. */
785 dra = 0;
786
787 /* Columns */
Kyösti Mälkki3f882faf2020-01-07 12:10:02 +0200788 col = smbus_read_byte(device, SPD_NUM_COLUMNS);
Keith Hui59356ca2010-03-06 18:16:25 +0000789
790 /*
791 * Is this an ECC DIMM? Actually will be a 2 if so.
792 * TODO: Other register than NBXCFG also needs this
793 * ECC information.
794 */
Kyösti Mälkki3f882faf2020-01-07 12:10:02 +0200795 value = smbus_read_byte(device, SPD_DIMM_CONFIG_TYPE);
Keith Hui59356ca2010-03-06 18:16:25 +0000796
797 /* Data width */
Kyösti Mälkki3f882faf2020-01-07 12:10:02 +0200798 width = smbus_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB);
Anders Jenbo0e1e8062010-04-27 06:35:31 +0000799
Keith Hui59356ca2010-03-06 18:16:25 +0000800 /* Exclude error checking data width from page size calculations */
Keith Huie089a3f2011-08-02 22:28:14 -0400801 if (value) {
Kyösti Mälkki3f882faf2020-01-07 12:10:02 +0200802 value = smbus_read_byte(device,
Keith Hui59356ca2010-03-06 18:16:25 +0000803 SPD_ERROR_CHECKING_SDRAM_WIDTH);
804 width -= value;
805 /* ### ECC */
806 /* Clear top 2 bits to help set up NBXCFG. */
Keith Huie089a3f2011-08-02 22:28:14 -0400807 nbxecc &= 0x3f;
Keith Hui59356ca2010-03-06 18:16:25 +0000808 } else {
809 /* Without ECC, top 2 bits should be 11. */
Keith Huie089a3f2011-08-02 22:28:14 -0400810 nbxecc |= 0xc0;
Keith Hui59356ca2010-03-06 18:16:25 +0000811 }
812
Keith Huie089a3f2011-08-02 22:28:14 -0400813 /* If any installed DIMM is *not* registered, this system cannot be
814 * configured for registered SDRAM.
815 * By registered, only the address and control lines need to be, which
816 * we can tell by reading SPD byte 21, bit 1.
817 */
Kyösti Mälkki3f882faf2020-01-07 12:10:02 +0200818 value = smbus_read_byte(device, SPD_MODULE_ATTRIBUTES);
Keith Huie089a3f2011-08-02 22:28:14 -0400819
820 PRINT_DEBUG("DIMM is ");
821 if ((value & MODULE_REGISTERED) == 0) {
822 regsd = 0;
823 PRINT_DEBUG("not ");
824 }
825 PRINT_DEBUG("registered\n");
826
Keith Hui59356ca2010-03-06 18:16:25 +0000827 /* Calculate page size in bits. */
828 value = ((1 << col) * width);
829
830 /* Convert to KB. */
831 dra = (value >> 13);
832
833 /* Number of banks of DIMM (single or double sided). */
Kyösti Mälkki3f882faf2020-01-07 12:10:02 +0200834 value = smbus_read_byte(device, SPD_NUM_DIMM_BANKS);
Keith Hui59356ca2010-03-06 18:16:25 +0000835
836 /* Once we have dra, col is done and can be reused.
837 * So it's reused for number of banks.
838 */
Kyösti Mälkki3f882faf2020-01-07 12:10:02 +0200839 col = smbus_read_byte(device, SPD_NUM_BANKS_PER_SDRAM);
Keith Hui59356ca2010-03-06 18:16:25 +0000840
841 if (value == 1) {
842 /*
843 * Second bank of 1-bank DIMMs "doesn't have
844 * ECC" - or anything.
845 */
Keith Hui59356ca2010-03-06 18:16:25 +0000846 if (dra == 2) {
847 dra = 0x0; /* 2KB */
848 } else if (dra == 4) {
849 dra = 0x1; /* 4KB */
850 } else if (dra == 8) {
851 dra = 0x2; /* 8KB */
Anders Jenbo771b0e42010-04-27 08:45:30 +0000852 } else if (dra >= 16) {
853 /* Page sizes larger than supported are
854 * set to 8KB to use module partially.
855 */
856 PRINT_DEBUG("Page size forced to 8KB.\n");
857 dra = 0x2; /* 8KB */
Keith Hui59356ca2010-03-06 18:16:25 +0000858 } else {
859 dra = -1;
860 }
861 /*
862 * Sets a flag in PGPOL[BPR] if this DIMM has
863 * 4 banks per row.
864 */
865 if (col == 4)
866 bpr |= 0x40;
867 } else if (value == 2) {
868 if (dra == 2) {
869 dra = 0x0; /* 2KB */
870 } else if (dra == 4) {
871 dra = 0x05; /* 4KB */
872 } else if (dra == 8) {
873 dra = 0x0a; /* 8KB */
Anders Jenbo771b0e42010-04-27 08:45:30 +0000874 } else if (dra >= 16) {
875 /* Ditto */
876 PRINT_DEBUG("Page size forced to 8KB.\n");
877 dra = 0x0a; /* 8KB */
Keith Hui59356ca2010-03-06 18:16:25 +0000878 } else {
879 dra = -1;
880 }
881 /* Ditto */
882 if (col == 4)
883 bpr |= 0xc0;
884 } else {
Stefan Reinauer65b72ab2015-01-05 12:59:54 -0800885 printk(BIOS_ERR, "# of banks of DIMM unsupported!\n");
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000886 die("HALT\n");
Keith Hui59356ca2010-03-06 18:16:25 +0000887 }
888 if (dra == -1) {
Stefan Reinauer65b72ab2015-01-05 12:59:54 -0800889 printk(BIOS_ERR, "Page size not supported\n");
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000890 die("HALT\n");
Keith Hui59356ca2010-03-06 18:16:25 +0000891 }
892
893 /*
894 * 440BX supports asymmetrical dual-sided DIMMs,
895 * but can't handle DIMMs smaller than 8MB per
Anders Jenbo771b0e42010-04-27 08:45:30 +0000896 * side.
Keith Hui59356ca2010-03-06 18:16:25 +0000897 */
898 struct dimm_size sz = spd_get_dimm_size(device);
899 if ((sz.side1 < 8)) {
Stefan Reinauer65b72ab2015-01-05 12:59:54 -0800900 printk(BIOS_ERR, "DIMMs smaller than 8MB per side\n"
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000901 "are not supported on this NB.\n");
902 die("HALT\n");
Keith Hui59356ca2010-03-06 18:16:25 +0000903 }
Keith Hui59356ca2010-03-06 18:16:25 +0000904
905 /* Divide size by 8 to set up the DRB registers. */
906 drb += (sz.side1 / 8);
907
908 /*
909 * Build the DRB for the next row in MSB so it gets
910 * placed in DRB[n+1] where it belongs when written
911 * as a 16-bit word.
912 */
913 drb &= 0xff;
914 drb |= (drb + (sz.side2 / 8)) << 8;
915 } else {
Keith Hui59356ca2010-03-06 18:16:25 +0000916 /* If there's no DIMM in the slot, set dra to 0x00. */
917 dra = 0x00;
Keith Hui59356ca2010-03-06 18:16:25 +0000918 /* Still have to propagate DRB over. */
919 drb &= 0xff;
920 drb |= (drb << 8);
921 }
922
923 pci_write_config16(NB, DRB + (2 * i), drb);
Keith Hui59356ca2010-03-06 18:16:25 +0000924
925 /* Brings the upper DRB back down to be base for
926 * DRB calculations for the next two rows.
927 */
928 drb >>= 8;
929
930 rps |= (dra & 0x0f) << (i * 4);
Keith Hui59356ca2010-03-06 18:16:25 +0000931 }
932
933 /* Set paging policy register. */
934 pci_write_config8(NB, PGPOL + 1, bpr);
Keith Hui09f5a742010-12-23 17:12:03 +0000935 PRINT_DEBUG("PGPOL[BPR] has been set to 0x%02x\n", bpr);
Keith Hui59356ca2010-03-06 18:16:25 +0000936
937 /* Set DRAM row page size register. */
938 pci_write_config16(NB, RPS, rps);
Keith Hui09f5a742010-12-23 17:12:03 +0000939 PRINT_DEBUG("RPS has been set to 0x%04x\n", rps);
Keith Hui59356ca2010-03-06 18:16:25 +0000940
941 /* ### ECC */
942 pci_write_config8(NB, NBXCFG + 3, nbxecc);
Keith Hui09f5a742010-12-23 17:12:03 +0000943 PRINT_DEBUG("NBXECC[31:24] has been set to 0x%02x\n", nbxecc);
Keith Hui59356ca2010-03-06 18:16:25 +0000944
Keith Huie089a3f2011-08-02 22:28:14 -0400945 /* Set DRAMC[4:3] to proper memory type (EDO/SDRAM/Registered SDRAM). */
Keith Hui59356ca2010-03-06 18:16:25 +0000946
Keith Huie089a3f2011-08-02 22:28:14 -0400947 /* i will be used to set DRAMC[4:3]. */
948 if (regsd && sd) {
949 i = 0x10; // Registered SDRAM
950 } else if (sd) {
951 i = 0x08; // SDRAM
952 } else {
953 i = 0; // EDO
954 }
955
Keith Hui59356ca2010-03-06 18:16:25 +0000956 value = pci_read_config8(NB, DRAMC) & 0xe7;
Keith Huie089a3f2011-08-02 22:28:14 -0400957 value |= i;
Keith Hui59356ca2010-03-06 18:16:25 +0000958 pci_write_config8(NB, DRAMC, value);
Keith Hui09f5a742010-12-23 17:12:03 +0000959 PRINT_DEBUG("DRAMC has been set to 0x%02x\n", value);
Keith Hui59356ca2010-03-06 18:16:25 +0000960}
961
Kyösti Mälkki7a955752020-01-07 12:18:24 +0200962static void sdram_set_spd_registers(void)
Richard Smithcb8eab42006-07-24 04:25:47 +0000963{
Keith Hui59356ca2010-03-06 18:16:25 +0000964 /* Setup DRAM row boundary registers and other attributes. */
965 set_dram_row_attributes();
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000966
Keith Huidf35cdc2010-09-20 23:41:37 +0000967 /* Setup DRAM buffer strength. */
Keith Hui59356ca2010-03-06 18:16:25 +0000968 set_dram_buffer_strength();
Richard Smithcb8eab42006-07-24 04:25:47 +0000969}
970
Kyösti Mälkki7a955752020-01-07 12:18:24 +0200971static void sdram_enable(void)
Richard Smithcb8eab42006-07-24 04:25:47 +0000972{
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000973 int i;
Richard Smithcb8eab42006-07-24 04:25:47 +0000974
Uwe Hermann861f9642007-05-28 14:37:06 +0000975 /* 0. Wait until power/voltages and clocks are stable (200us). */
976 udelay(200);
Richard Smithcb8eab42006-07-24 04:25:47 +0000977
Uwe Hermann861f9642007-05-28 14:37:06 +0000978 /* 1. Apply NOP. Wait 200 clock cycles (200us should do). */
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000979 PRINT_DEBUG("RAM Enable 1: Apply NOP\n");
Uwe Hermann8b643cea2008-12-09 16:36:12 +0000980 do_ram_command(RAM_COMMAND_NOP);
Uwe Hermann861f9642007-05-28 14:37:06 +0000981 udelay(200);
Richard Smithcb8eab42006-07-24 04:25:47 +0000982
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000983 /* 2. Precharge all. Wait tRP. */
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000984 PRINT_DEBUG("RAM Enable 2: Precharge all\n");
Uwe Hermann8b643cea2008-12-09 16:36:12 +0000985 do_ram_command(RAM_COMMAND_PRECHARGE);
Uwe Hermann861f9642007-05-28 14:37:06 +0000986 udelay(1);
Richard Smithcb8eab42006-07-24 04:25:47 +0000987
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000988 /* 3. Perform 8 refresh cycles. Wait tRC each time. */
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000989 PRINT_DEBUG("RAM Enable 3: CBR\n");
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000990 for (i = 0; i < 8; i++) {
Uwe Hermann8b643cea2008-12-09 16:36:12 +0000991 do_ram_command(RAM_COMMAND_CBR);
Uwe Hermann861f9642007-05-28 14:37:06 +0000992 udelay(1);
Richard Smithcb8eab42006-07-24 04:25:47 +0000993 }
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000994
995 /* 4. Mode register set. Wait two memory cycles. */
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000996 PRINT_DEBUG("RAM Enable 4: Mode register set\n");
Uwe Hermann8b643cea2008-12-09 16:36:12 +0000997 do_ram_command(RAM_COMMAND_MRS);
Uwe Hermann861f9642007-05-28 14:37:06 +0000998 udelay(2);
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000999
1000 /* 5. Normal operation. */
Stefan Reinauer64ed2b72010-03-31 14:47:43 +00001001 PRINT_DEBUG("RAM Enable 5: Normal operation\n");
Uwe Hermann8b643cea2008-12-09 16:36:12 +00001002 do_ram_command(RAM_COMMAND_NORMAL);
Uwe Hermann861f9642007-05-28 14:37:06 +00001003 udelay(1);
Uwe Hermann1a9c8922007-04-01 17:24:03 +00001004
1005 /* 6. Finally enable refresh. */
Stefan Reinauer64ed2b72010-03-31 14:47:43 +00001006 PRINT_DEBUG("RAM Enable 6: Enable refresh\n");
Keith Huie9b3fd12020-01-12 18:41:26 -05001007 pci_write_config8(NB, PMCR, 0x10);
Uwe Hermann1683cef2008-11-27 00:47:07 +00001008 spd_enable_refresh();
Uwe Hermann861f9642007-05-28 14:37:06 +00001009 udelay(1);
Uwe Hermann1a9c8922007-04-01 17:24:03 +00001010
Stefan Reinauer64ed2b72010-03-31 14:47:43 +00001011 PRINT_DEBUG("Northbridge following SDRAM init:\n");
Uwe Hermann1a9c8922007-04-01 17:24:03 +00001012 DUMPNORTH();
Richard Smithcb8eab42006-07-24 04:25:47 +00001013}
Keith Hui078e3242017-07-20 21:14:21 -04001014
Kyösti Mälkki93e08c72020-01-07 15:17:48 +02001015/* Implemented under mainboard. */
1016void __weak enable_spd(void) { }
1017void __weak disable_spd(void) { }
1018
Keith Hui078e3242017-07-20 21:14:21 -04001019void sdram_initialize(void)
1020{
Keith Huid6f259e2020-01-12 18:38:28 -05001021 timestamp_add_now(TS_BEFORE_INITRAM);
Kyösti Mälkki93e08c72020-01-07 15:17:48 +02001022 enable_spd();
1023
Keith Hui078e3242017-07-20 21:14:21 -04001024 dump_spd_registers();
1025 sdram_set_registers();
1026 sdram_set_spd_registers();
1027 sdram_enable();
Kyösti Mälkki93e08c72020-01-07 15:17:48 +02001028
1029 disable_spd();
Keith Huid6f259e2020-01-12 18:38:28 -05001030 timestamp_add_now(TS_AFTER_INITRAM);
Martin Rothe1695e22017-07-24 11:28:50 -06001031}