blob: 26e01563b24e6c23743099707eee8f0949c46846 [file] [log] [blame]
Aaron Durbine18d68f2013-10-24 00:05:31 -05001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2008-2009 coresystems GmbH
5 * Copyright (C) 2013 Google Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
Patrick Georgib890a122015-03-26 15:17:45 +010018 * Foundation, Inc.
Aaron Durbine18d68f2013-10-24 00:05:31 -050019 */
20
21#include <stdint.h>
22#include <arch/io.h>
Kein Yuan35110232014-02-22 12:26:55 -080023#include <arch/acpi.h>
Aaron Durbin4177db52014-02-05 14:55:26 -060024#include <bootstate.h>
Shawn Nematbakhsh51d787a2014-01-16 17:52:21 -080025#include <cbmem.h>
Aaron Durbind7bc23a2013-10-29 16:37:10 -050026#include <console/console.h>
Aaron Durbin4177db52014-02-05 14:55:26 -060027#include <cpu/x86/smm.h>
Aaron Durbine18d68f2013-10-24 00:05:31 -050028#include <device/device.h>
29#include <device/pci.h>
30#include <device/pci_ids.h>
Shawn Nematbakhsh51d787a2014-01-16 17:52:21 -080031#include <pc80/mc146818rtc.h>
Kein Yuan35110232014-02-22 12:26:55 -080032#include <drivers/uart/uart8250reg.h>
Aaron Durbine18d68f2013-10-24 00:05:31 -050033
Julius Werner18ea2d32014-10-07 16:42:17 -070034#include <soc/iomap.h>
35#include <soc/irq.h>
36#include <soc/lpc.h>
37#include <soc/nvs.h>
38#include <soc/pci_devs.h>
39#include <soc/pmc.h>
40#include <soc/ramstage.h>
41#include <soc/spi.h>
Shawn Nematbakhsh51d787a2014-01-16 17:52:21 -080042#include "chip.h"
Vladimir Serbinenko7fb149d2014-10-08 22:56:27 +020043#include <arch/acpi.h>
44#include <arch/acpigen.h>
45#include <cpu/cpu.h>
Aaron Durbine18d68f2013-10-24 00:05:31 -050046
47static inline void
48add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size)
49{
50 mmio_resource(dev, i, addr >> 10, size >> 10);
51}
52
53static void sc_add_mmio_resources(device_t dev)
54{
Duncan Laurie7fbe20b2013-11-04 17:00:22 -080055 add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE);
56 add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE);
57 add_mmio_resource(dev, IOBASE, IO_BASE_ADDRESS, IO_BASE_SIZE);
58 add_mmio_resource(dev, IBASE, ILB_BASE_ADDRESS, ILB_BASE_SIZE);
59 add_mmio_resource(dev, SBASE, SPI_BASE_ADDRESS, SPI_BASE_SIZE);
60 add_mmio_resource(dev, MPBASE, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE);
61 add_mmio_resource(dev, PUBASE, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE);
62 add_mmio_resource(dev, RCBA, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE);
Aaron Durbine18d68f2013-10-24 00:05:31 -050063}
64
65/* Default IO range claimed by the LPC device. The upper bound is exclusive. */
66#define LPC_DEFAULT_IO_RANGE_LOWER 0
67#define LPC_DEFAULT_IO_RANGE_UPPER 0x1000
68
69static inline int io_range_in_default(int base, int size)
70{
71 /* Does it start above the range? */
72 if (base >= LPC_DEFAULT_IO_RANGE_UPPER)
73 return 0;
74
75 /* Is it entirely contained? */
76 if (base >= LPC_DEFAULT_IO_RANGE_LOWER &&
77 (base + size) < LPC_DEFAULT_IO_RANGE_UPPER)
78 return 1;
79
80 /* This will return not in range for partial overlaps. */
81 return 0;
82}
83
84/*
85 * Note: this function assumes there is no overlap with the default LPC device's
86 * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER.
87 */
88static void sc_add_io_resource(device_t dev, int base, int size, int index)
89{
90 struct resource *res;
91
92 if (io_range_in_default(base, size))
93 return;
94
95 res = new_resource(dev, index);
96 res->base = base;
97 res->size = size;
98 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
99}
100
101static void sc_add_io_resources(device_t dev)
102{
103 struct resource *res;
104
105 /* Add the default claimed IO range for the LPC device. */
106 res = new_resource(dev, 0);
107 res->base = LPC_DEFAULT_IO_RANGE_LOWER;
108 res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER;
109 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
110
111 /* GPIO */
112 sc_add_io_resource(dev, GPIO_BASE_ADDRESS, 256, GBASE);
113
114 /* ACPI */
115 sc_add_io_resource(dev, ACPI_BASE_ADDRESS, 128, ABASE);
116}
117
118static void sc_read_resources(device_t dev)
119{
120 /* Get the normal PCI resources of this device. */
121 pci_dev_read_resources(dev);
122
123 /* Add non-standard MMIO resources. */
124 sc_add_mmio_resources(dev);
125
126 /* Add IO resources. */
127 sc_add_io_resources(dev);
128}
129
Shawn Nematbakhsh51d787a2014-01-16 17:52:21 -0800130static void sc_rtc_init(void)
131{
132 uint32_t gen_pmcon1;
133 int rtc_fail;
134 struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
135
136 if (ps != NULL) {
137 gen_pmcon1 = ps->gen_pmcon1;
138 } else {
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800139 gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1));
Shawn Nematbakhsh51d787a2014-01-16 17:52:21 -0800140 }
141
142 rtc_fail = !!(gen_pmcon1 & RPS);
143
144 if (rtc_fail) {
145 printk(BIOS_DEBUG, "RTC failure.\n");
146 }
147
Gabe Blackb3f08c62014-04-30 17:12:25 -0700148 cmos_init(rtc_fail);
Shawn Nematbakhsh51d787a2014-01-16 17:52:21 -0800149}
150
Kein Yuan35110232014-02-22 12:26:55 -0800151/*
152 * The UART hardware loses power while in suspend. Because of this the kernel
153 * can hang because it doesn't re-initialize serial ports it is using for
154 * consoles at resume time. The following function configures the UART
155 * if the hardware is enabled though it may not be the correct baud rate
156 * or configuration. This is definitely a hack, but it helps the kernel
157 * along.
158 */
159static void com1_configure_resume(device_t dev)
160{
161 const uint16_t port = 0x3f8;
162
Martin Roth99a3bba2014-12-07 14:57:26 -0700163 /* Is the UART I/O port enabled? */
Kein Yuan35110232014-02-22 12:26:55 -0800164 if (!(pci_read_config32(dev, UART_CONT) & 1))
165 return;
166
167 /* Disable interrupts */
168 outb(0x0, port + UART8250_IER);
169
170 /* Enable FIFOs */
171 outb(UART8250_FCR_FIFO_EN, port + UART8250_FCR);
172
173 /* assert DTR and RTS so the other end is happy */
174 outb(UART8250_MCR_DTR | UART8250_MCR_RTS, port + UART8250_MCR);
175
176 /* DLAB on */
177 outb(UART8250_LCR_DLAB | 3, port + UART8250_LCR);
178
179 /* Set Baud Rate Divisor. 1 ==> 115200 Baud */
180 outb(1, port + UART8250_DLL);
181 outb(0, port + UART8250_DLM);
182
183 /* Set to 3 for 8N1 */
184 outb(3, port + UART8250_LCR);
185}
186
Aaron Durbin3bde3d72013-11-04 21:45:52 -0600187static void sc_init(device_t dev)
188{
189 int i;
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800190 u8 *pr_base = (u8 *)(ILB_BASE_ADDRESS + 0x08);
191 u16 *ir_base = (u16 *)ILB_BASE_ADDRESS + 0x20;
192 u32 *gen_pmcon1 = (u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1);
193 u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL);
Aaron Durbin3bde3d72013-11-04 21:45:52 -0600194 const struct baytrail_irq_route *ir = &global_baytrail_irq_route;
Shawn Nematbakhsh51d787a2014-01-16 17:52:21 -0800195 struct soc_intel_baytrail_config *config = dev->chip_info;
Aaron Durbin3bde3d72013-11-04 21:45:52 -0600196
197 /* Set up the PIRQ PIC routing based on static config. */
198 for (i = 0; i < NUM_PIRQS; i++) {
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800199 write8(pr_base + i, ir->pic[i]);
Aaron Durbin3bde3d72013-11-04 21:45:52 -0600200 }
201 /* Set up the per device PIRQ routing base on static config. */
202 for (i = 0; i < NUM_IR_DEVS; i++) {
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800203 write16(ir_base + i, ir->pcidev[i]);
Aaron Durbin3bde3d72013-11-04 21:45:52 -0600204 }
Aaron Durbin1af36632013-11-07 10:42:16 -0600205
206 /* Route SCI to IRQ9 */
207 write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9);
Shawn Nematbakhsh51d787a2014-01-16 17:52:21 -0800208
209 sc_rtc_init();
210
211 if (config->disable_slp_x_stretch_sus_fail) {
212 printk(BIOS_DEBUG, "Disabling slp_x stretching.\n");
213 write32(gen_pmcon1,
214 read32(gen_pmcon1) | DIS_SLP_X_STRCH_SUS_UP);
215 } else {
216 write32(gen_pmcon1,
217 read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP);
218 }
Kein Yuan35110232014-02-22 12:26:55 -0800219
Kyösti Mälkki9e94dbf2015-01-08 20:03:18 +0200220 if (acpi_is_wakeup_s3())
Kein Yuan35110232014-02-22 12:26:55 -0800221 com1_configure_resume(dev);
Aaron Durbin3bde3d72013-11-04 21:45:52 -0600222}
223
Aaron Durbind7bc23a2013-10-29 16:37:10 -0500224/*
225 * Common code for the south cluster devices.
226 */
227
Martin Roth99a3bba2014-12-07 14:57:26 -0700228/* Set bit in function disable register to hide this device. */
Aaron Durbind7bc23a2013-10-29 16:37:10 -0500229static void sc_disable_devfn(device_t dev)
230{
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800231 u32 *func_dis = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS);
232 u32 *func_dis2 = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS2);
Aaron Durbind7bc23a2013-10-29 16:37:10 -0500233 uint32_t mask = 0;
234 uint32_t mask2 = 0;
235
236 switch (dev->path.pci.devfn) {
237 case PCI_DEVFN(SDIO_DEV, SDIO_FUNC):
238 mask |= SDIO_DIS;
239 break;
240 case PCI_DEVFN(SD_DEV, SD_FUNC):
241 mask |= SD_DIS;
242 break;
243 case PCI_DEVFN(SATA_DEV, SATA_FUNC):
244 mask |= SATA_DIS;
245 break;
246 case PCI_DEVFN(XHCI_DEV, XHCI_FUNC):
247 mask |= XHCI_DIS;
248 /* Disable super speed PHY when XHCI is not available. */
249 mask2 |= USH_SS_PHY_DIS;
250 break;
251 case PCI_DEVFN(LPE_DEV, LPE_FUNC):
252 mask |= LPE_DIS;
253 break;
254 case PCI_DEVFN(MMC_DEV, MMC_FUNC):
255 mask |= MMC_DIS;
256 break;
257 case PCI_DEVFN(SIO_DMA1_DEV, SIO_DMA1_FUNC):
258 mask |= SIO_DMA1_DIS;
259 break;
260 case PCI_DEVFN(I2C1_DEV, I2C1_FUNC):
261 mask |= I2C1_DIS;
262 break;
263 case PCI_DEVFN(I2C2_DEV, I2C2_FUNC):
264 mask |= I2C1_DIS;
265 break;
266 case PCI_DEVFN(I2C3_DEV, I2C3_FUNC):
267 mask |= I2C3_DIS;
268 break;
269 case PCI_DEVFN(I2C4_DEV, I2C4_FUNC):
270 mask |= I2C4_DIS;
271 break;
272 case PCI_DEVFN(I2C5_DEV, I2C5_FUNC):
273 mask |= I2C5_DIS;
274 break;
275 case PCI_DEVFN(I2C6_DEV, I2C6_FUNC):
276 mask |= I2C6_DIS;
277 break;
278 case PCI_DEVFN(I2C7_DEV, I2C7_FUNC):
279 mask |= I2C7_DIS;
280 break;
281 case PCI_DEVFN(TXE_DEV, TXE_FUNC):
282 mask |= TXE_DIS;
283 break;
284 case PCI_DEVFN(HDA_DEV, HDA_FUNC):
285 mask |= HDA_DIS;
286 break;
287 case PCI_DEVFN(PCIE_PORT1_DEV, PCIE_PORT1_FUNC):
288 mask |= PCIE_PORT1_DIS;
289 break;
290 case PCI_DEVFN(PCIE_PORT2_DEV, PCIE_PORT2_FUNC):
291 mask |= PCIE_PORT2_DIS;
292 break;
293 case PCI_DEVFN(PCIE_PORT3_DEV, PCIE_PORT3_FUNC):
294 mask |= PCIE_PORT3_DIS;
295 break;
296 case PCI_DEVFN(PCIE_PORT4_DEV, PCIE_PORT4_FUNC):
297 mask |= PCIE_PORT4_DIS;
298 break;
299 case PCI_DEVFN(EHCI_DEV, EHCI_FUNC):
300 mask |= EHCI_DIS;
301 break;
302 case PCI_DEVFN(SIO_DMA2_DEV, SIO_DMA2_FUNC):
303 mask |= SIO_DMA2_DIS;
304 break;
305 case PCI_DEVFN(PWM1_DEV, PWM1_FUNC):
306 mask |= PWM1_DIS;
307 break;
308 case PCI_DEVFN(PWM2_DEV, PWM2_FUNC):
309 mask |= PWM2_DIS;
310 break;
311 case PCI_DEVFN(HSUART1_DEV, HSUART1_FUNC):
312 mask |= HSUART1_DIS;
313 break;
314 case PCI_DEVFN(HSUART2_DEV, HSUART2_FUNC):
315 mask |= HSUART2_DIS;
316 break;
317 case PCI_DEVFN(SPI_DEV, SPI_FUNC):
318 mask |= SPI_DIS;
319 break;
320 case PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC):
321 mask2 |= SMBUS_DIS;
322 break;
323 }
324
325 if (mask != 0) {
326 write32(func_dis, read32(func_dis) | mask);
327 /* Ensure posted write hits. */
328 read32(func_dis);
329 }
330
331 if (mask2 != 0) {
332 write32(func_dis2, read32(func_dis2) | mask2);
333 /* Ensure posted write hits. */
334 read32(func_dis2);
335 }
336}
337
338static inline void set_d3hot_bits(device_t dev, int offset)
339{
340 uint32_t reg8;
341 printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset);
342 reg8 = pci_read_config8(dev, offset + 4);
343 reg8 |= 0x3;
344 pci_write_config8(dev, offset + 4, reg8);
345}
346
Aaron Durbin46ab8cd2013-10-30 17:07:46 -0500347/* Parts of the audio subsystem are powered by the HDA device. Therefore, one
348 * cannot put HDA into D3Hot. Instead perform this workaround to make some of
349 * the audio paths work for LPE audio. */
350static void hda_work_around(device_t dev)
351{
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800352 u32 *gctl = (u32 *)(TEMP_BASE_ADDRESS + 0x8);
Aaron Durbin46ab8cd2013-10-30 17:07:46 -0500353
354 /* Need to set magic register 0x43 to 0xd7 in config space. */
355 pci_write_config8(dev, 0x43, 0xd7);
356
357 /* Need to set bit 0 of GCTL to take the device out of reset. However,
358 * that requires setting up the 64-bit BAR. */
359 pci_write_config32(dev, PCI_BASE_ADDRESS_0, TEMP_BASE_ADDRESS);
360 pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0);
361 pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
362 write32(gctl, read32(gctl) | 0x1);
363 pci_write_config8(dev, PCI_COMMAND, 0);
364 pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0);
365}
366
Aaron Durbind7bc23a2013-10-29 16:37:10 -0500367static int place_device_in_d3hot(device_t dev)
368{
369 unsigned offset;
370
Aaron Durbin46ab8cd2013-10-30 17:07:46 -0500371 /* Parts of the HDA block are used for LPE audio as well.
372 * Therefore assume the HDA will never be put into D3Hot. */
373 if (dev->path.pci.devfn == PCI_DEVFN(HDA_DEV, HDA_FUNC)) {
374 hda_work_around(dev);
375 return 0;
376 }
377
Aaron Durbind7bc23a2013-10-29 16:37:10 -0500378 offset = pci_find_capability(dev, PCI_CAP_ID_PM);
379
380 if (offset != 0) {
381 set_d3hot_bits(dev, offset);
382 return 0;
383 }
384
385 /* For some reason some of the devices don't have the capability
386 * pointer set correctly. Work around this by hard coding the offset. */
387 switch (dev->path.pci.devfn) {
388 case PCI_DEVFN(SDIO_DEV, SDIO_FUNC):
389 offset = 0x80;
390 break;
391 case PCI_DEVFN(SD_DEV, SD_FUNC):
392 offset = 0x80;
393 break;
394 case PCI_DEVFN(MMC_DEV, MMC_FUNC):
395 offset = 0x80;
396 break;
397 case PCI_DEVFN(LPE_DEV, LPE_FUNC):
398 offset = 0x80;
399 break;
400 case PCI_DEVFN(SIO_DMA1_DEV, SIO_DMA1_FUNC):
401 offset = 0x80;
402 break;
403 case PCI_DEVFN(I2C1_DEV, I2C1_FUNC):
404 offset = 0x80;
405 break;
406 case PCI_DEVFN(I2C2_DEV, I2C2_FUNC):
407 offset = 0x80;
408 break;
409 case PCI_DEVFN(I2C3_DEV, I2C3_FUNC):
410 offset = 0x80;
411 break;
412 case PCI_DEVFN(I2C4_DEV, I2C4_FUNC):
413 offset = 0x80;
414 break;
415 case PCI_DEVFN(I2C5_DEV, I2C5_FUNC):
416 offset = 0x80;
417 break;
418 case PCI_DEVFN(I2C6_DEV, I2C6_FUNC):
419 offset = 0x80;
420 break;
421 case PCI_DEVFN(I2C7_DEV, I2C7_FUNC):
422 offset = 0x80;
423 break;
424 case PCI_DEVFN(SIO_DMA2_DEV, SIO_DMA2_FUNC):
425 offset = 0x80;
426 break;
427 case PCI_DEVFN(PWM1_DEV, PWM1_FUNC):
428 offset = 0x80;
429 break;
430 case PCI_DEVFN(PWM2_DEV, PWM2_FUNC):
431 offset = 0x80;
432 break;
433 case PCI_DEVFN(HSUART1_DEV, HSUART1_FUNC):
434 offset = 0x80;
435 break;
436 case PCI_DEVFN(HSUART2_DEV, HSUART2_FUNC):
437 offset = 0x80;
438 break;
439 case PCI_DEVFN(SPI_DEV, SPI_FUNC):
440 offset = 0x80;
441 break;
442 case PCI_DEVFN(SATA_DEV, SATA_FUNC):
443 offset = 0x70;
444 break;
445 case PCI_DEVFN(XHCI_DEV, XHCI_FUNC):
446 offset = 0x70;
447 break;
448 case PCI_DEVFN(EHCI_DEV, EHCI_FUNC):
449 offset = 0x70;
450 break;
451 case PCI_DEVFN(HDA_DEV, HDA_FUNC):
452 offset = 0x50;
453 break;
454 case PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC):
455 offset = 0x50;
456 break;
457 case PCI_DEVFN(TXE_DEV, TXE_FUNC):
Aaron Durbin1eae3ee2013-10-30 17:08:59 -0500458 /* TXE cannot be placed in D3Hot. */
459 return 0;
Aaron Durbind7bc23a2013-10-29 16:37:10 -0500460 case PCI_DEVFN(PCIE_PORT1_DEV, PCIE_PORT1_FUNC):
461 offset = 0xa0;
462 break;
463 case PCI_DEVFN(PCIE_PORT2_DEV, PCIE_PORT2_FUNC):
464 offset = 0xa0;
465 break;
466 case PCI_DEVFN(PCIE_PORT3_DEV, PCIE_PORT3_FUNC):
467 offset = 0xa0;
468 break;
469 case PCI_DEVFN(PCIE_PORT4_DEV, PCIE_PORT4_FUNC):
470 offset = 0xa0;
471 break;
472 }
473
474 if (offset != 0) {
475 set_d3hot_bits(dev, offset);
476 return 0;
477 }
478
479 return -1;
480}
481
482/* Common PCI device function disable. */
483void southcluster_enable_dev(device_t dev)
484{
485 uint32_t reg32;
486
487 if (!dev->enabled) {
488 int slot = PCI_SLOT(dev->path.pci.devfn);
489 int func = PCI_FUNC(dev->path.pci.devfn);
490 printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n",
491 dev_path(dev), slot, func);
492
493 /* Ensure memory, io, and bus master are all disabled */
494 reg32 = pci_read_config32(dev, PCI_COMMAND);
495 reg32 &= ~(PCI_COMMAND_MASTER |
496 PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
497 pci_write_config32(dev, PCI_COMMAND, reg32);
498
499 /* Place device in D3Hot */
500 if (place_device_in_d3hot(dev) < 0) {
501 printk(BIOS_WARNING,
502 "Could not place %02x.%01x into D3Hot. "
503 "Keeping device visible.\n", slot, func);
504 return;
505 }
506 /* Disable this device if possible */
507 sc_disable_devfn(dev);
508 } else {
509 /* Enable SERR */
510 reg32 = pci_read_config32(dev, PCI_COMMAND);
511 reg32 |= PCI_COMMAND_SERR;
512 pci_write_config32(dev, PCI_COMMAND, reg32);
513 }
514}
515
Vladimir Serbinenko7fb149d2014-10-08 22:56:27 +0200516static void southcluster_inject_dsdt(void)
517{
518 global_nvs_t *gnvs;
519
520 gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
521 if (!gnvs) {
522 gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof (*gnvs));
523 if (gnvs)
524 memset(gnvs, 0, sizeof(*gnvs));
525 }
526
527 if (gnvs) {
528 acpi_create_gnvs(gnvs);
529 acpi_save_gnvs((unsigned long)gnvs);
530 /* And tell SMI about it */
531 smm_setup_structures(gnvs, NULL, NULL);
532
533 /* Add it to DSDT. */
534 acpigen_write_scope("\\");
535 acpigen_write_name_dword("NVSA", (u32) gnvs);
536 acpigen_pop_len();
537 }
538}
539
540
Aaron Durbine18d68f2013-10-24 00:05:31 -0500541static struct device_operations device_ops = {
542 .read_resources = sc_read_resources,
543 .set_resources = pci_dev_set_resources,
Vladimir Serbinenko7fb149d2014-10-08 22:56:27 +0200544 .acpi_inject_dsdt_generator = southcluster_inject_dsdt,
545 .write_acpi_tables = acpi_write_hpet,
Aaron Durbine18d68f2013-10-24 00:05:31 -0500546 .enable_resources = NULL,
Aaron Durbin3bde3d72013-11-04 21:45:52 -0600547 .init = sc_init,
Aaron Durbind7bc23a2013-10-29 16:37:10 -0500548 .enable = southcluster_enable_dev,
Kyösti Mälkkid0e212c2015-02-26 20:47:47 +0200549 .scan_bus = scan_lpc_bus,
Aaron Durbine18d68f2013-10-24 00:05:31 -0500550 .ops_pci = &soc_pci_ops,
551};
552
553static const struct pci_driver southcluster __pci_driver = {
554 .ops = &device_ops,
555 .vendor = PCI_VENDOR_ID_INTEL,
556 .device = LPC_DEVID,
557};
Aaron Durbin4177db52014-02-05 14:55:26 -0600558
559int __attribute__((weak)) mainboard_get_spi_config(struct spi_config *cfg)
560{
561 return -1;
562}
563
564static void finalize_chipset(void *unused)
565{
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800566 u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR);
567 u32 *gcs = (u32 *)(RCBA_BASE_ADDRESS + GCS);
568 u32 *gen_pmcon2 = (u32 *)(PMC_BASE_ADDRESS + GEN_PMCON2);
569 u32 *etr = (u32 *)(PMC_BASE_ADDRESS + ETR);
570 u8 *spi = (u8 *)SPI_BASE_ADDRESS;
Aaron Durbin4177db52014-02-05 14:55:26 -0600571 struct spi_config cfg;
572
573 /* Set the lock enable on the BIOS control register. */
574 write32(bcr, read32(bcr) | BCR_LE);
575
576 /* Set BIOS lock down bit controlling boot block size and swapping. */
577 write32(gcs, read32(gcs) | BILD);
578
579 /* Lock sleep stretching policy and set SMI lock. */
580 write32(gen_pmcon2, read32(gen_pmcon2) | SLPSX_STR_POL_LOCK | SMI_LOCK);
581
582 /* Set the CF9 lock. */
583 write32(etr, read32(etr) | CF9LOCK);
584
585 if (mainboard_get_spi_config(&cfg) < 0) {
586 printk(BIOS_DEBUG, "No SPI lockdown configuration.\n");
587 } else {
588 write16(spi + PREOP, cfg.preop);
589 write16(spi + OPTYPE, cfg.optype);
590 write32(spi + OPMENU0, cfg.opmenu[0]);
591 write32(spi + OPMENU1, cfg.opmenu[1]);
592 write16(spi + HSFSTS, read16(spi + HSFSTS) | FLOCKDN);
593 write32(spi + UVSCC, cfg.uvscc);
594 write32(spi + LVSCC, cfg.lvscc | VCL);
595 }
596
597 printk(BIOS_DEBUG, "Finalizing SMM.\n");
598 outb(APM_CNT_FINALIZE, APM_CNT);
599}
600
Aaron Durbin9ef9d852015-03-16 17:30:09 -0500601BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, finalize_chipset, NULL);
602BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, finalize_chipset, NULL);