Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 4 | #include <device/pci_ops.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 5 | #include <acpi/acpi.h> |
| 6 | #include <acpi/acpigen.h> |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 7 | #include <stdint.h> |
| 8 | #include <device/device.h> |
| 9 | #include <device/pci.h> |
| 10 | #include <device/pci_ids.h> |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 11 | #include <string.h> |
| 12 | #include <lib.h> |
| 13 | #include <cpu/cpu.h> |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 14 | #include <cpu/x86/lapic.h> |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 15 | #include <cpu/amd/msr.h> |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 16 | #include <cpu/amd/mtrr.h> |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 17 | #include <Porting.h> |
| 18 | #include <AGESA.h> |
| 19 | #include <Options.h> |
| 20 | #include <Topology.h> |
Angel Pons | ec5cf15 | 2020-11-10 20:42:07 +0100 | [diff] [blame] | 21 | #include <northbridge/amd/nb_common.h> |
Kyösti Mälkki | 28c4d2f | 2016-11-25 11:21:02 +0200 | [diff] [blame] | 22 | #include <northbridge/amd/agesa/state_machine.h> |
Kyösti Mälkki | d610c58 | 2017-03-05 06:28:18 +0200 | [diff] [blame] | 23 | #include <northbridge/amd/agesa/agesa_helper.h> |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 24 | |
Kyösti Mälkki | 113f670 | 2018-05-20 20:12:32 +0300 | [diff] [blame] | 25 | #define MAX_NODE_NUMS MAX_NODES |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 26 | |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 27 | static unsigned int node_nums; |
| 28 | static unsigned int sblink; |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 29 | static struct device *__f0_dev[MAX_NODE_NUMS]; |
| 30 | static struct device *__f1_dev[MAX_NODE_NUMS]; |
| 31 | static struct device *__f2_dev[MAX_NODE_NUMS]; |
| 32 | static struct device *__f4_dev[MAX_NODE_NUMS]; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 33 | static unsigned int fx_devs = 0; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 34 | |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 35 | static struct device *get_node_pci(u32 nodeid, u32 fn) |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 36 | { |
Kyösti Mälkki | 3d3152e | 2019-01-10 09:05:30 +0200 | [diff] [blame] | 37 | return pcidev_on_root(DEV_CDB + nodeid, fn); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 38 | } |
| 39 | |
| 40 | static void get_fx_devs(void) |
| 41 | { |
| 42 | int i; |
| 43 | for (i = 0; i < MAX_NODE_NUMS; i++) { |
| 44 | __f0_dev[i] = get_node_pci(i, 0); |
| 45 | __f1_dev[i] = get_node_pci(i, 1); |
| 46 | __f2_dev[i] = get_node_pci(i, 2); |
| 47 | __f4_dev[i] = get_node_pci(i, 4); |
| 48 | if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) |
Elyes Haouas | 3adfde9 | 2022-07-16 09:36:01 +0200 | [diff] [blame] | 49 | fx_devs = i + 1; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 50 | } |
| 51 | if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { |
| 52 | die("Cannot find 0:0x18.[0|1]\n"); |
| 53 | } |
| 54 | printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs); |
| 55 | } |
| 56 | |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 57 | static u32 f1_read_config32(unsigned int reg) |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 58 | { |
| 59 | if (fx_devs == 0) |
| 60 | get_fx_devs(); |
| 61 | return pci_read_config32(__f1_dev[0], reg); |
| 62 | } |
| 63 | |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 64 | static void f1_write_config32(unsigned int reg, u32 value) |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 65 | { |
| 66 | int i; |
| 67 | if (fx_devs == 0) |
| 68 | get_fx_devs(); |
Elyes HAOUAS | 5a7e72f | 2016-08-23 21:36:02 +0200 | [diff] [blame] | 69 | for (i = 0; i < fx_devs; i++) { |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 70 | struct device *dev; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 71 | dev = __f1_dev[i]; |
| 72 | if (dev && dev->enabled) { |
| 73 | pci_write_config32(dev, reg, value); |
| 74 | } |
| 75 | } |
| 76 | } |
| 77 | |
Michał Żygowski | 88a0ce6 | 2021-05-05 09:52:59 +0200 | [diff] [blame] | 78 | static int get_dram_base_limit(u32 nodeid, resource_t *basek, resource_t *limitk) |
| 79 | { |
| 80 | u32 temp; |
| 81 | |
| 82 | if (fx_devs == 0) |
| 83 | get_fx_devs(); |
| 84 | |
| 85 | |
| 86 | temp = pci_read_config32(__f1_dev[nodeid], 0x40 + (nodeid << 3)); //[39:24] at [31:16] |
| 87 | if (!(temp & 1)) |
| 88 | return 0; // this memory range is not enabled |
| 89 | /* |
| 90 | * BKDG: {DramBase[39:24], 00_0000h} <= address[39:0] so shift left by 8 bits |
| 91 | * for physical address and the convert to KiB by shifting 10 bits left |
| 92 | */ |
| 93 | *basek = ((temp & 0xffff0000)) >> (10 - 8); |
| 94 | /* |
| 95 | * BKDG address[39:0] <= {DramLimit[39:24], FF_FFFFh} converted as above but |
| 96 | * ORed with 0xffff to get real limit before shifting. |
| 97 | */ |
| 98 | temp = pci_read_config32(__f1_dev[nodeid], 0x44 + (nodeid << 3)); //[39:24] at [31:16] |
| 99 | *limitk = ((temp & 0xffff0000) | 0xffff) >> (10 - 8); |
| 100 | *limitk += 1; // round up last byte |
| 101 | |
| 102 | return 1; |
| 103 | } |
| 104 | |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 105 | static u32 amdfam16_nodeid(struct device *dev) |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 106 | { |
Kyösti Mälkki | 3d3152e | 2019-01-10 09:05:30 +0200 | [diff] [blame] | 107 | return (dev->path.pci.devfn >> 3) - DEV_CDB; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 108 | } |
| 109 | |
| 110 | static void set_vga_enable_reg(u32 nodeid, u32 linkn) |
| 111 | { |
| 112 | u32 val; |
| 113 | |
Elyes HAOUAS | 27e1801 | 2017-06-27 23:14:51 +0200 | [diff] [blame] | 114 | val = 1 | (nodeid << 4) | (linkn << 12); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 115 | /* it will routing |
| 116 | * (1)mmio 0xa0000:0xbffff |
| 117 | * (2)io 0x3b0:0x3bb, 0x3c0:0x3df |
| 118 | */ |
| 119 | f1_write_config32(0xf4, val); |
| 120 | |
| 121 | } |
| 122 | |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 123 | static void read_resources(struct device *dev) |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 124 | { |
Edward O'Callaghan | 66c6532 | 2014-11-21 01:43:38 +1100 | [diff] [blame] | 125 | /* |
| 126 | * This MMCONF resource must be reserved in the PCI_DOMAIN. |
| 127 | * It is not honored by the coreboot resource allocator if it is in |
| 128 | * the APIC_CLUSTER. |
| 129 | */ |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 130 | mmconf_resource(dev, MMIO_CONF_BASE); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 131 | |
Arthur Heymans | d0b2aa1 | 2022-10-13 18:33:18 +0200 | [diff] [blame^] | 132 | /* There should be no BAR. */ |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 133 | } |
| 134 | |
| 135 | /** |
| 136 | * I tried to reuse the resource allocation code in set_resource() |
| 137 | * but it is too difficult to deal with the resource allocation magic. |
| 138 | */ |
| 139 | |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 140 | static void create_vga_resource(struct device *dev, unsigned int nodeid) |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 141 | { |
| 142 | struct bus *link; |
| 143 | |
| 144 | /* find out which link the VGA card is connected, |
| 145 | * we only deal with the 'first' vga card */ |
| 146 | for (link = dev->link_list; link; link = link->next) { |
| 147 | if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 148 | #if CONFIG(MULTIPLE_VGA_ADAPTERS) |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 149 | extern struct device *vga_pri; // the primary vga device, defined in device.c |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 150 | printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, |
Elyes Haouas | 3adfde9 | 2022-07-16 09:36:01 +0200 | [diff] [blame] | 151 | link->secondary, link->subordinate); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 152 | /* We need to make sure the vga_pri is under the link */ |
Elyes HAOUAS | 1d8daa6 | 2016-09-18 08:50:54 +0200 | [diff] [blame] | 153 | if ((vga_pri->bus->secondary >= link->secondary) && |
| 154 | (vga_pri->bus->secondary <= link->subordinate)) |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 155 | #endif |
| 156 | break; |
| 157 | } |
| 158 | } |
| 159 | |
| 160 | /* no VGA card installed */ |
| 161 | if (link == NULL) |
| 162 | return; |
| 163 | |
| 164 | printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, sblink); |
| 165 | set_vga_enable_reg(nodeid, sblink); |
| 166 | } |
| 167 | |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 168 | static void set_resources(struct device *dev) |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 169 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 170 | unsigned int nodeid; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 171 | |
| 172 | /* Find the nodeid */ |
| 173 | nodeid = amdfam16_nodeid(dev); |
| 174 | |
| 175 | create_vga_resource(dev, nodeid); //TODO: do we need this? |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 176 | } |
| 177 | |
Vladimir Serbinenko | 807127f | 2014-11-09 13:36:18 +0100 | [diff] [blame] | 178 | static unsigned long acpi_fill_hest(acpi_hest_t *hest) |
Vladimir Serbinenko | db09b062 | 2014-10-08 22:15:17 +0200 | [diff] [blame] | 179 | { |
| 180 | void *addr, *current; |
| 181 | |
| 182 | /* Skip the HEST header. */ |
| 183 | current = (void *)(hest + 1); |
| 184 | |
| 185 | addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); |
| 186 | if (addr != NULL) |
Stefan Reinauer | 77a1d1a | 2015-07-21 12:48:17 -0700 | [diff] [blame] | 187 | current += acpi_create_hest_error_source(hest, current, 0, |
| 188 | addr + 2, *(UINT16 *)addr - 2); |
Vladimir Serbinenko | db09b062 | 2014-10-08 22:15:17 +0200 | [diff] [blame] | 189 | |
| 190 | addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); |
| 191 | if (addr != NULL) |
Stefan Reinauer | 77a1d1a | 2015-07-21 12:48:17 -0700 | [diff] [blame] | 192 | current += acpi_create_hest_error_source(hest, current, 1, |
| 193 | addr + 2, *(UINT16 *)addr - 2); |
Vladimir Serbinenko | db09b062 | 2014-10-08 22:15:17 +0200 | [diff] [blame] | 194 | |
| 195 | return (unsigned long)current; |
| 196 | } |
| 197 | |
Furquan Shaikh | 7536a39 | 2020-04-24 21:59:21 -0700 | [diff] [blame] | 198 | static void northbridge_fill_ssdt_generator(const struct device *device) |
Vladimir Serbinenko | db09b062 | 2014-10-08 22:15:17 +0200 | [diff] [blame] | 199 | { |
| 200 | msr_t msr; |
| 201 | char pscope[] = "\\_SB.PCI0"; |
| 202 | |
| 203 | acpigen_write_scope(pscope); |
| 204 | msr = rdmsr(TOP_MEM); |
| 205 | acpigen_write_name_dword("TOM1", msr.lo); |
| 206 | msr = rdmsr(TOP_MEM2); |
| 207 | /* |
| 208 | * Since XP only implements parts of ACPI 2.0, we can't use a qword |
| 209 | * here. |
| 210 | * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt |
| 211 | * slide 22ff. |
| 212 | * Shift value right by 20 bit to make it fit into 32bit, |
| 213 | * giving us 1MB granularity and a limit of almost 4Exabyte of memory. |
| 214 | */ |
| 215 | acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); |
| 216 | acpigen_pop_len(); |
| 217 | } |
| 218 | |
Michał Żygowski | 9550e97 | 2020-03-20 13:56:46 +0100 | [diff] [blame] | 219 | static void patch_ssdt_processor_scope(acpi_header_t *ssdt) |
| 220 | { |
| 221 | unsigned int len = ssdt->length - sizeof(acpi_header_t); |
| 222 | unsigned int i; |
| 223 | |
| 224 | for (i = sizeof(acpi_header_t); i < len; i++) { |
| 225 | /* Search for _PR_ scope and replace it with _SB_ */ |
| 226 | if (*(uint32_t *)((unsigned long)ssdt + i) == 0x5f52505f) |
| 227 | *(uint32_t *)((unsigned long)ssdt + i) = 0x5f42535f; |
| 228 | } |
| 229 | /* Recalculate checksum */ |
| 230 | ssdt->checksum = 0; |
| 231 | ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); |
| 232 | } |
| 233 | |
Furquan Shaikh | 0f007d8 | 2020-04-24 06:41:18 -0700 | [diff] [blame] | 234 | static unsigned long agesa_write_acpi_tables(const struct device *device, |
Alexander Couzens | 83fc32f | 2015-04-12 22:28:37 +0200 | [diff] [blame] | 235 | unsigned long current, |
Vladimir Serbinenko | db09b062 | 2014-10-08 22:15:17 +0200 | [diff] [blame] | 236 | acpi_rsdp_t *rsdp) |
| 237 | { |
| 238 | acpi_srat_t *srat; |
| 239 | acpi_slit_t *slit; |
| 240 | acpi_header_t *ssdt; |
| 241 | acpi_header_t *alib; |
| 242 | acpi_header_t *ivrs; |
| 243 | acpi_hest_t *hest; |
| 244 | |
| 245 | /* HEST */ |
Elyes Haouas | d6b6b22 | 2022-10-10 12:34:21 +0200 | [diff] [blame] | 246 | current = ALIGN_UP(current, 8); |
Vladimir Serbinenko | db09b062 | 2014-10-08 22:15:17 +0200 | [diff] [blame] | 247 | hest = (acpi_hest_t *)current; |
Arthur Heymans | cc66ff3 | 2022-03-23 21:33:15 +0100 | [diff] [blame] | 248 | acpi_write_hest(hest, acpi_fill_hest); |
| 249 | acpi_add_table(rsdp, hest); |
| 250 | current += hest->header.length; |
Vladimir Serbinenko | db09b062 | 2014-10-08 22:15:17 +0200 | [diff] [blame] | 251 | |
Elyes Haouas | d6b6b22 | 2022-10-10 12:34:21 +0200 | [diff] [blame] | 252 | current = ALIGN_UP(current, 8); |
Vladimir Serbinenko | db09b062 | 2014-10-08 22:15:17 +0200 | [diff] [blame] | 253 | printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); |
| 254 | ivrs = agesawrapper_getlateinitptr(PICK_IVRS); |
| 255 | if (ivrs != NULL) { |
| 256 | memcpy((void *)current, ivrs, ivrs->length); |
Elyes Haouas | 3adfde9 | 2022-07-16 09:36:01 +0200 | [diff] [blame] | 257 | ivrs = (acpi_header_t *)current; |
Vladimir Serbinenko | db09b062 | 2014-10-08 22:15:17 +0200 | [diff] [blame] | 258 | current += ivrs->length; |
| 259 | acpi_add_table(rsdp, ivrs); |
| 260 | } else { |
| 261 | printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n"); |
| 262 | } |
| 263 | |
| 264 | /* SRAT */ |
Elyes Haouas | d6b6b22 | 2022-10-10 12:34:21 +0200 | [diff] [blame] | 265 | current = ALIGN_UP(current, 8); |
Vladimir Serbinenko | db09b062 | 2014-10-08 22:15:17 +0200 | [diff] [blame] | 266 | printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); |
Elyes Haouas | 3adfde9 | 2022-07-16 09:36:01 +0200 | [diff] [blame] | 267 | srat = (acpi_srat_t *)agesawrapper_getlateinitptr(PICK_SRAT); |
Vladimir Serbinenko | db09b062 | 2014-10-08 22:15:17 +0200 | [diff] [blame] | 268 | if (srat != NULL) { |
| 269 | memcpy((void *)current, srat, srat->header.length); |
Elyes Haouas | 3adfde9 | 2022-07-16 09:36:01 +0200 | [diff] [blame] | 270 | srat = (acpi_srat_t *)current; |
Vladimir Serbinenko | db09b062 | 2014-10-08 22:15:17 +0200 | [diff] [blame] | 271 | current += srat->header.length; |
| 272 | acpi_add_table(rsdp, srat); |
| 273 | } else { |
| 274 | printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); |
| 275 | } |
| 276 | |
| 277 | /* SLIT */ |
Elyes Haouas | d6b6b22 | 2022-10-10 12:34:21 +0200 | [diff] [blame] | 278 | current = ALIGN_UP(current, 8); |
Vladimir Serbinenko | db09b062 | 2014-10-08 22:15:17 +0200 | [diff] [blame] | 279 | printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); |
Elyes Haouas | 3adfde9 | 2022-07-16 09:36:01 +0200 | [diff] [blame] | 280 | slit = (acpi_slit_t *)agesawrapper_getlateinitptr(PICK_SLIT); |
Vladimir Serbinenko | db09b062 | 2014-10-08 22:15:17 +0200 | [diff] [blame] | 281 | if (slit != NULL) { |
| 282 | memcpy((void *)current, slit, slit->header.length); |
Elyes Haouas | 3adfde9 | 2022-07-16 09:36:01 +0200 | [diff] [blame] | 283 | slit = (acpi_slit_t *)current; |
Vladimir Serbinenko | db09b062 | 2014-10-08 22:15:17 +0200 | [diff] [blame] | 284 | current += slit->header.length; |
| 285 | acpi_add_table(rsdp, slit); |
| 286 | } else { |
| 287 | printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); |
| 288 | } |
| 289 | |
| 290 | /* ALIB */ |
Elyes Haouas | d6b6b22 | 2022-10-10 12:34:21 +0200 | [diff] [blame] | 291 | current = ALIGN_UP(current, 16); |
Vladimir Serbinenko | db09b062 | 2014-10-08 22:15:17 +0200 | [diff] [blame] | 292 | printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); |
Elyes Haouas | 3adfde9 | 2022-07-16 09:36:01 +0200 | [diff] [blame] | 293 | alib = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_ALIB); |
Vladimir Serbinenko | db09b062 | 2014-10-08 22:15:17 +0200 | [diff] [blame] | 294 | if (alib != NULL) { |
| 295 | memcpy((void *)current, alib, alib->length); |
Elyes Haouas | 3adfde9 | 2022-07-16 09:36:01 +0200 | [diff] [blame] | 296 | alib = (acpi_header_t *)current; |
Vladimir Serbinenko | db09b062 | 2014-10-08 22:15:17 +0200 | [diff] [blame] | 297 | current += alib->length; |
| 298 | acpi_add_table(rsdp, (void *)alib); |
| 299 | } |
| 300 | else { |
| 301 | printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); |
| 302 | } |
| 303 | |
| 304 | /* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */ |
| 305 | /* SSDT */ |
Elyes Haouas | d6b6b22 | 2022-10-10 12:34:21 +0200 | [diff] [blame] | 306 | current = ALIGN_UP(current, 16); |
Vladimir Serbinenko | db09b062 | 2014-10-08 22:15:17 +0200 | [diff] [blame] | 307 | printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); |
Elyes Haouas | 3adfde9 | 2022-07-16 09:36:01 +0200 | [diff] [blame] | 308 | ssdt = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_PSTATE); |
Vladimir Serbinenko | db09b062 | 2014-10-08 22:15:17 +0200 | [diff] [blame] | 309 | if (ssdt != NULL) { |
Michał Żygowski | 9550e97 | 2020-03-20 13:56:46 +0100 | [diff] [blame] | 310 | patch_ssdt_processor_scope(ssdt); |
Vladimir Serbinenko | db09b062 | 2014-10-08 22:15:17 +0200 | [diff] [blame] | 311 | memcpy((void *)current, ssdt, ssdt->length); |
Elyes Haouas | 3adfde9 | 2022-07-16 09:36:01 +0200 | [diff] [blame] | 312 | ssdt = (acpi_header_t *)current; |
Vladimir Serbinenko | db09b062 | 2014-10-08 22:15:17 +0200 | [diff] [blame] | 313 | current += ssdt->length; |
| 314 | } |
| 315 | else { |
| 316 | printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n"); |
| 317 | } |
Elyes Haouas | 3adfde9 | 2022-07-16 09:36:01 +0200 | [diff] [blame] | 318 | acpi_add_table(rsdp, ssdt); |
Vladimir Serbinenko | db09b062 | 2014-10-08 22:15:17 +0200 | [diff] [blame] | 319 | |
| 320 | printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); |
| 321 | |
| 322 | return current; |
| 323 | } |
| 324 | |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 325 | static struct device_operations northbridge_operations = { |
| 326 | .read_resources = read_resources, |
| 327 | .set_resources = set_resources, |
| 328 | .enable_resources = pci_dev_enable_resources, |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 329 | .acpi_fill_ssdt = northbridge_fill_ssdt_generator, |
Vladimir Serbinenko | db09b062 | 2014-10-08 22:15:17 +0200 | [diff] [blame] | 330 | .write_acpi_tables = agesa_write_acpi_tables, |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 331 | }; |
| 332 | |
| 333 | static const struct pci_driver family16_northbridge __pci_driver = { |
| 334 | .ops = &northbridge_operations, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 335 | .vendor = PCI_VID_AMD, |
| 336 | .device = PCI_DID_AMD_16H_MODEL_000F_NB_HT, |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 337 | }; |
| 338 | |
| 339 | static const struct pci_driver family10_northbridge __pci_driver = { |
| 340 | .ops = &northbridge_operations, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 341 | .vendor = PCI_VID_AMD, |
| 342 | .device = PCI_DID_AMD_10H_NB_HT, |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 343 | }; |
| 344 | |
Kyösti Mälkki | 4ee82c6 | 2014-11-25 16:03:12 +0200 | [diff] [blame] | 345 | static void fam16_finalize(void *chip_info) |
| 346 | { |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 347 | struct device *dev; |
Kyösti Mälkki | 4ee82c6 | 2014-11-25 16:03:12 +0200 | [diff] [blame] | 348 | u32 value; |
Kyösti Mälkki | 4ad7f5b | 2018-05-22 01:15:17 +0300 | [diff] [blame] | 349 | dev = pcidev_on_root(0, 0); /* clear IoapicSbFeatureEn */ |
Kyösti Mälkki | 4ee82c6 | 2014-11-25 16:03:12 +0200 | [diff] [blame] | 350 | pci_write_config32(dev, 0xF8, 0); |
| 351 | pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ |
| 352 | |
| 353 | /* disable No Snoop */ |
Kyösti Mälkki | 4ad7f5b | 2018-05-22 01:15:17 +0300 | [diff] [blame] | 354 | dev = pcidev_on_root(1, 1); |
Kyösti Mälkki | 69f6fd4 | 2019-01-21 14:19:01 +0200 | [diff] [blame] | 355 | if (dev != NULL) { |
| 356 | value = pci_read_config32(dev, 0x60); |
| 357 | value &= ~(1 << 11); |
| 358 | pci_write_config32(dev, 0x60, value); |
| 359 | } |
Kyösti Mälkki | 4ee82c6 | 2014-11-25 16:03:12 +0200 | [diff] [blame] | 360 | } |
| 361 | |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 362 | struct chip_operations northbridge_amd_agesa_family16kb_ops = { |
| 363 | CHIP_NAME("AMD FAM16 Northbridge") |
| 364 | .enable_dev = 0, |
Kyösti Mälkki | 4ee82c6 | 2014-11-25 16:03:12 +0200 | [diff] [blame] | 365 | .final = fam16_finalize, |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 366 | }; |
| 367 | |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 368 | static void domain_read_resources(struct device *dev) |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 369 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 370 | unsigned int reg; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 371 | |
| 372 | /* Find the already assigned resource pairs */ |
| 373 | get_fx_devs(); |
Elyes Haouas | 3adfde9 | 2022-07-16 09:36:01 +0200 | [diff] [blame] | 374 | for (reg = 0x80; reg <= 0xd8; reg += 0x08) { |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 375 | u32 base, limit; |
| 376 | base = f1_read_config32(reg); |
| 377 | limit = f1_read_config32(reg + 0x04); |
| 378 | /* Is this register allocated? */ |
| 379 | if ((base & 3) != 0) { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 380 | unsigned int nodeid, reg_link; |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 381 | struct device *reg_dev; |
Elyes HAOUAS | 1d8daa6 | 2016-09-18 08:50:54 +0200 | [diff] [blame] | 382 | if (reg < 0xc0) { // mmio |
Elyes Haouas | 3adfde9 | 2022-07-16 09:36:01 +0200 | [diff] [blame] | 383 | nodeid = (limit & 0xf) + (base & 0x30); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 384 | } else { // io |
Elyes Haouas | 3adfde9 | 2022-07-16 09:36:01 +0200 | [diff] [blame] | 385 | nodeid = (limit & 0xf) + ((base >> 4) & 0x30); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 386 | } |
| 387 | reg_link = (limit >> 4) & 7; |
| 388 | reg_dev = __f0_dev[nodeid]; |
| 389 | if (reg_dev) { |
| 390 | /* Reserve the resource */ |
| 391 | struct resource *res; |
| 392 | res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); |
| 393 | if (res) { |
| 394 | res->flags = 1; |
| 395 | } |
| 396 | } |
| 397 | } |
| 398 | } |
| 399 | /* FIXME: do we need to check extend conf space? |
| 400 | I don't believe that much preset value */ |
| 401 | |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 402 | pci_domain_read_resources(dev); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 403 | } |
| 404 | |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 405 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 406 | struct hw_mem_hole_info { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 407 | unsigned int hole_startk; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 408 | int node_id; |
| 409 | }; |
| 410 | static struct hw_mem_hole_info get_hw_mem_hole_info(void) |
| 411 | { |
| 412 | struct hw_mem_hole_info mem_hole; |
| 413 | int i; |
| 414 | mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; |
| 415 | mem_hole.node_id = -1; |
| 416 | for (i = 0; i < node_nums; i++) { |
Michał Żygowski | 88a0ce6 | 2021-05-05 09:52:59 +0200 | [diff] [blame] | 417 | resource_t basek, limitk; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 418 | u32 hole; |
Michał Żygowski | 88a0ce6 | 2021-05-05 09:52:59 +0200 | [diff] [blame] | 419 | if (!get_dram_base_limit(i, &basek, &limitk)) |
| 420 | continue; // no memory on this node |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 421 | hole = pci_read_config32(__f1_dev[i], 0xf0); |
| 422 | if (hole & 2) { // we find the hole |
Elyes HAOUAS | 27e1801 | 2017-06-27 23:14:51 +0200 | [diff] [blame] | 423 | mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 424 | mem_hole.node_id = i; // record the node No with hole |
| 425 | break; // only one hole |
| 426 | } |
| 427 | } |
Kyösti Mälkki | 2f9b3af | 2014-06-26 05:30:54 +0300 | [diff] [blame] | 428 | |
| 429 | /* We need to double check if there is special set on base reg and limit reg |
| 430 | * are not continuous instead of hole, it will find out its hole_startk. |
| 431 | */ |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 432 | if (mem_hole.node_id == -1) { |
| 433 | resource_t limitk_pri = 0; |
Elyes HAOUAS | 1d8daa6 | 2016-09-18 08:50:54 +0200 | [diff] [blame] | 434 | for (i = 0; i < node_nums; i++) { |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 435 | resource_t base_k, limit_k; |
Michał Żygowski | 88a0ce6 | 2021-05-05 09:52:59 +0200 | [diff] [blame] | 436 | if (!get_dram_base_limit(i, &base_k, &limit_k)) |
| 437 | continue; // no memory on this node |
Elyes Haouas | 3adfde9 | 2022-07-16 09:36:01 +0200 | [diff] [blame] | 438 | if (base_k > 4 * 1024 * 1024) break; // don't need to go to check |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 439 | if (limitk_pri != base_k) { // we find the hole |
Martin Roth | 468d02c | 2019-10-23 21:44:42 -0600 | [diff] [blame] | 440 | mem_hole.hole_startk = (unsigned int)limitk_pri; // must beblow 4G |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 441 | mem_hole.node_id = i; |
| 442 | break; //only one hole |
| 443 | } |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 444 | limitk_pri = limit_k; |
| 445 | } |
| 446 | } |
| 447 | return mem_hole; |
| 448 | } |
| 449 | #endif |
| 450 | |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 451 | static void domain_set_resources(struct device *dev) |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 452 | { |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 453 | unsigned long mmio_basek; |
| 454 | u32 pci_tolm; |
| 455 | int i, idx; |
| 456 | struct bus *link; |
| 457 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 458 | struct hw_mem_hole_info mem_hole; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 459 | #endif |
| 460 | |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 461 | pci_tolm = 0xffffffffUL; |
| 462 | for (link = dev->link_list; link; link = link->next) { |
| 463 | pci_tolm = find_pci_tolm(link); |
| 464 | } |
| 465 | |
| 466 | // FIXME handle interleaved nodes. If you fix this here, please fix |
| 467 | // amdk8, too. |
| 468 | mmio_basek = pci_tolm >> 10; |
| 469 | /* Round mmio_basek to something the processor can support */ |
Elyes Haouas | 3adfde9 | 2022-07-16 09:36:01 +0200 | [diff] [blame] | 470 | mmio_basek &= ~((1 << 6) - 1); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 471 | |
| 472 | // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M |
| 473 | // MMIO hole. If you fix this here, please fix amdk8, too. |
| 474 | /* Round the mmio hole to 64M */ |
Elyes Haouas | 3adfde9 | 2022-07-16 09:36:01 +0200 | [diff] [blame] | 475 | mmio_basek &= ~((64 * 1024) - 1); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 476 | |
| 477 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 478 | /* if the hw mem hole is already set in raminit stage, here we will compare |
| 479 | * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will |
| 480 | * use hole_basek as mmio_basek and we don't need to reset hole. |
| 481 | * otherwise We reset the hole to the mmio_basek |
| 482 | */ |
| 483 | |
| 484 | mem_hole = get_hw_mem_hole_info(); |
| 485 | |
| 486 | // Use hole_basek as mmio_basek, and we don't need to reset hole anymore |
Arthur Heymans | 99eab34 | 2022-03-23 21:34:20 +0100 | [diff] [blame] | 487 | if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 488 | mmio_basek = mem_hole.hole_startk; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 489 | #endif |
| 490 | |
| 491 | idx = 0x10; |
| 492 | for (i = 0; i < node_nums; i++) { |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 493 | resource_t basek, limitk, sizek; // 4 1T |
| 494 | |
Michał Żygowski | 88a0ce6 | 2021-05-05 09:52:59 +0200 | [diff] [blame] | 495 | if (!get_dram_base_limit(i, &basek, &limitk)) |
| 496 | continue; // no memory on this node |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 497 | |
| 498 | sizek = limitk - basek; |
| 499 | |
Elyes Haouas | 5213b19 | 2022-02-25 18:13:03 +0100 | [diff] [blame] | 500 | /* See if we need a hole from 0xa0000 (640K) to 0xbffff (768K) */ |
Elyes Haouas | 9d8df30 | 2022-02-25 18:23:01 +0100 | [diff] [blame] | 501 | if (basek < 640 && sizek > 768) { |
Kyösti Mälkki | 27d6299 | 2022-05-24 20:25:58 +0300 | [diff] [blame] | 502 | ram_resource_kb(dev, (idx | i), basek, 640 - basek); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 503 | idx += 0x10; |
Elyes Haouas | 9d8df30 | 2022-02-25 18:23:01 +0100 | [diff] [blame] | 504 | basek = 768; |
| 505 | sizek = limitk - basek; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 506 | } |
| 507 | |
| 508 | //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); |
| 509 | |
Kyösti Mälkki | 26c6543 | 2014-06-26 05:30:54 +0300 | [diff] [blame] | 510 | /* split the region to accommodate pci memory space */ |
Elyes Haouas | 3adfde9 | 2022-07-16 09:36:01 +0200 | [diff] [blame] | 511 | if ((basek < 4 * 1024 * 1024) && (limitk > mmio_basek)) { |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 512 | if (basek <= mmio_basek) { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 513 | unsigned int pre_sizek; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 514 | pre_sizek = mmio_basek - basek; |
Elyes HAOUAS | 1d8daa6 | 2016-09-18 08:50:54 +0200 | [diff] [blame] | 515 | if (pre_sizek > 0) { |
Kyösti Mälkki | 27d6299 | 2022-05-24 20:25:58 +0300 | [diff] [blame] | 516 | ram_resource_kb(dev, (idx | i), basek, pre_sizek); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 517 | idx += 0x10; |
| 518 | sizek -= pre_sizek; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 519 | } |
| 520 | basek = mmio_basek; |
| 521 | } |
Elyes Haouas | 3adfde9 | 2022-07-16 09:36:01 +0200 | [diff] [blame] | 522 | if ((basek + sizek) <= 4 * 1024 * 1024) { |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 523 | sizek = 0; |
| 524 | } |
| 525 | else { |
Arthur Heymans | c435038 | 2021-10-28 12:35:39 +0200 | [diff] [blame] | 526 | uint64_t topmem2 = amd_topmem2(); |
Elyes Haouas | 3adfde9 | 2022-07-16 09:36:01 +0200 | [diff] [blame] | 527 | basek = 4 * 1024 * 1024; |
| 528 | sizek = topmem2 / 1024 - basek; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 529 | } |
| 530 | } |
| 531 | |
Kyösti Mälkki | 27d6299 | 2022-05-24 20:25:58 +0300 | [diff] [blame] | 532 | ram_resource_kb(dev, (idx | i), basek, sizek); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 533 | idx += 0x10; |
| 534 | printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", |
| 535 | i, mmio_basek, basek, limitk); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 536 | } |
| 537 | |
Kyösti Mälkki | 61be360 | 2017-04-15 20:07:53 +0300 | [diff] [blame] | 538 | add_uma_resource_below_tolm(dev, 7); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 539 | |
Elyes HAOUAS | 5a7e72f | 2016-08-23 21:36:02 +0200 | [diff] [blame] | 540 | for (link = dev->link_list; link; link = link->next) { |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 541 | if (link->children) { |
| 542 | assign_resources(link); |
| 543 | } |
| 544 | } |
| 545 | } |
| 546 | |
Kevin Cody-Little | 06d2323 | 2018-05-09 14:22:15 -0400 | [diff] [blame] | 547 | static const char *domain_acpi_name(const struct device *dev) |
| 548 | { |
| 549 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 550 | return "PCI0"; |
| 551 | |
| 552 | return NULL; |
| 553 | } |
| 554 | |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 555 | static struct device_operations pci_domain_ops = { |
| 556 | .read_resources = domain_read_resources, |
| 557 | .set_resources = domain_set_resources, |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 558 | .scan_bus = pci_domain_scan_bus, |
Kevin Cody-Little | 06d2323 | 2018-05-09 14:22:15 -0400 | [diff] [blame] | 559 | .acpi_name = domain_acpi_name, |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 560 | }; |
| 561 | |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 562 | static void sysconf_init(struct device *dev) // first node |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 563 | { |
Elyes Haouas | 3adfde9 | 2022-07-16 09:36:01 +0200 | [diff] [blame] | 564 | sblink = (pci_read_config32(dev, 0x64) >> 8) & 7; // don't forget sublink1 |
| 565 | node_nums = ((pci_read_config32(dev, 0x60) >> 4) & 7) + 1; //NodeCnt[2:0] |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 566 | } |
| 567 | |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 568 | static void cpu_bus_scan(struct device *dev) |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 569 | { |
| 570 | struct bus *cpu_bus; |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 571 | struct device *dev_mc; |
Elyes Haouas | 3adfde9 | 2022-07-16 09:36:01 +0200 | [diff] [blame] | 572 | int i, j; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 573 | int coreid_bits; |
| 574 | int core_max = 0; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 575 | unsigned int ApicIdCoreIdSize; |
| 576 | unsigned int core_nums; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 577 | int siblings = 0; |
| 578 | unsigned int family; |
| 579 | |
Kyösti Mälkki | 3d3152e | 2019-01-10 09:05:30 +0200 | [diff] [blame] | 580 | dev_mc = pcidev_on_root(DEV_CDB, 0); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 581 | if (!dev_mc) { |
Kyösti Mälkki | 3d3152e | 2019-01-10 09:05:30 +0200 | [diff] [blame] | 582 | printk(BIOS_ERR, "0:%02x.0 not found", DEV_CDB); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 583 | die(""); |
| 584 | } |
| 585 | sysconf_init(dev_mc); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 586 | |
| 587 | /* Get Max Number of cores(MNC) */ |
Kyösti Mälkki | d41feed | 2017-09-24 16:23:57 +0300 | [diff] [blame] | 588 | coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 589 | core_max = 1 << (coreid_bits & 0x000F); //mnc |
| 590 | |
Elyes Haouas | 3adfde9 | 2022-07-16 09:36:01 +0200 | [diff] [blame] | 591 | ApicIdCoreIdSize = ((cpuid_ecx(0x80000008) >> 12) & 0xF); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 592 | if (ApicIdCoreIdSize) { |
| 593 | core_nums = (1 << ApicIdCoreIdSize) - 1; |
| 594 | } else { |
| 595 | core_nums = 3; //quad core |
| 596 | } |
| 597 | |
| 598 | /* Find which cpus are present */ |
| 599 | cpu_bus = dev->link_list; |
| 600 | for (i = 0; i < node_nums; i++) { |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 601 | struct device *cdb_dev; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 602 | unsigned int devn; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 603 | struct bus *pbus; |
| 604 | |
Kyösti Mälkki | 3d3152e | 2019-01-10 09:05:30 +0200 | [diff] [blame] | 605 | devn = DEV_CDB + i; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 606 | pbus = dev_mc->bus; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 607 | |
| 608 | /* Find the cpu's pci device */ |
Kyösti Mälkki | 4ad7f5b | 2018-05-22 01:15:17 +0300 | [diff] [blame] | 609 | cdb_dev = pcidev_on_root(devn, 0); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 610 | if (!cdb_dev) { |
| 611 | /* If I am probing things in a weird order |
| 612 | * ensure all of the cpu's pci devices are found. |
| 613 | */ |
| 614 | int fn; |
Elyes HAOUAS | 5a7e72f | 2016-08-23 21:36:02 +0200 | [diff] [blame] | 615 | for (fn = 0; fn <= 5; fn++) { //FBDIMM? |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 616 | cdb_dev = pci_probe_dev(NULL, pbus, |
| 617 | PCI_DEVFN(devn, fn)); |
| 618 | } |
Kyösti Mälkki | 4ad7f5b | 2018-05-22 01:15:17 +0300 | [diff] [blame] | 619 | cdb_dev = pcidev_on_root(devn, 0); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 620 | } else { |
| 621 | /* Ok, We need to set the links for that device. |
| 622 | * otherwise the device under it will not be scanned |
| 623 | */ |
Kyösti Mälkki | 2a2d613 | 2015-02-04 13:25:37 +0200 | [diff] [blame] | 624 | add_more_links(cdb_dev, 4); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 625 | } |
| 626 | |
| 627 | family = cpuid_eax(1); |
| 628 | family = (family >> 20) & 0xFF; |
| 629 | if (family == 1) { //f10 |
| 630 | u32 dword; |
Kyösti Mälkki | 4ad7f5b | 2018-05-22 01:15:17 +0300 | [diff] [blame] | 631 | cdb_dev = pcidev_on_root(devn, 3); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 632 | dword = pci_read_config32(cdb_dev, 0xe8); |
| 633 | siblings = ((dword & BIT15) >> 13) | ((dword & (BIT13 | BIT12)) >> 12); |
| 634 | } else if (family == 7) {//f16 |
Kyösti Mälkki | 4ad7f5b | 2018-05-22 01:15:17 +0300 | [diff] [blame] | 635 | cdb_dev = pcidev_on_root(devn, 5); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 636 | if (cdb_dev && cdb_dev->enabled) { |
| 637 | siblings = pci_read_config32(cdb_dev, 0x84); |
| 638 | siblings &= 0xFF; |
| 639 | } |
| 640 | } else { |
| 641 | siblings = 0; //default one core |
| 642 | } |
| 643 | int enable_node = cdb_dev && cdb_dev->enabled; |
| 644 | printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", |
| 645 | dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); |
| 646 | |
Elyes HAOUAS | 1d8daa6 | 2016-09-18 08:50:54 +0200 | [diff] [blame] | 647 | for (j = 0; j <= siblings; j++) { |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 648 | extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration; |
| 649 | u32 modules = TopologyConfiguration.PlatformNumberOfModules; |
| 650 | u32 lapicid_start = 0; |
| 651 | |
| 652 | /* |
| 653 | * APIC ID calucation is tightly coupled with AGESA v5 code. |
| 654 | * This calculation MUST match the assignment calculation done |
| 655 | * in LocalApicInitializationAtEarly() function. |
| 656 | * And reference GetLocalApicIdForCore() |
| 657 | * |
Elyes HAOUAS | a5b0bc4 | 2020-02-20 20:04:29 +0100 | [diff] [blame] | 658 | * Apply APIC enumeration rules |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 659 | * For systems with >= 16 APICs, put the IO-APICs at 0..n and |
| 660 | * put the local-APICs at m..z |
| 661 | * |
| 662 | * This is needed because many IO-APIC devices only have 4 bits |
| 663 | * for their APIC id and therefore must reside at 0..15 |
Elyes HAOUAS | 6e8b3c1 | 2016-09-02 19:22:00 +0200 | [diff] [blame] | 664 | */ |
Kyösti Mälkki | 5003632 | 2016-05-18 13:35:21 +0300 | [diff] [blame] | 665 | |
Elyes HAOUAS | 6e8b3c1 | 2016-09-02 19:22:00 +0200 | [diff] [blame] | 666 | u8 plat_num_io_apics = 3; /* FIXME */ |
Kyösti Mälkki | 5003632 | 2016-05-18 13:35:21 +0300 | [diff] [blame] | 667 | |
| 668 | if ((node_nums * core_max) + plat_num_io_apics >= 0x10) { |
| 669 | lapicid_start = (plat_num_io_apics - 1) / core_max; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 670 | lapicid_start = (lapicid_start + 1) * core_max; |
| 671 | printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); |
| 672 | } |
Elyes Haouas | 3adfde9 | 2022-07-16 09:36:01 +0200 | [diff] [blame] | 673 | u32 apic_id = (lapicid_start * (i / modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 674 | printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", |
| 675 | i, j, apic_id); |
| 676 | |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 677 | struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 678 | if (cpu) |
| 679 | amd_cpu_topology(cpu, i, j); |
| 680 | } //j |
| 681 | } |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 682 | } |
| 683 | |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 684 | static void cpu_bus_init(struct device *dev) |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 685 | { |
| 686 | initialize_cpus(dev->link_list); |
| 687 | } |
| 688 | |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 689 | static struct device_operations cpu_bus_ops = { |
Nico Huber | 2f8ba69 | 2020-04-05 14:05:24 +0200 | [diff] [blame] | 690 | .read_resources = noop_read_resources, |
| 691 | .set_resources = noop_set_resources, |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 692 | .init = cpu_bus_init, |
| 693 | .scan_bus = cpu_bus_scan, |
| 694 | }; |
| 695 | |
| 696 | static void root_complex_enable_dev(struct device *dev) |
| 697 | { |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 698 | /* Set the operations if it is a special bus type */ |
| 699 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 700 | dev->ops = &pci_domain_ops; |
| 701 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 702 | dev->ops = &cpu_bus_ops; |
| 703 | } |
| 704 | } |
| 705 | |
| 706 | struct chip_operations northbridge_amd_agesa_family16kb_root_complex_ops = { |
| 707 | CHIP_NAME("AMD FAM16 Root Complex") |
| 708 | .enable_dev = root_complex_enable_dev, |
| 709 | }; |
Bruce Griffith | 76db07e | 2013-07-07 02:06:53 -0600 | [diff] [blame] | 710 | |
| 711 | /********************************************************************* |
| 712 | * Change the vendor / device IDs to match the generic VBIOS header. * |
| 713 | *********************************************************************/ |
| 714 | u32 map_oprom_vendev(u32 vendev) |
| 715 | { |
| 716 | u32 new_vendev = vendev; |
| 717 | |
Elyes HAOUAS | 0ce41f1 | 2018-11-13 10:03:31 +0100 | [diff] [blame] | 718 | switch (vendev) { |
Bruce Griffith | 76db07e | 2013-07-07 02:06:53 -0600 | [diff] [blame] | 719 | case 0x10029830: |
| 720 | case 0x10029831: |
| 721 | case 0x10029832: |
| 722 | case 0x10029833: |
| 723 | case 0x10029834: |
| 724 | case 0x10029835: |
| 725 | case 0x10029836: |
| 726 | case 0x10029837: |
| 727 | case 0x10029838: |
| 728 | case 0x10029839: |
| 729 | case 0x1002983A: |
| 730 | case 0x1002983D: |
| 731 | new_vendev = 0x10029830; // This is the default value in AMD-generated VBIOS |
| 732 | break; |
| 733 | default: |
| 734 | break; |
| 735 | } |
| 736 | |
| 737 | if (vendev != new_vendev) |
| 738 | printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", vendev, new_vendev); |
| 739 | |
| 740 | return new_vendev; |
| 741 | } |