Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <console/console.h> |
| 17 | #include <arch/io.h> |
Kyösti Mälkki | 8ae16a4 | 2014-06-19 20:44:34 +0300 | [diff] [blame] | 18 | #include <arch/acpi.h> |
Vladimir Serbinenko | db09b062 | 2014-10-08 22:15:17 +0200 | [diff] [blame] | 19 | #include <arch/acpigen.h> |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 20 | #include <stdint.h> |
| 21 | #include <device/device.h> |
| 22 | #include <device/pci.h> |
| 23 | #include <device/pci_ids.h> |
| 24 | #include <device/hypertransport.h> |
| 25 | #include <stdlib.h> |
| 26 | #include <string.h> |
| 27 | #include <lib.h> |
| 28 | #include <cpu/cpu.h> |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 29 | #include <cpu/x86/lapic.h> |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 30 | #include <cpu/amd/msr.h> |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 31 | #include <cpu/amd/mtrr.h> |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 32 | #include <Porting.h> |
| 33 | #include <AGESA.h> |
| 34 | #include <Options.h> |
| 35 | #include <Topology.h> |
Kyösti Mälkki | 28c4d2f | 2016-11-25 11:21:02 +0200 | [diff] [blame] | 36 | #include <northbridge/amd/agesa/state_machine.h> |
Kyösti Mälkki | d610c58 | 2017-03-05 06:28:18 +0200 | [diff] [blame] | 37 | #include <northbridge/amd/agesa/agesa_helper.h> |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 38 | |
Kyösti Mälkki | 113f670 | 2018-05-20 20:12:32 +0300 | [diff] [blame] | 39 | #define MAX_NODE_NUMS MAX_NODES |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 40 | |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 41 | typedef struct dram_base_mask { |
| 42 | u32 base; //[47:27] at [28:8] |
| 43 | u32 mask; //[47:27] at [28:8] and enable at bit 0 |
| 44 | } dram_base_mask_t; |
| 45 | |
| 46 | static unsigned node_nums; |
| 47 | static unsigned sblink; |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 48 | static struct device *__f0_dev[MAX_NODE_NUMS]; |
| 49 | static struct device *__f1_dev[MAX_NODE_NUMS]; |
| 50 | static struct device *__f2_dev[MAX_NODE_NUMS]; |
| 51 | static struct device *__f4_dev[MAX_NODE_NUMS]; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 52 | static unsigned fx_devs = 0; |
| 53 | |
| 54 | static dram_base_mask_t get_dram_base_mask(u32 nodeid) |
| 55 | { |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 56 | struct device *dev; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 57 | dram_base_mask_t d; |
| 58 | dev = __f1_dev[0]; |
| 59 | u32 temp; |
| 60 | temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] |
| 61 | d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too |
| 62 | temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] |
Elyes HAOUAS | 27e1801 | 2017-06-27 23:14:51 +0200 | [diff] [blame] | 63 | d.mask |= temp << 21; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 64 | temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] |
| 65 | d.mask |= (temp & 1); // enable bit |
| 66 | d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too |
| 67 | temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] |
Elyes HAOUAS | 27e1801 | 2017-06-27 23:14:51 +0200 | [diff] [blame] | 68 | d.base |= temp << 21; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 69 | return d; |
| 70 | } |
| 71 | |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 72 | static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 73 | u32 io_min, u32 io_max) |
| 74 | { |
| 75 | u32 i; |
| 76 | u32 tempreg; |
| 77 | /* io range allocation */ |
Elyes HAOUAS | 27e1801 | 2017-06-27 23:14:51 +0200 | [diff] [blame] | 78 | tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit |
Elyes HAOUAS | 1d8daa6 | 2016-09-18 08:50:54 +0200 | [diff] [blame] | 79 | for (i = 0; i < node_nums; i++) |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 80 | pci_write_config32(__f1_dev[i], reg+4, tempreg); |
Elyes HAOUAS | 27e1801 | 2017-06-27 23:14:51 +0200 | [diff] [blame] | 81 | tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? |
Elyes HAOUAS | 1d8daa6 | 2016-09-18 08:50:54 +0200 | [diff] [blame] | 82 | for (i = 0; i < node_nums; i++) |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 83 | pci_write_config32(__f1_dev[i], reg, tempreg); |
| 84 | } |
| 85 | |
| 86 | static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) |
| 87 | { |
| 88 | u32 i; |
| 89 | u32 tempreg; |
| 90 | /* io range allocation */ |
Elyes HAOUAS | 27e1801 | 2017-06-27 23:14:51 +0200 | [diff] [blame] | 91 | tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit |
Elyes HAOUAS | 1d8daa6 | 2016-09-18 08:50:54 +0200 | [diff] [blame] | 92 | for (i = 0; i < nodes; i++) |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 93 | pci_write_config32(__f1_dev[i], reg+4, tempreg); |
| 94 | tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); |
Elyes HAOUAS | 1d8daa6 | 2016-09-18 08:50:54 +0200 | [diff] [blame] | 95 | for (i = 0; i < node_nums; i++) |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 96 | pci_write_config32(__f1_dev[i], reg, tempreg); |
| 97 | } |
| 98 | |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 99 | static struct device *get_node_pci(u32 nodeid, u32 fn) |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 100 | { |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 101 | return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 102 | } |
| 103 | |
| 104 | static void get_fx_devs(void) |
| 105 | { |
| 106 | int i; |
| 107 | for (i = 0; i < MAX_NODE_NUMS; i++) { |
| 108 | __f0_dev[i] = get_node_pci(i, 0); |
| 109 | __f1_dev[i] = get_node_pci(i, 1); |
| 110 | __f2_dev[i] = get_node_pci(i, 2); |
| 111 | __f4_dev[i] = get_node_pci(i, 4); |
| 112 | if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) |
| 113 | fx_devs = i+1; |
| 114 | } |
| 115 | if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { |
| 116 | die("Cannot find 0:0x18.[0|1]\n"); |
| 117 | } |
| 118 | printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs); |
| 119 | } |
| 120 | |
| 121 | static u32 f1_read_config32(unsigned reg) |
| 122 | { |
| 123 | if (fx_devs == 0) |
| 124 | get_fx_devs(); |
| 125 | return pci_read_config32(__f1_dev[0], reg); |
| 126 | } |
| 127 | |
| 128 | static void f1_write_config32(unsigned reg, u32 value) |
| 129 | { |
| 130 | int i; |
| 131 | if (fx_devs == 0) |
| 132 | get_fx_devs(); |
Elyes HAOUAS | 5a7e72f | 2016-08-23 21:36:02 +0200 | [diff] [blame] | 133 | for (i = 0; i < fx_devs; i++) { |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 134 | struct device *dev; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 135 | dev = __f1_dev[i]; |
| 136 | if (dev && dev->enabled) { |
| 137 | pci_write_config32(dev, reg, value); |
| 138 | } |
| 139 | } |
| 140 | } |
| 141 | |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 142 | static u32 amdfam16_nodeid(struct device *dev) |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 143 | { |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 144 | return (dev->path.pci.devfn >> 3) - CONFIG_CDB; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 145 | } |
| 146 | |
| 147 | static void set_vga_enable_reg(u32 nodeid, u32 linkn) |
| 148 | { |
| 149 | u32 val; |
| 150 | |
Elyes HAOUAS | 27e1801 | 2017-06-27 23:14:51 +0200 | [diff] [blame] | 151 | val = 1 | (nodeid << 4) | (linkn << 12); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 152 | /* it will routing |
| 153 | * (1)mmio 0xa0000:0xbffff |
| 154 | * (2)io 0x3b0:0x3bb, 0x3c0:0x3df |
| 155 | */ |
| 156 | f1_write_config32(0xf4, val); |
| 157 | |
| 158 | } |
| 159 | |
| 160 | /** |
| 161 | * @return |
| 162 | * @retval 2 resoure does not exist, usable |
| 163 | * @retval 0 resource exists, not usable |
| 164 | * @retval 1 resource exist, resource has been allocated before |
| 165 | */ |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 166 | static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid, |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 167 | unsigned goal_link) |
| 168 | { |
| 169 | struct resource *res; |
| 170 | unsigned nodeid, link = 0; |
| 171 | int result; |
| 172 | res = 0; |
| 173 | for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 174 | struct device *dev; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 175 | dev = __f0_dev[nodeid]; |
| 176 | if (!dev) |
| 177 | continue; |
| 178 | for (link = 0; !res && (link < 8); link++) { |
| 179 | res = probe_resource(dev, IOINDEX(0x1000 + reg, link)); |
| 180 | } |
| 181 | } |
| 182 | result = 2; |
| 183 | if (res) { |
| 184 | result = 0; |
| 185 | if ((goal_link == (link - 1)) && |
| 186 | (goal_nodeid == (nodeid - 1)) && |
| 187 | (res->flags <= 1)) { |
| 188 | result = 1; |
| 189 | } |
| 190 | } |
| 191 | return result; |
| 192 | } |
| 193 | |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 194 | static struct resource *amdfam16_find_iopair(struct device *dev, unsigned nodeid, unsigned link) |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 195 | { |
| 196 | struct resource *resource; |
| 197 | u32 free_reg, reg; |
| 198 | resource = 0; |
| 199 | free_reg = 0; |
| 200 | for (reg = 0xc0; reg <= 0xd8; reg += 0x8) { |
| 201 | int result; |
| 202 | result = reg_useable(reg, dev, nodeid, link); |
| 203 | if (result == 1) { |
| 204 | /* I have been allocated this one */ |
| 205 | break; |
| 206 | } |
| 207 | else if (result > 1) { |
| 208 | /* I have a free register pair */ |
| 209 | free_reg = reg; |
| 210 | } |
| 211 | } |
| 212 | if (reg > 0xd8) { |
| 213 | reg = free_reg; // if no free, the free_reg still be 0 |
| 214 | } |
| 215 | |
| 216 | resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); |
| 217 | |
| 218 | return resource; |
| 219 | } |
| 220 | |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 221 | static struct resource *amdfam16_find_mempair(struct device *dev, u32 nodeid, u32 link) |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 222 | { |
| 223 | struct resource *resource; |
| 224 | u32 free_reg, reg; |
| 225 | resource = 0; |
| 226 | free_reg = 0; |
| 227 | for (reg = 0x80; reg <= 0xb8; reg += 0x8) { |
| 228 | int result; |
| 229 | result = reg_useable(reg, dev, nodeid, link); |
| 230 | if (result == 1) { |
| 231 | /* I have been allocated this one */ |
| 232 | break; |
| 233 | } |
| 234 | else if (result > 1) { |
| 235 | /* I have a free register pair */ |
| 236 | free_reg = reg; |
| 237 | } |
| 238 | } |
| 239 | if (reg > 0xb8) { |
| 240 | reg = free_reg; |
| 241 | } |
| 242 | |
| 243 | resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); |
| 244 | return resource; |
| 245 | } |
| 246 | |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 247 | static void amdfam16_link_read_bases(struct device *dev, u32 nodeid, u32 link) |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 248 | { |
| 249 | struct resource *resource; |
| 250 | |
| 251 | /* Initialize the io space constraints on the current bus */ |
| 252 | resource = amdfam16_find_iopair(dev, nodeid, link); |
| 253 | if (resource) { |
| 254 | u32 align; |
| 255 | align = log2(HT_IO_HOST_ALIGN); |
| 256 | resource->base = 0; |
| 257 | resource->size = 0; |
| 258 | resource->align = align; |
| 259 | resource->gran = align; |
| 260 | resource->limit = 0xffffUL; |
| 261 | resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE; |
| 262 | } |
| 263 | |
| 264 | /* Initialize the prefetchable memory constraints on the current bus */ |
| 265 | resource = amdfam16_find_mempair(dev, nodeid, link); |
| 266 | if (resource) { |
| 267 | resource->base = 0; |
| 268 | resource->size = 0; |
| 269 | resource->align = log2(HT_MEM_HOST_ALIGN); |
| 270 | resource->gran = log2(HT_MEM_HOST_ALIGN); |
| 271 | resource->limit = 0xffffffffffULL; |
| 272 | resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; |
| 273 | resource->flags |= IORESOURCE_BRIDGE; |
| 274 | } |
| 275 | |
| 276 | /* Initialize the memory constraints on the current bus */ |
| 277 | resource = amdfam16_find_mempair(dev, nodeid, link); |
| 278 | if (resource) { |
| 279 | resource->base = 0; |
| 280 | resource->size = 0; |
| 281 | resource->align = log2(HT_MEM_HOST_ALIGN); |
| 282 | resource->gran = log2(HT_MEM_HOST_ALIGN); |
| 283 | resource->limit = 0xffffffffffULL; |
| 284 | resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; |
| 285 | } |
| 286 | |
| 287 | } |
| 288 | |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 289 | static void read_resources(struct device *dev) |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 290 | { |
| 291 | u32 nodeid; |
| 292 | struct bus *link; |
| 293 | |
| 294 | nodeid = amdfam16_nodeid(dev); |
| 295 | for (link = dev->link_list; link; link = link->next) { |
| 296 | if (link->children) { |
| 297 | amdfam16_link_read_bases(dev, nodeid, link->link_num); |
| 298 | } |
| 299 | } |
Edward O'Callaghan | 66c6532 | 2014-11-21 01:43:38 +1100 | [diff] [blame] | 300 | |
| 301 | /* |
| 302 | * This MMCONF resource must be reserved in the PCI_DOMAIN. |
| 303 | * It is not honored by the coreboot resource allocator if it is in |
| 304 | * the APIC_CLUSTER. |
| 305 | */ |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 306 | mmconf_resource(dev, MMIO_CONF_BASE); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 307 | } |
| 308 | |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 309 | static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 310 | { |
| 311 | resource_t rbase, rend; |
| 312 | unsigned reg, link_num; |
| 313 | char buf[50]; |
| 314 | |
| 315 | /* Make certain the resource has actually been set */ |
| 316 | if (!(resource->flags & IORESOURCE_ASSIGNED)) { |
| 317 | return; |
| 318 | } |
| 319 | |
| 320 | /* If I have already stored this resource don't worry about it */ |
| 321 | if (resource->flags & IORESOURCE_STORED) { |
| 322 | return; |
| 323 | } |
| 324 | |
| 325 | /* Only handle PCI memory and IO resources */ |
| 326 | if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) |
| 327 | return; |
| 328 | |
| 329 | /* Ensure I am actually looking at a resource of function 1 */ |
| 330 | if ((resource->index & 0xffff) < 0x1000) { |
| 331 | return; |
| 332 | } |
| 333 | /* Get the base address */ |
| 334 | rbase = resource->base; |
| 335 | |
| 336 | /* Get the limit (rounded up) */ |
| 337 | rend = resource_end(resource); |
| 338 | |
| 339 | /* Get the register and link */ |
| 340 | reg = resource->index & 0xfff; // 4k |
| 341 | link_num = IOINDEX_LINK(resource->index); |
| 342 | |
| 343 | if (resource->flags & IORESOURCE_IO) { |
| 344 | set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); |
| 345 | } |
| 346 | else if (resource->flags & IORESOURCE_MEM) { |
Edward O'Callaghan | ae5fd34 | 2014-11-20 19:58:09 +1100 | [diff] [blame] | 347 | set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums);// [39:8] |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 348 | } |
| 349 | resource->flags |= IORESOURCE_STORED; |
Elyes HAOUAS | 0d4b11a | 2016-10-03 21:57:21 +0200 | [diff] [blame] | 350 | snprintf(buf, sizeof(buf), " <node %x link %x>", |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 351 | nodeid, link_num); |
| 352 | report_resource_stored(dev, resource, buf); |
| 353 | } |
| 354 | |
| 355 | /** |
| 356 | * I tried to reuse the resource allocation code in set_resource() |
| 357 | * but it is too difficult to deal with the resource allocation magic. |
| 358 | */ |
| 359 | |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 360 | static void create_vga_resource(struct device *dev, unsigned nodeid) |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 361 | { |
| 362 | struct bus *link; |
| 363 | |
| 364 | /* find out which link the VGA card is connected, |
| 365 | * we only deal with the 'first' vga card */ |
| 366 | for (link = dev->link_list; link; link = link->next) { |
| 367 | if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { |
Martin Roth | 77a58b9 | 2017-06-24 14:45:48 -0600 | [diff] [blame] | 368 | #if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 369 | extern struct device *vga_pri; // the primary vga device, defined in device.c |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 370 | printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, |
| 371 | link->secondary,link->subordinate); |
| 372 | /* We need to make sure the vga_pri is under the link */ |
Elyes HAOUAS | 1d8daa6 | 2016-09-18 08:50:54 +0200 | [diff] [blame] | 373 | if ((vga_pri->bus->secondary >= link->secondary) && |
| 374 | (vga_pri->bus->secondary <= link->subordinate)) |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 375 | #endif |
| 376 | break; |
| 377 | } |
| 378 | } |
| 379 | |
| 380 | /* no VGA card installed */ |
| 381 | if (link == NULL) |
| 382 | return; |
| 383 | |
| 384 | printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, sblink); |
| 385 | set_vga_enable_reg(nodeid, sblink); |
| 386 | } |
| 387 | |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 388 | static void set_resources(struct device *dev) |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 389 | { |
| 390 | unsigned nodeid; |
| 391 | struct bus *bus; |
| 392 | struct resource *res; |
| 393 | |
| 394 | /* Find the nodeid */ |
| 395 | nodeid = amdfam16_nodeid(dev); |
| 396 | |
| 397 | create_vga_resource(dev, nodeid); //TODO: do we need this? |
| 398 | |
| 399 | /* Set each resource we have found */ |
| 400 | for (res = dev->resource_list; res; res = res->next) { |
| 401 | set_resource(dev, res, nodeid); |
| 402 | } |
| 403 | |
| 404 | for (bus = dev->link_list; bus; bus = bus->next) { |
| 405 | if (bus->children) { |
| 406 | assign_resources(bus); |
| 407 | } |
| 408 | } |
| 409 | } |
| 410 | |
Vladimir Serbinenko | db09b062 | 2014-10-08 22:15:17 +0200 | [diff] [blame] | 411 | |
Vladimir Serbinenko | 807127f | 2014-11-09 13:36:18 +0100 | [diff] [blame] | 412 | static unsigned long acpi_fill_hest(acpi_hest_t *hest) |
Vladimir Serbinenko | db09b062 | 2014-10-08 22:15:17 +0200 | [diff] [blame] | 413 | { |
| 414 | void *addr, *current; |
| 415 | |
| 416 | /* Skip the HEST header. */ |
| 417 | current = (void *)(hest + 1); |
| 418 | |
| 419 | addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); |
| 420 | if (addr != NULL) |
Stefan Reinauer | 77a1d1a | 2015-07-21 12:48:17 -0700 | [diff] [blame] | 421 | current += acpi_create_hest_error_source(hest, current, 0, |
| 422 | addr + 2, *(UINT16 *)addr - 2); |
Vladimir Serbinenko | db09b062 | 2014-10-08 22:15:17 +0200 | [diff] [blame] | 423 | |
| 424 | addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); |
| 425 | if (addr != NULL) |
Stefan Reinauer | 77a1d1a | 2015-07-21 12:48:17 -0700 | [diff] [blame] | 426 | current += acpi_create_hest_error_source(hest, current, 1, |
| 427 | addr + 2, *(UINT16 *)addr - 2); |
Vladimir Serbinenko | db09b062 | 2014-10-08 22:15:17 +0200 | [diff] [blame] | 428 | |
| 429 | return (unsigned long)current; |
| 430 | } |
| 431 | |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 432 | static void northbridge_fill_ssdt_generator(struct device *device) |
Vladimir Serbinenko | db09b062 | 2014-10-08 22:15:17 +0200 | [diff] [blame] | 433 | { |
| 434 | msr_t msr; |
| 435 | char pscope[] = "\\_SB.PCI0"; |
| 436 | |
| 437 | acpigen_write_scope(pscope); |
| 438 | msr = rdmsr(TOP_MEM); |
| 439 | acpigen_write_name_dword("TOM1", msr.lo); |
| 440 | msr = rdmsr(TOP_MEM2); |
| 441 | /* |
| 442 | * Since XP only implements parts of ACPI 2.0, we can't use a qword |
| 443 | * here. |
| 444 | * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt |
| 445 | * slide 22ff. |
| 446 | * Shift value right by 20 bit to make it fit into 32bit, |
| 447 | * giving us 1MB granularity and a limit of almost 4Exabyte of memory. |
| 448 | */ |
| 449 | acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); |
| 450 | acpigen_pop_len(); |
| 451 | } |
| 452 | |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 453 | static unsigned long agesa_write_acpi_tables(struct device *device, |
Alexander Couzens | 83fc32f | 2015-04-12 22:28:37 +0200 | [diff] [blame] | 454 | unsigned long current, |
Vladimir Serbinenko | db09b062 | 2014-10-08 22:15:17 +0200 | [diff] [blame] | 455 | acpi_rsdp_t *rsdp) |
| 456 | { |
| 457 | acpi_srat_t *srat; |
| 458 | acpi_slit_t *slit; |
| 459 | acpi_header_t *ssdt; |
| 460 | acpi_header_t *alib; |
| 461 | acpi_header_t *ivrs; |
| 462 | acpi_hest_t *hest; |
| 463 | |
| 464 | /* HEST */ |
| 465 | current = ALIGN(current, 8); |
| 466 | hest = (acpi_hest_t *)current; |
Vladimir Serbinenko | 807127f | 2014-11-09 13:36:18 +0100 | [diff] [blame] | 467 | acpi_write_hest((void *)current, acpi_fill_hest); |
Vladimir Serbinenko | db09b062 | 2014-10-08 22:15:17 +0200 | [diff] [blame] | 468 | acpi_add_table(rsdp, (void *)current); |
| 469 | current += ((acpi_header_t *)current)->length; |
| 470 | |
| 471 | current = ALIGN(current, 8); |
| 472 | printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); |
| 473 | ivrs = agesawrapper_getlateinitptr(PICK_IVRS); |
| 474 | if (ivrs != NULL) { |
| 475 | memcpy((void *)current, ivrs, ivrs->length); |
| 476 | ivrs = (acpi_header_t *) current; |
| 477 | current += ivrs->length; |
| 478 | acpi_add_table(rsdp, ivrs); |
| 479 | } else { |
| 480 | printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n"); |
| 481 | } |
| 482 | |
| 483 | /* SRAT */ |
| 484 | current = ALIGN(current, 8); |
| 485 | printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); |
| 486 | srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); |
| 487 | if (srat != NULL) { |
| 488 | memcpy((void *)current, srat, srat->header.length); |
| 489 | srat = (acpi_srat_t *) current; |
| 490 | current += srat->header.length; |
| 491 | acpi_add_table(rsdp, srat); |
| 492 | } else { |
| 493 | printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); |
| 494 | } |
| 495 | |
| 496 | /* SLIT */ |
| 497 | current = ALIGN(current, 8); |
| 498 | printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); |
| 499 | slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); |
| 500 | if (slit != NULL) { |
| 501 | memcpy((void *)current, slit, slit->header.length); |
| 502 | slit = (acpi_slit_t *) current; |
| 503 | current += slit->header.length; |
| 504 | acpi_add_table(rsdp, slit); |
| 505 | } else { |
| 506 | printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); |
| 507 | } |
| 508 | |
| 509 | /* ALIB */ |
| 510 | current = ALIGN(current, 16); |
| 511 | printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); |
| 512 | alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); |
| 513 | if (alib != NULL) { |
| 514 | memcpy((void *)current, alib, alib->length); |
| 515 | alib = (acpi_header_t *) current; |
| 516 | current += alib->length; |
| 517 | acpi_add_table(rsdp, (void *)alib); |
| 518 | } |
| 519 | else { |
| 520 | printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); |
| 521 | } |
| 522 | |
| 523 | /* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */ |
| 524 | /* SSDT */ |
| 525 | current = ALIGN(current, 16); |
| 526 | printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); |
| 527 | ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); |
| 528 | if (ssdt != NULL) { |
| 529 | memcpy((void *)current, ssdt, ssdt->length); |
| 530 | ssdt = (acpi_header_t *) current; |
| 531 | current += ssdt->length; |
| 532 | } |
| 533 | else { |
| 534 | printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n"); |
| 535 | } |
| 536 | acpi_add_table(rsdp,ssdt); |
| 537 | |
| 538 | printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); |
| 539 | |
| 540 | return current; |
| 541 | } |
| 542 | |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 543 | static struct device_operations northbridge_operations = { |
| 544 | .read_resources = read_resources, |
| 545 | .set_resources = set_resources, |
| 546 | .enable_resources = pci_dev_enable_resources, |
Edward O'Callaghan | d994ef1 | 2014-11-21 02:22:33 +1100 | [diff] [blame] | 547 | .init = DEVICE_NOOP, |
Vladimir Serbinenko | db09b062 | 2014-10-08 22:15:17 +0200 | [diff] [blame] | 548 | .acpi_fill_ssdt_generator = northbridge_fill_ssdt_generator, |
| 549 | .write_acpi_tables = agesa_write_acpi_tables, |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 550 | .enable = 0, |
| 551 | .ops_pci = 0, |
| 552 | }; |
| 553 | |
| 554 | static const struct pci_driver family16_northbridge __pci_driver = { |
| 555 | .ops = &northbridge_operations, |
| 556 | .vendor = PCI_VENDOR_ID_AMD, |
| 557 | .device = PCI_DEVICE_ID_AMD_16H_MODEL_000F_NB_HT, |
| 558 | }; |
| 559 | |
| 560 | static const struct pci_driver family10_northbridge __pci_driver = { |
| 561 | .ops = &northbridge_operations, |
| 562 | .vendor = PCI_VENDOR_ID_AMD, |
| 563 | .device = PCI_DEVICE_ID_AMD_10H_NB_HT, |
| 564 | }; |
| 565 | |
Kyösti Mälkki | 4ee82c6 | 2014-11-25 16:03:12 +0200 | [diff] [blame] | 566 | static void fam16_finalize(void *chip_info) |
| 567 | { |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 568 | struct device *dev; |
Kyösti Mälkki | 4ee82c6 | 2014-11-25 16:03:12 +0200 | [diff] [blame] | 569 | u32 value; |
| 570 | dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */ |
| 571 | pci_write_config32(dev, 0xF8, 0); |
| 572 | pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ |
| 573 | |
| 574 | /* disable No Snoop */ |
| 575 | dev = dev_find_slot(0, PCI_DEVFN(1, 1)); |
| 576 | value = pci_read_config32(dev, 0x60); |
| 577 | value &= ~(1 << 11); |
| 578 | pci_write_config32(dev, 0x60, value); |
| 579 | } |
| 580 | |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 581 | struct chip_operations northbridge_amd_agesa_family16kb_ops = { |
| 582 | CHIP_NAME("AMD FAM16 Northbridge") |
| 583 | .enable_dev = 0, |
Kyösti Mälkki | 4ee82c6 | 2014-11-25 16:03:12 +0200 | [diff] [blame] | 584 | .final = fam16_finalize, |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 585 | }; |
| 586 | |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 587 | static void domain_read_resources(struct device *dev) |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 588 | { |
| 589 | unsigned reg; |
| 590 | |
| 591 | /* Find the already assigned resource pairs */ |
| 592 | get_fx_devs(); |
| 593 | for (reg = 0x80; reg <= 0xd8; reg+= 0x08) { |
| 594 | u32 base, limit; |
| 595 | base = f1_read_config32(reg); |
| 596 | limit = f1_read_config32(reg + 0x04); |
| 597 | /* Is this register allocated? */ |
| 598 | if ((base & 3) != 0) { |
| 599 | unsigned nodeid, reg_link; |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 600 | struct device *reg_dev; |
Elyes HAOUAS | 1d8daa6 | 2016-09-18 08:50:54 +0200 | [diff] [blame] | 601 | if (reg < 0xc0) { // mmio |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 602 | nodeid = (limit & 0xf) + (base&0x30); |
| 603 | } else { // io |
| 604 | nodeid = (limit & 0xf) + ((base>>4)&0x30); |
| 605 | } |
| 606 | reg_link = (limit >> 4) & 7; |
| 607 | reg_dev = __f0_dev[nodeid]; |
| 608 | if (reg_dev) { |
| 609 | /* Reserve the resource */ |
| 610 | struct resource *res; |
| 611 | res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); |
| 612 | if (res) { |
| 613 | res->flags = 1; |
| 614 | } |
| 615 | } |
| 616 | } |
| 617 | } |
| 618 | /* FIXME: do we need to check extend conf space? |
| 619 | I don't believe that much preset value */ |
| 620 | |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 621 | pci_domain_read_resources(dev); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 622 | } |
| 623 | |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 624 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 625 | struct hw_mem_hole_info { |
| 626 | unsigned hole_startk; |
| 627 | int node_id; |
| 628 | }; |
| 629 | static struct hw_mem_hole_info get_hw_mem_hole_info(void) |
| 630 | { |
| 631 | struct hw_mem_hole_info mem_hole; |
| 632 | int i; |
| 633 | mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; |
| 634 | mem_hole.node_id = -1; |
| 635 | for (i = 0; i < node_nums; i++) { |
| 636 | dram_base_mask_t d; |
| 637 | u32 hole; |
| 638 | d = get_dram_base_mask(i); |
| 639 | if (!(d.mask & 1)) continue; // no memory on this node |
| 640 | hole = pci_read_config32(__f1_dev[i], 0xf0); |
| 641 | if (hole & 2) { // we find the hole |
Elyes HAOUAS | 27e1801 | 2017-06-27 23:14:51 +0200 | [diff] [blame] | 642 | mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 643 | mem_hole.node_id = i; // record the node No with hole |
| 644 | break; // only one hole |
| 645 | } |
| 646 | } |
Kyösti Mälkki | 2f9b3af | 2014-06-26 05:30:54 +0300 | [diff] [blame] | 647 | |
| 648 | /* We need to double check if there is special set on base reg and limit reg |
| 649 | * are not continuous instead of hole, it will find out its hole_startk. |
| 650 | */ |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 651 | if (mem_hole.node_id == -1) { |
| 652 | resource_t limitk_pri = 0; |
Elyes HAOUAS | 1d8daa6 | 2016-09-18 08:50:54 +0200 | [diff] [blame] | 653 | for (i = 0; i < node_nums; i++) { |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 654 | dram_base_mask_t d; |
| 655 | resource_t base_k, limit_k; |
| 656 | d = get_dram_base_mask(i); |
| 657 | if (!(d.base & 1)) continue; |
| 658 | base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; |
| 659 | if (base_k > 4 *1024 * 1024) break; // don't need to go to check |
| 660 | if (limitk_pri != base_k) { // we find the hole |
| 661 | mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G |
| 662 | mem_hole.node_id = i; |
| 663 | break; //only one hole |
| 664 | } |
| 665 | limit_k = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; |
| 666 | limitk_pri = limit_k; |
| 667 | } |
| 668 | } |
| 669 | return mem_hole; |
| 670 | } |
| 671 | #endif |
| 672 | |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 673 | static void domain_set_resources(struct device *dev) |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 674 | { |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 675 | unsigned long mmio_basek; |
| 676 | u32 pci_tolm; |
| 677 | int i, idx; |
| 678 | struct bus *link; |
| 679 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 680 | struct hw_mem_hole_info mem_hole; |
| 681 | u32 reset_memhole = 1; |
| 682 | #endif |
| 683 | |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 684 | pci_tolm = 0xffffffffUL; |
| 685 | for (link = dev->link_list; link; link = link->next) { |
| 686 | pci_tolm = find_pci_tolm(link); |
| 687 | } |
| 688 | |
| 689 | // FIXME handle interleaved nodes. If you fix this here, please fix |
| 690 | // amdk8, too. |
| 691 | mmio_basek = pci_tolm >> 10; |
| 692 | /* Round mmio_basek to something the processor can support */ |
| 693 | mmio_basek &= ~((1 << 6) -1); |
| 694 | |
| 695 | // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M |
| 696 | // MMIO hole. If you fix this here, please fix amdk8, too. |
| 697 | /* Round the mmio hole to 64M */ |
| 698 | mmio_basek &= ~((64*1024) - 1); |
| 699 | |
| 700 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 701 | /* if the hw mem hole is already set in raminit stage, here we will compare |
| 702 | * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will |
| 703 | * use hole_basek as mmio_basek and we don't need to reset hole. |
| 704 | * otherwise We reset the hole to the mmio_basek |
| 705 | */ |
| 706 | |
| 707 | mem_hole = get_hw_mem_hole_info(); |
| 708 | |
| 709 | // Use hole_basek as mmio_basek, and we don't need to reset hole anymore |
| 710 | if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { |
| 711 | mmio_basek = mem_hole.hole_startk; |
| 712 | reset_memhole = 0; |
| 713 | } |
| 714 | #endif |
| 715 | |
| 716 | idx = 0x10; |
| 717 | for (i = 0; i < node_nums; i++) { |
| 718 | dram_base_mask_t d; |
| 719 | resource_t basek, limitk, sizek; // 4 1T |
| 720 | |
| 721 | d = get_dram_base_mask(i); |
| 722 | |
| 723 | if (!(d.mask & 1)) continue; |
| 724 | basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here |
Edward O'Callaghan | ae5fd34 | 2014-11-20 19:58:09 +1100 | [diff] [blame] | 725 | limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 726 | |
| 727 | sizek = limitk - basek; |
| 728 | |
| 729 | /* see if we need a hole from 0xa0000 to 0xbffff */ |
| 730 | if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) { |
| 731 | ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek); |
| 732 | idx += 0x10; |
| 733 | basek = (8*64)+(16*16); |
| 734 | sizek = limitk - ((8*64)+(16*16)); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 735 | } |
| 736 | |
| 737 | //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); |
| 738 | |
Kyösti Mälkki | 26c6543 | 2014-06-26 05:30:54 +0300 | [diff] [blame] | 739 | /* split the region to accommodate pci memory space */ |
Elyes HAOUAS | 1d8daa6 | 2016-09-18 08:50:54 +0200 | [diff] [blame] | 740 | if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 741 | if (basek <= mmio_basek) { |
| 742 | unsigned pre_sizek; |
| 743 | pre_sizek = mmio_basek - basek; |
Elyes HAOUAS | 1d8daa6 | 2016-09-18 08:50:54 +0200 | [diff] [blame] | 744 | if (pre_sizek > 0) { |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 745 | ram_resource(dev, (idx | i), basek, pre_sizek); |
| 746 | idx += 0x10; |
| 747 | sizek -= pre_sizek; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 748 | } |
| 749 | basek = mmio_basek; |
| 750 | } |
| 751 | if ((basek + sizek) <= 4*1024*1024) { |
| 752 | sizek = 0; |
| 753 | } |
| 754 | else { |
| 755 | uint64_t topmem2 = bsp_topmem2(); |
| 756 | basek = 4*1024*1024; |
| 757 | sizek = topmem2/1024 - basek; |
| 758 | } |
| 759 | } |
| 760 | |
| 761 | ram_resource(dev, (idx | i), basek, sizek); |
| 762 | idx += 0x10; |
| 763 | printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", |
| 764 | i, mmio_basek, basek, limitk); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 765 | } |
| 766 | |
Kyösti Mälkki | 61be360 | 2017-04-15 20:07:53 +0300 | [diff] [blame] | 767 | add_uma_resource_below_tolm(dev, 7); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 768 | |
Elyes HAOUAS | 5a7e72f | 2016-08-23 21:36:02 +0200 | [diff] [blame] | 769 | for (link = dev->link_list; link; link = link->next) { |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 770 | if (link->children) { |
| 771 | assign_resources(link); |
| 772 | } |
| 773 | } |
| 774 | } |
| 775 | |
Kevin Cody-Little | 06d2323 | 2018-05-09 14:22:15 -0400 | [diff] [blame] | 776 | static const char *domain_acpi_name(const struct device *dev) |
| 777 | { |
| 778 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 779 | return "PCI0"; |
| 780 | |
| 781 | return NULL; |
| 782 | } |
| 783 | |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 784 | static struct device_operations pci_domain_ops = { |
| 785 | .read_resources = domain_read_resources, |
| 786 | .set_resources = domain_set_resources, |
Edward O'Callaghan | e9e1d7a | 2015-01-02 15:11:49 +1100 | [diff] [blame] | 787 | .init = DEVICE_NOOP, |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 788 | .scan_bus = pci_domain_scan_bus, |
Kevin Cody-Little | 06d2323 | 2018-05-09 14:22:15 -0400 | [diff] [blame] | 789 | .acpi_name = domain_acpi_name, |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 790 | }; |
| 791 | |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 792 | static void sysconf_init(struct device *dev) // first node |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 793 | { |
| 794 | sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 |
| 795 | node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] |
| 796 | } |
| 797 | |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 798 | static void add_more_links(struct device *dev, unsigned total_links) |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 799 | { |
| 800 | struct bus *link, *last = NULL; |
| 801 | int link_num; |
| 802 | |
| 803 | for (link = dev->link_list; link; link = link->next) |
| 804 | last = link; |
| 805 | |
| 806 | if (last) { |
| 807 | int links = total_links - last->link_num; |
| 808 | link_num = last->link_num; |
| 809 | if (links > 0) { |
| 810 | link = malloc(links*sizeof(*link)); |
| 811 | if (!link) |
| 812 | die("Couldn't allocate more links!\n"); |
| 813 | memset(link, 0, links*sizeof(*link)); |
| 814 | last->next = link; |
| 815 | } |
| 816 | } |
| 817 | else { |
| 818 | link_num = -1; |
| 819 | link = malloc(total_links*sizeof(*link)); |
| 820 | memset(link, 0, total_links*sizeof(*link)); |
| 821 | dev->link_list = link; |
| 822 | } |
| 823 | |
| 824 | for (link_num = link_num + 1; link_num < total_links; link_num++) { |
| 825 | link->link_num = link_num; |
| 826 | link->dev = dev; |
| 827 | link->next = link + 1; |
| 828 | last = link; |
| 829 | link = link->next; |
| 830 | } |
| 831 | last->next = NULL; |
| 832 | } |
| 833 | |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 834 | static void cpu_bus_scan(struct device *dev) |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 835 | { |
| 836 | struct bus *cpu_bus; |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 837 | struct device *dev_mc; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 838 | int i,j; |
| 839 | int coreid_bits; |
| 840 | int core_max = 0; |
| 841 | unsigned ApicIdCoreIdSize; |
| 842 | unsigned core_nums; |
| 843 | int siblings = 0; |
| 844 | unsigned int family; |
| 845 | |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 846 | dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); |
| 847 | if (!dev_mc) { |
| 848 | printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); |
| 849 | die(""); |
| 850 | } |
| 851 | sysconf_init(dev_mc); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 852 | |
| 853 | /* Get Max Number of cores(MNC) */ |
Kyösti Mälkki | d41feed | 2017-09-24 16:23:57 +0300 | [diff] [blame] | 854 | coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 855 | core_max = 1 << (coreid_bits & 0x000F); //mnc |
| 856 | |
| 857 | ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF); |
| 858 | if (ApicIdCoreIdSize) { |
| 859 | core_nums = (1 << ApicIdCoreIdSize) - 1; |
| 860 | } else { |
| 861 | core_nums = 3; //quad core |
| 862 | } |
| 863 | |
| 864 | /* Find which cpus are present */ |
| 865 | cpu_bus = dev->link_list; |
| 866 | for (i = 0; i < node_nums; i++) { |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 867 | struct device *cdb_dev; |
Kyösti Mälkki | edf51d2 | 2018-05-20 22:38:00 +0300 | [diff] [blame] | 868 | unsigned devn; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 869 | struct bus *pbus; |
| 870 | |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 871 | devn = CONFIG_CDB + i; |
| 872 | pbus = dev_mc->bus; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 873 | |
| 874 | /* Find the cpu's pci device */ |
Kyösti Mälkki | edf51d2 | 2018-05-20 22:38:00 +0300 | [diff] [blame] | 875 | cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(devn, 0)); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 876 | if (!cdb_dev) { |
| 877 | /* If I am probing things in a weird order |
| 878 | * ensure all of the cpu's pci devices are found. |
| 879 | */ |
| 880 | int fn; |
Elyes HAOUAS | 5a7e72f | 2016-08-23 21:36:02 +0200 | [diff] [blame] | 881 | for (fn = 0; fn <= 5; fn++) { //FBDIMM? |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 882 | cdb_dev = pci_probe_dev(NULL, pbus, |
| 883 | PCI_DEVFN(devn, fn)); |
| 884 | } |
Kyösti Mälkki | edf51d2 | 2018-05-20 22:38:00 +0300 | [diff] [blame] | 885 | cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(devn, 0)); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 886 | } else { |
| 887 | /* Ok, We need to set the links for that device. |
| 888 | * otherwise the device under it will not be scanned |
| 889 | */ |
Kyösti Mälkki | 2a2d613 | 2015-02-04 13:25:37 +0200 | [diff] [blame] | 890 | add_more_links(cdb_dev, 4); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 891 | } |
| 892 | |
| 893 | family = cpuid_eax(1); |
| 894 | family = (family >> 20) & 0xFF; |
| 895 | if (family == 1) { //f10 |
| 896 | u32 dword; |
Kyösti Mälkki | edf51d2 | 2018-05-20 22:38:00 +0300 | [diff] [blame] | 897 | cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(devn, 3)); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 898 | dword = pci_read_config32(cdb_dev, 0xe8); |
| 899 | siblings = ((dword & BIT15) >> 13) | ((dword & (BIT13 | BIT12)) >> 12); |
| 900 | } else if (family == 7) {//f16 |
Kyösti Mälkki | edf51d2 | 2018-05-20 22:38:00 +0300 | [diff] [blame] | 901 | cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(devn, 5)); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 902 | if (cdb_dev && cdb_dev->enabled) { |
| 903 | siblings = pci_read_config32(cdb_dev, 0x84); |
| 904 | siblings &= 0xFF; |
| 905 | } |
| 906 | } else { |
| 907 | siblings = 0; //default one core |
| 908 | } |
| 909 | int enable_node = cdb_dev && cdb_dev->enabled; |
| 910 | printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", |
| 911 | dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); |
| 912 | |
Elyes HAOUAS | 1d8daa6 | 2016-09-18 08:50:54 +0200 | [diff] [blame] | 913 | for (j = 0; j <= siblings; j++) { |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 914 | extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration; |
| 915 | u32 modules = TopologyConfiguration.PlatformNumberOfModules; |
| 916 | u32 lapicid_start = 0; |
| 917 | |
| 918 | /* |
| 919 | * APIC ID calucation is tightly coupled with AGESA v5 code. |
| 920 | * This calculation MUST match the assignment calculation done |
| 921 | * in LocalApicInitializationAtEarly() function. |
| 922 | * And reference GetLocalApicIdForCore() |
| 923 | * |
| 924 | * Apply apic enumeration rules |
| 925 | * For systems with >= 16 APICs, put the IO-APICs at 0..n and |
| 926 | * put the local-APICs at m..z |
| 927 | * |
| 928 | * This is needed because many IO-APIC devices only have 4 bits |
| 929 | * for their APIC id and therefore must reside at 0..15 |
Elyes HAOUAS | 6e8b3c1 | 2016-09-02 19:22:00 +0200 | [diff] [blame] | 930 | */ |
Kyösti Mälkki | 5003632 | 2016-05-18 13:35:21 +0300 | [diff] [blame] | 931 | |
Elyes HAOUAS | 6e8b3c1 | 2016-09-02 19:22:00 +0200 | [diff] [blame] | 932 | u8 plat_num_io_apics = 3; /* FIXME */ |
Kyösti Mälkki | 5003632 | 2016-05-18 13:35:21 +0300 | [diff] [blame] | 933 | |
| 934 | if ((node_nums * core_max) + plat_num_io_apics >= 0x10) { |
| 935 | lapicid_start = (plat_num_io_apics - 1) / core_max; |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 936 | lapicid_start = (lapicid_start + 1) * core_max; |
| 937 | printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); |
| 938 | } |
| 939 | u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); |
| 940 | printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", |
| 941 | i, j, apic_id); |
| 942 | |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 943 | struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 944 | if (cpu) |
| 945 | amd_cpu_topology(cpu, i, j); |
| 946 | } //j |
| 947 | } |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 948 | } |
| 949 | |
Kyösti Mälkki | e2c2a4c | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 950 | static void cpu_bus_init(struct device *dev) |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 951 | { |
| 952 | initialize_cpus(dev->link_list); |
| 953 | } |
| 954 | |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 955 | static struct device_operations cpu_bus_ops = { |
Edward O'Callaghan | 66c6532 | 2014-11-21 01:43:38 +1100 | [diff] [blame] | 956 | .read_resources = DEVICE_NOOP, |
| 957 | .set_resources = DEVICE_NOOP, |
Edward O'Callaghan | 812d2a4 | 2014-10-31 08:17:23 +1100 | [diff] [blame] | 958 | .enable_resources = DEVICE_NOOP, |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 959 | .init = cpu_bus_init, |
| 960 | .scan_bus = cpu_bus_scan, |
| 961 | }; |
| 962 | |
| 963 | static void root_complex_enable_dev(struct device *dev) |
| 964 | { |
| 965 | static int done = 0; |
| 966 | |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 967 | if (!done) { |
| 968 | setup_bsp_ramtop(); |
Siyuan Wang | 3e32cc0 | 2013-07-09 17:16:20 +0800 | [diff] [blame] | 969 | done = 1; |
| 970 | } |
| 971 | |
| 972 | /* Set the operations if it is a special bus type */ |
| 973 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 974 | dev->ops = &pci_domain_ops; |
| 975 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 976 | dev->ops = &cpu_bus_ops; |
| 977 | } |
| 978 | } |
| 979 | |
| 980 | struct chip_operations northbridge_amd_agesa_family16kb_root_complex_ops = { |
| 981 | CHIP_NAME("AMD FAM16 Root Complex") |
| 982 | .enable_dev = root_complex_enable_dev, |
| 983 | }; |
Bruce Griffith | 76db07e | 2013-07-07 02:06:53 -0600 | [diff] [blame] | 984 | |
| 985 | /********************************************************************* |
| 986 | * Change the vendor / device IDs to match the generic VBIOS header. * |
| 987 | *********************************************************************/ |
| 988 | u32 map_oprom_vendev(u32 vendev) |
| 989 | { |
| 990 | u32 new_vendev = vendev; |
| 991 | |
Elyes HAOUAS | 0ce41f1 | 2018-11-13 10:03:31 +0100 | [diff] [blame^] | 992 | switch (vendev) { |
Bruce Griffith | 76db07e | 2013-07-07 02:06:53 -0600 | [diff] [blame] | 993 | case 0x10029830: |
| 994 | case 0x10029831: |
| 995 | case 0x10029832: |
| 996 | case 0x10029833: |
| 997 | case 0x10029834: |
| 998 | case 0x10029835: |
| 999 | case 0x10029836: |
| 1000 | case 0x10029837: |
| 1001 | case 0x10029838: |
| 1002 | case 0x10029839: |
| 1003 | case 0x1002983A: |
| 1004 | case 0x1002983D: |
| 1005 | new_vendev = 0x10029830; // This is the default value in AMD-generated VBIOS |
| 1006 | break; |
| 1007 | default: |
| 1008 | break; |
| 1009 | } |
| 1010 | |
| 1011 | if (vendev != new_vendev) |
| 1012 | printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", vendev, new_vendev); |
| 1013 | |
| 1014 | return new_vendev; |
| 1015 | } |