Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 ChromeOS Authors |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <stdint.h> |
Aaron Durbin | 7492ec1 | 2013-02-08 22:18:04 -0600 | [diff] [blame] | 21 | #include <string.h> |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 22 | #include <cbmem.h> |
| 23 | #include <console/console.h> |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 24 | #include <arch/cpu.h> |
| 25 | #include <cpu/x86/bist.h> |
| 26 | #include <cpu/x86/msr.h> |
Aaron Durbin | 38d9423 | 2013-02-07 00:03:33 -0600 | [diff] [blame] | 27 | #include <cpu/x86/mtrr.h> |
| 28 | #include <cpu/x86/stack.h> |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 29 | #include <lib.h> |
| 30 | #include <timestamp.h> |
| 31 | #include <arch/io.h> |
Aaron Durbin | 7492ec1 | 2013-02-08 22:18:04 -0600 | [diff] [blame] | 32 | #include <arch/stages.h> |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 33 | #include <device/pci_def.h> |
| 34 | #include <cpu/x86/lapic.h> |
Aaron Durbin | f7cdfe5 | 2013-02-16 00:05:52 -0600 | [diff] [blame] | 35 | #include <cbfs.h> |
Aaron Durbin | bf396ff | 2013-02-11 21:50:35 -0600 | [diff] [blame] | 36 | #include <romstage_handoff.h> |
Aaron Durbin | b86113f | 2013-02-19 08:59:16 -0600 | [diff] [blame] | 37 | #include <reset.h> |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 38 | #if CONFIG_CHROMEOS |
| 39 | #include <vendorcode/google/chromeos/chromeos.h> |
| 40 | #endif |
| 41 | #include "haswell.h" |
| 42 | #include "northbridge/intel/haswell/haswell.h" |
| 43 | #include "northbridge/intel/haswell/raminit.h" |
| 44 | #include "southbridge/intel/lynxpoint/pch.h" |
| 45 | #include "southbridge/intel/lynxpoint/me.h" |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 46 | |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 47 | |
Aaron Durbin | b86113f | 2013-02-19 08:59:16 -0600 | [diff] [blame] | 48 | static inline void reset_system(void) |
| 49 | { |
| 50 | hard_reset(); |
| 51 | while (1) { |
| 52 | hlt(); |
| 53 | } |
| 54 | } |
| 55 | |
Aaron Durbin | 38d9423 | 2013-02-07 00:03:33 -0600 | [diff] [blame] | 56 | /* The cache-as-ram assembly file calls romstage_main() after setting up |
| 57 | * cache-as-ram. romstage_main() will then call the mainboards's |
| 58 | * mainboard_romstage_entry() function. That function then calls |
| 59 | * romstage_common() below. The reason for the back and forth is to provide |
| 60 | * common entry point from cache-as-ram while still allowing for code sharing. |
| 61 | * Because we can't use global variables the stack is used for allocations -- |
| 62 | * thus the need to call back and forth. */ |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 63 | |
Aaron Durbin | 38d9423 | 2013-02-07 00:03:33 -0600 | [diff] [blame] | 64 | |
| 65 | static inline u32 *stack_push(u32 *stack, u32 value) |
| 66 | { |
| 67 | stack = &stack[-1]; |
| 68 | *stack = value; |
| 69 | return stack; |
| 70 | } |
| 71 | |
Aaron Durbin | c0cbd6e | 2013-03-13 13:51:20 -0500 | [diff] [blame] | 72 | /* Romstage needs quite a bit of stack for decompressing images since the lzma |
| 73 | * lib keeps its state on the stack during romstage. */ |
| 74 | #define ROMSTAGE_RAM_STACK_SIZE 0x5000 |
Aaron Durbin | e2d9e5b | 2013-02-08 17:38:35 -0600 | [diff] [blame] | 75 | static unsigned long choose_top_of_stack(void) |
| 76 | { |
| 77 | unsigned long stack_top; |
Aaron Durbin | c0cbd6e | 2013-03-13 13:51:20 -0500 | [diff] [blame] | 78 | #if CONFIG_DYNAMIC_CBMEM |
| 79 | /* cbmem_add() does a find() before add(). */ |
| 80 | stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, |
| 81 | ROMSTAGE_RAM_STACK_SIZE); |
| 82 | stack_top += ROMSTAGE_RAM_STACK_SIZE; |
Aaron Durbin | e2d9e5b | 2013-02-08 17:38:35 -0600 | [diff] [blame] | 83 | #else |
| 84 | stack_top = ROMSTAGE_STACK; |
| 85 | #endif |
| 86 | return stack_top; |
| 87 | } |
| 88 | |
Aaron Durbin | 38d9423 | 2013-02-07 00:03:33 -0600 | [diff] [blame] | 89 | /* setup_romstage_stack_after_car() determines the stack to use after |
| 90 | * cache-as-ram is torn down as well as the MTRR settings to use. */ |
| 91 | static void *setup_romstage_stack_after_car(void) |
| 92 | { |
| 93 | unsigned long top_of_stack; |
| 94 | int num_mtrrs; |
| 95 | u32 *slot; |
| 96 | u32 mtrr_mask_upper; |
Aaron Durbin | 67481ddc | 2013-02-15 15:08:37 -0600 | [diff] [blame] | 97 | u32 top_of_ram; |
Aaron Durbin | 38d9423 | 2013-02-07 00:03:33 -0600 | [diff] [blame] | 98 | |
| 99 | /* Top of stack needs to be aligned to a 4-byte boundary. */ |
Aaron Durbin | e2d9e5b | 2013-02-08 17:38:35 -0600 | [diff] [blame] | 100 | top_of_stack = choose_top_of_stack() & ~3; |
Aaron Durbin | 38d9423 | 2013-02-07 00:03:33 -0600 | [diff] [blame] | 101 | slot = (void *)top_of_stack; |
| 102 | num_mtrrs = 0; |
| 103 | |
| 104 | /* The upper bits of the MTRR mask need to set according to the number |
| 105 | * of physical address bits. */ |
| 106 | mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1; |
| 107 | |
| 108 | /* The order for each MTTR is value then base with upper 32-bits of |
| 109 | * each value coming before the lower 32-bits. The reasoning for |
| 110 | * this ordering is to create a stack layout like the following: |
| 111 | * +0: Number of MTRRs |
| 112 | * +4: MTTR base 0 31:0 |
| 113 | * +8: MTTR base 0 63:32 |
| 114 | * +12: MTTR mask 0 31:0 |
| 115 | * +16: MTTR mask 0 63:32 |
| 116 | * +20: MTTR base 1 31:0 |
| 117 | * +24: MTTR base 1 63:32 |
| 118 | * +28: MTTR mask 1 31:0 |
| 119 | * +32: MTTR mask 1 63:32 |
| 120 | */ |
| 121 | |
| 122 | /* Cache the ROM as WP just below 4GiB. */ |
| 123 | slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ |
| 124 | slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRRphysMaskValid); |
| 125 | slot = stack_push(slot, 0); /* upper base */ |
| 126 | slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT); |
| 127 | num_mtrrs++; |
| 128 | |
| 129 | /* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */ |
| 130 | slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ |
| 131 | slot = stack_push(slot, ~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid); |
| 132 | slot = stack_push(slot, 0); /* upper base */ |
| 133 | slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK); |
| 134 | num_mtrrs++; |
| 135 | |
Aaron Durbin | 67481ddc | 2013-02-15 15:08:37 -0600 | [diff] [blame] | 136 | top_of_ram = get_top_of_ram(); |
Aaron Durbin | 38d9423 | 2013-02-07 00:03:33 -0600 | [diff] [blame] | 137 | /* Cache 8MiB below the top of ram. On haswell systems the top of |
| 138 | * ram under 4GiB is the start of the TSEG region. It is required to |
| 139 | * be 8MiB aligned. Set this area as cacheable so it can be used later |
| 140 | * for ramstage before setting up the entire RAM as cacheable. */ |
| 141 | slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ |
| 142 | slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid); |
| 143 | slot = stack_push(slot, 0); /* upper base */ |
Aaron Durbin | 67481ddc | 2013-02-15 15:08:37 -0600 | [diff] [blame] | 144 | slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK); |
| 145 | num_mtrrs++; |
| 146 | |
| 147 | /* Cache 8MiB at the top of ram. Top of ram on haswell systems |
| 148 | * is where the TSEG region resides. However, it is not restricted |
| 149 | * to SMM mode until SMM has been relocated. By setting the region |
| 150 | * to cacheable it provides faster access when relocating the SMM |
| 151 | * handler as well as using the TSEG region for other purposes. */ |
| 152 | slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ |
| 153 | slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid); |
| 154 | slot = stack_push(slot, 0); /* upper base */ |
| 155 | slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK); |
Aaron Durbin | 38d9423 | 2013-02-07 00:03:33 -0600 | [diff] [blame] | 156 | num_mtrrs++; |
| 157 | |
| 158 | /* Save the number of MTTRs to setup. Return the stack location |
| 159 | * pointing to the number of MTRRs. */ |
| 160 | slot = stack_push(slot, num_mtrrs); |
| 161 | |
| 162 | return slot; |
| 163 | } |
| 164 | |
| 165 | void * __attribute__((regparm(0))) romstage_main(unsigned long bist) |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 166 | { |
| 167 | int i; |
Aaron Durbin | 38d9423 | 2013-02-07 00:03:33 -0600 | [diff] [blame] | 168 | void *romstage_stack_after_car; |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 169 | const int num_guards = 4; |
| 170 | const u32 stack_guard = 0xdeadbeef; |
| 171 | u32 *stack_base = (void *)(CONFIG_DCACHE_RAM_BASE + |
| 172 | CONFIG_DCACHE_RAM_SIZE - |
| 173 | CONFIG_DCACHE_RAM_ROMSTAGE_STACK_SIZE); |
| 174 | |
| 175 | printk(BIOS_DEBUG, "Setting up stack guards.\n"); |
| 176 | for (i = 0; i < num_guards; i++) |
| 177 | stack_base[i] = stack_guard; |
| 178 | |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 179 | mainboard_romstage_entry(bist); |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 180 | |
| 181 | /* Check the stack. */ |
| 182 | for (i = 0; i < num_guards; i++) { |
| 183 | if (stack_base[i] == stack_guard) |
| 184 | continue; |
| 185 | printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n"); |
| 186 | } |
| 187 | |
Aaron Durbin | 38d9423 | 2013-02-07 00:03:33 -0600 | [diff] [blame] | 188 | /* Get the stack to use after cache-as-ram is torn down. */ |
| 189 | romstage_stack_after_car = setup_romstage_stack_after_car(); |
| 190 | |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 191 | #if CONFIG_CONSOLE_CBMEM |
| 192 | /* Keep this the last thing this function does. */ |
| 193 | cbmemc_reinit(); |
| 194 | #endif |
Aaron Durbin | 38d9423 | 2013-02-07 00:03:33 -0600 | [diff] [blame] | 195 | |
| 196 | return romstage_stack_after_car; |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 197 | } |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 198 | |
| 199 | void romstage_common(const struct romstage_params *params) |
| 200 | { |
Aaron Durbin | bf396ff | 2013-02-11 21:50:35 -0600 | [diff] [blame] | 201 | int boot_mode; |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 202 | int wake_from_s3; |
Aaron Durbin | bf396ff | 2013-02-11 21:50:35 -0600 | [diff] [blame] | 203 | struct romstage_handoff *handoff; |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 204 | |
| 205 | #if CONFIG_COLLECT_TIMESTAMPS |
| 206 | tsc_t start_romstage_time; |
| 207 | tsc_t before_dram_time; |
| 208 | tsc_t after_dram_time; |
| 209 | tsc_t base_time = { |
| 210 | .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), |
| 211 | .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) |
| 212 | }; |
| 213 | #endif |
| 214 | |
| 215 | #if CONFIG_COLLECT_TIMESTAMPS |
| 216 | start_romstage_time = rdtsc(); |
| 217 | #endif |
| 218 | |
| 219 | if (params->bist == 0) |
| 220 | enable_lapic(); |
| 221 | |
| 222 | wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config); |
| 223 | |
| 224 | /* Halt if there was a built in self test failure */ |
| 225 | report_bist_failure(params->bist); |
| 226 | |
| 227 | /* Perform some early chipset initialization required |
| 228 | * before RAM initialization can work |
| 229 | */ |
| 230 | haswell_early_initialization(HASWELL_MOBILE); |
| 231 | printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n"); |
| 232 | |
| 233 | if (wake_from_s3) { |
| 234 | #if CONFIG_HAVE_ACPI_RESUME |
| 235 | printk(BIOS_DEBUG, "Resume from S3 detected.\n"); |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 236 | #else |
| 237 | printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); |
Aaron Durbin | bf396ff | 2013-02-11 21:50:35 -0600 | [diff] [blame] | 238 | wake_from_s3 = 0; |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 239 | #endif |
| 240 | } |
| 241 | |
Aaron Durbin | bf396ff | 2013-02-11 21:50:35 -0600 | [diff] [blame] | 242 | /* There are hard coded assumptions of 2 meaning s3 wake. Normalize |
| 243 | * the users of the 2 literal here based off wake_from_s3. */ |
| 244 | boot_mode = wake_from_s3 ? 2 : 0; |
| 245 | |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 246 | /* Prepare USB controller early in S3 resume */ |
Aaron Durbin | bf396ff | 2013-02-11 21:50:35 -0600 | [diff] [blame] | 247 | if (wake_from_s3) |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 248 | enable_usb_bar(); |
| 249 | |
| 250 | post_code(0x3a); |
| 251 | params->pei_data->boot_mode = boot_mode; |
| 252 | #if CONFIG_COLLECT_TIMESTAMPS |
| 253 | before_dram_time = rdtsc(); |
| 254 | #endif |
| 255 | |
| 256 | report_platform_info(); |
| 257 | |
| 258 | sdram_initialize(params->pei_data); |
| 259 | |
| 260 | #if CONFIG_COLLECT_TIMESTAMPS |
| 261 | after_dram_time = rdtsc(); |
| 262 | #endif |
| 263 | post_code(0x3b); |
| 264 | |
| 265 | intel_early_me_status(); |
| 266 | |
| 267 | quick_ram_check(); |
| 268 | post_code(0x3e); |
| 269 | |
Aaron Durbin | c0cbd6e | 2013-03-13 13:51:20 -0500 | [diff] [blame] | 270 | if (!wake_from_s3) { |
| 271 | cbmem_initialize_empty(); |
| 272 | /* Save data returned from MRC on non-S3 resumes. */ |
Aaron Durbin | 2ad1dba | 2013-02-07 00:51:18 -0600 | [diff] [blame] | 273 | save_mrc_data(params->pei_data); |
Aaron Durbin | c0cbd6e | 2013-03-13 13:51:20 -0500 | [diff] [blame] | 274 | } else if (cbmem_initialize()) { |
| 275 | #if CONFIG_HAVE_ACPI_RESUME |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 276 | /* Failed S3 resume, reset to come up cleanly */ |
Aaron Durbin | b86113f | 2013-02-19 08:59:16 -0600 | [diff] [blame] | 277 | reset_system(); |
Aaron Durbin | c0cbd6e | 2013-03-13 13:51:20 -0500 | [diff] [blame] | 278 | #endif |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 279 | } |
Aaron Durbin | bf396ff | 2013-02-11 21:50:35 -0600 | [diff] [blame] | 280 | |
| 281 | handoff = romstage_handoff_find_or_add(); |
| 282 | if (handoff != NULL) |
| 283 | handoff->s3_resume = wake_from_s3; |
| 284 | else |
| 285 | printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); |
| 286 | |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 287 | post_code(0x3f); |
| 288 | #if CONFIG_CHROMEOS |
| 289 | init_chromeos(boot_mode); |
| 290 | #endif |
| 291 | #if CONFIG_COLLECT_TIMESTAMPS |
| 292 | timestamp_init(base_time); |
| 293 | timestamp_add(TS_START_ROMSTAGE, start_romstage_time ); |
| 294 | timestamp_add(TS_BEFORE_INITRAM, before_dram_time ); |
| 295 | timestamp_add(TS_AFTER_INITRAM, after_dram_time ); |
| 296 | timestamp_add_now(TS_END_ROMSTAGE); |
| 297 | #endif |
| 298 | } |
Aaron Durbin | 7492ec1 | 2013-02-08 22:18:04 -0600 | [diff] [blame] | 299 | |
| 300 | static inline void prepare_for_resume(void) |
| 301 | { |
Aaron Durbin | e2d9e5b | 2013-02-08 17:38:35 -0600 | [diff] [blame] | 302 | /* Only need to save memory when ramstage isn't relocatable. */ |
| 303 | #if !CONFIG_RELOCATABLE_RAMSTAGE |
Aaron Durbin | 7492ec1 | 2013-02-08 22:18:04 -0600 | [diff] [blame] | 304 | #if CONFIG_HAVE_ACPI_RESUME |
Aaron Durbin | bf396ff | 2013-02-11 21:50:35 -0600 | [diff] [blame] | 305 | struct romstage_handoff *handoff = romstage_handoff_find_or_add(); |
| 306 | |
Aaron Durbin | 7492ec1 | 2013-02-08 22:18:04 -0600 | [diff] [blame] | 307 | /* Back up the OS-controlled memory where ramstage will be loaded. */ |
Aaron Durbin | bf396ff | 2013-02-11 21:50:35 -0600 | [diff] [blame] | 308 | if (handoff != NULL && handoff->s3_resume) { |
Aaron Durbin | 7492ec1 | 2013-02-08 22:18:04 -0600 | [diff] [blame] | 309 | void *src = (void *)CONFIG_RAMBASE; |
Aaron Durbin | bf396ff | 2013-02-11 21:50:35 -0600 | [diff] [blame] | 310 | void *dest = cbmem_find(CBMEM_ID_RESUME); |
| 311 | if (dest != NULL) |
| 312 | memcpy(dest, src, HIGH_MEMORY_SAVE); |
Aaron Durbin | 7492ec1 | 2013-02-08 22:18:04 -0600 | [diff] [blame] | 313 | } |
| 314 | #endif |
Aaron Durbin | e2d9e5b | 2013-02-08 17:38:35 -0600 | [diff] [blame] | 315 | #endif |
Aaron Durbin | 7492ec1 | 2013-02-08 22:18:04 -0600 | [diff] [blame] | 316 | } |
| 317 | |
| 318 | void romstage_after_car(void) |
| 319 | { |
| 320 | prepare_for_resume(); |
| 321 | /* Load the ramstage. */ |
| 322 | copy_and_run(0); |
| 323 | } |
Aaron Durbin | f7cdfe5 | 2013-02-16 00:05:52 -0600 | [diff] [blame] | 324 | |
| 325 | |
| 326 | #if CONFIG_RELOCATABLE_RAMSTAGE |
| 327 | void cache_loaded_ramstage(struct romstage_handoff *handoff, |
Aaron Durbin | c0cbd6e | 2013-03-13 13:51:20 -0500 | [diff] [blame] | 328 | const struct cbmem_entry *ramstage, |
Aaron Durbin | f7cdfe5 | 2013-02-16 00:05:52 -0600 | [diff] [blame] | 329 | void *entry_point) |
| 330 | { |
| 331 | struct ramstage_cache *cache; |
| 332 | uint32_t total_size; |
Aaron Durbin | c0cbd6e | 2013-03-13 13:51:20 -0500 | [diff] [blame] | 333 | uint32_t ramstage_size; |
| 334 | void *ramstage_base; |
| 335 | |
| 336 | ramstage_size = cbmem_entry_size(ramstage); |
| 337 | ramstage_base = cbmem_entry_start(ramstage); |
Aaron Durbin | f7cdfe5 | 2013-02-16 00:05:52 -0600 | [diff] [blame] | 338 | |
| 339 | /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. |
| 340 | * The top of ram is defined to be the TSEG base address. */ |
| 341 | cache = (void *)(get_top_of_ram() + RESERVED_SMM_OFFSET); |
| 342 | total_size = sizeof(*cache) + ramstage_size; |
| 343 | if (total_size > RESERVED_SMM_SIZE) { |
| 344 | printk(BIOS_DEBUG, "0x%08x > RESERVED_SMM_SIZE (0x%08x)\n", |
| 345 | total_size, RESERVED_SMM_SIZE); |
| 346 | /* Nuke whatever may be there now just in case. */ |
| 347 | cache->magic = ~RAMSTAGE_CACHE_MAGIC; |
| 348 | return; |
| 349 | } |
| 350 | |
| 351 | cache->magic = RAMSTAGE_CACHE_MAGIC; |
| 352 | cache->entry_point = (uint32_t)entry_point; |
| 353 | cache->load_address = (uint32_t)ramstage_base; |
| 354 | cache->size = ramstage_size; |
| 355 | |
| 356 | printk(BIOS_DEBUG, "Saving ramstage to SMM space cache.\n"); |
| 357 | |
| 358 | /* Copy over the program. */ |
| 359 | memcpy(&cache->program[0], ramstage_base, ramstage_size); |
| 360 | |
Aaron Durbin | f7cdfe5 | 2013-02-16 00:05:52 -0600 | [diff] [blame] | 361 | if (handoff == NULL) |
| 362 | return; |
| 363 | |
Aaron Durbin | f7cdfe5 | 2013-02-16 00:05:52 -0600 | [diff] [blame] | 364 | handoff->ramstage_entry_point = (uint32_t)entry_point; |
| 365 | } |
| 366 | |
Aaron Durbin | c0cbd6e | 2013-03-13 13:51:20 -0500 | [diff] [blame] | 367 | void *load_cached_ramstage(struct romstage_handoff *handoff, |
| 368 | const struct cbmem_entry *ramstage) |
Aaron Durbin | f7cdfe5 | 2013-02-16 00:05:52 -0600 | [diff] [blame] | 369 | { |
| 370 | struct ramstage_cache *cache; |
| 371 | |
| 372 | /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. |
| 373 | * The top of ram is defined to be the TSEG base address. */ |
| 374 | cache = (void *)(get_top_of_ram() + RESERVED_SMM_OFFSET); |
| 375 | |
| 376 | if (cache->magic != RAMSTAGE_CACHE_MAGIC) { |
| 377 | printk(BIOS_DEBUG, "Invalid ramstage cache found.\n"); |
Aaron Durbin | b86113f | 2013-02-19 08:59:16 -0600 | [diff] [blame] | 378 | #if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE |
| 379 | reset_system(); |
| 380 | #endif |
Aaron Durbin | f7cdfe5 | 2013-02-16 00:05:52 -0600 | [diff] [blame] | 381 | return NULL; |
| 382 | } |
| 383 | |
| 384 | printk(BIOS_DEBUG, "Loading ramstage from SMM space cache.\n"); |
| 385 | |
| 386 | memcpy((void *)cache->load_address, &cache->program[0], cache->size); |
| 387 | |
| 388 | return (void *)cache->entry_point; |
| 389 | } |
| 390 | #endif |